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Fri, 26 May 2023 17:28:59 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id AC9FF23C6AC; Fri, 26 May 2023 17:28:59 +0200 (CEST) Received: from LMECWL1299 (10.201.28.137) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 26 May 2023 17:28:57 +0200 From: To: 'Marek Vasut' , CC: Alexandre TORGUE - foss , 'Conor Dooley' , 'Krzysztof Kozlowski' , 'Maxime Coquelin' , 'Rob Herring' , 'Srinivas Kandagatla' , , , References: <20230517152513.27922-1-marex@denx.de> <20230517152513.27922-3-marex@denx.de> In-Reply-To: <20230517152513.27922-3-marex@denx.de> Subject: RE: [PATCH v2 3/3] ARM: dts: stm32: Add nvmem-syscon node to TAMP to expose boot count on DHSOM Date: Fri, 26 May 2023 17:28:51 +0200 Message-ID: <02ca01d98fe6$ca371d80$5ea55880$@foss.st.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 16.0 Content-Language: en-us Thread-Index: AQHZj9Uh86Xh97Obl0G0KFWD/onRSq9skNqA msip_labels: MSIP_Label_23add6c0-cfdb-4bb9-b90f-bf23b83aa6c0_Enabled=true; MSIP_Label_23add6c0-cfdb-4bb9-b90f-bf23b83aa6c0_SetDate=2023-05-26T15:28:51Z; MSIP_Label_23add6c0-cfdb-4bb9-b90f-bf23b83aa6c0_Method=Standard; MSIP_Label_23add6c0-cfdb-4bb9-b90f-bf23b83aa6c0_Name=23add6c0-cfdb-4bb9-b90f-bf23b83aa6c0; MSIP_Label_23add6c0-cfdb-4bb9-b90f-bf23b83aa6c0_SiteId=75e027c9-20d5-47d5-b82f-77d7cd041e8f; MSIP_Label_23add6c0-cfdb-4bb9-b90f-bf23b83aa6c0_ActionId=d91f1318-ed6d-4299-a9f2-97d9fb285e39; MSIP_Label_23add6c0-cfdb-4bb9-b90f-bf23b83aa6c0_ContentBits=2 X-Originating-IP: [10.201.28.137] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-26_06,2023-05-25_03,2023-05-22_02 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Marek, > From: Marek Vasut > Sent: Wednesday, May 17, 2023 5:25 PM > Subject: [PATCH v2 3/3] ARM: dts: stm32: Add nvmem-syscon node to TAMP = to > expose boot count on DHSOM >=20 > Add nvmem-syscon subnode to expose TAMP_BKPxR register 19 to user = space. > This register contains U-Boot boot counter, by exposing it to user = space the user > space can reset the boot counter. >=20 > Read access example: > " > $ hexdump -vC /sys/bus/nvmem/devices/5c00a000.tamp\:nvmem0/nvmem > 00000000 0c 00 c4 b0 > " >=20 > Signed-off-by: Marek Vasut > --- > Cc: Alexandre Torgue > Cc: Conor Dooley > Cc: Krzysztof Kozlowski > Cc: Marek Vasut > Cc: Maxime Coquelin > Cc: Rob Herring > Cc: Srinivas Kandagatla > Cc: devicetree@vger.kernel.org > Cc: kernel@dh-electronics.com > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-stm32@st-md-mailman.stormreply.com > --- > V2: No change > --- > arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 11 +++++++++++ > arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi | 11 +++++++++++ > 2 files changed, 22 insertions(+) >=20 > diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi > b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi > index 74735552f4803..b2557bb718f52 100644 > --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi > +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi > @@ -537,6 +537,17 @@ &sdmmc3 { > status =3D "okay"; > }; >=20 > +&tamp { > + #address-cells =3D <1>; > + #size-cells =3D <1>; > + > + /* Boot counter */ > + nvmem { > + compatible =3D "nvmem-syscon"; > + reg =3D <0x14c 0x4>; > + }; > +}; > + > &uart4 { > pinctrl-names =3D "default"; > pinctrl-0 =3D <&uart4_pins_a>; > diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi > b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi > index bba19f21e5277..864960387e634 100644 > --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi > +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi > @@ -269,3 +269,14 @@ &rng1 { > &rtc { > status =3D "okay"; > }; > + > +&tamp { > + #address-cells =3D <1>; > + #size-cells =3D <1>; > + > + /* Boot counter */ > + nvmem { According binding you need to add "@" =3D> nvmem@14c And you export only TAMP_BKP19R directly in a nvmem region ? > + compatible =3D "nvmem-syscon"; > + reg =3D <0x14c 0x4>; > + }; > +}; the boot counter could be a nvem cell so you could expose other backup = registers=20 For example : &tamp { #address-cells =3D <1>; #size-cells =3D <1>; nvmem@14c { compatible =3D "nvmem-syscon"; reg =3D <0x14c 0x4>; /* Data cells */ boot_counter: boot-counter@14c { reg =3D <0x14c 0x4>; }; }; }; Even if you export more backup register the cell will be correctly = described in DT and could be accessible directly with sysfs without managed offset in = userland with https://lore.kernel.org/lkml/202305240724.z3McDuYM-lkp@intel.com/T/ Or previous serie = https://lore.kernel.org/lkml/20211220064730.28806-1-zajec5@gmail.com/ for example to export all the free register: Reference: https://wiki.st.com/stm32mpu/wiki/STM32MP15_backup_registers the cell " boot-counter" will be always available for users. &tamp { #address-cells =3D <1>; #size-cells =3D <1>; /* backup register: 10 to 21 */ nvmem@0x128 { compatible =3D "nvmem-syscon"; reg =3D <0x128 0x44>; /* Data cells */ boot_counter: boot-counter@14c { reg =3D <0x14c 0x4>; }; boot_mode: boot-mode@150 { reg =3D <0x150 0x4>; }; .... }; }; Patrick > -- > 2.39.2 ST Restricted