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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id p9-20020a2e7409000000b002bfe8537f37sm3633373ljc.33.2023.10.12.09.41.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Oct 2023 09:42:04 -0700 (PDT) Message-ID: <02de745f-d648-497d-b520-712450f4ad9c@linaro.org> Date: Thu, 12 Oct 2023 18:41:44 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v13 10/10] arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb controller Content-Language: en-US To: Krishna Kurapati , Thinh Nguyen , Greg Kroah-Hartman , Philipp Zabel , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Felipe Balbi , Wesley Cheng , Johan Hovold Cc: linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, quic_pkondeti@quicinc.com, quic_ppratap@quicinc.com, quic_jackp@quicinc.com, ahalaney@redhat.com, quic_shazhuss@quicinc.com References: <20231007154806.605-1-quic_kriskura@quicinc.com> <20231007154806.605-11-quic_kriskura@quicinc.com> From: Konrad Dybcio In-Reply-To: <20231007154806.605-11-quic_kriskura@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=1.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: * X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net On 10/7/23 17:48, Krishna Kurapati wrote: > From: Andrew Halaney > > There is now support for the multiport USB controller this uses so > enable it. > > The board only has a single port hooked up (despite it being wired up to > the multiport IP on the SoC). There's also a USB 2.0 mux hooked up, > which by default on boot is selected to mux properly. Grab the gpio > controlling that and ensure it stays in the right position so USB 2.0 > continues to be routed from the external port to the SoC. > > Co-developed-by: Andrew Halaney > Signed-off-by: Andrew Halaney > [Krishna: Rebased on top of usb-next] > Co-developed-by: Krishna Kurapati > Signed-off-by: Krishna Kurapati > --- > arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts > index b04f72ec097c..6904a4c201ff 100644 > --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts > +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts > @@ -503,6 +503,18 @@ &usb_2_qmpphy0 { > status = "okay"; > }; > > +&usb_2 { > + pinctrl-0 = <&usb2_en_state>; > + pinctrl-names = "default"; > + > + status = "okay"; > +}; > + > +&usb_2_dwc3 { These additions are not quite sorted alphabetically, it seems > + phy-names = "usb2-port0", "usb3-port0"; > + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>; property property-names With that: Reviewed-by: Konrad Dybcio Konrad