From: Yu Tu <yu.tu@amlogic.com>
To: Jerome Brunet <jbrunet@baylibre.com>, <linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-amlogic@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Neil Armstrong <narmstrong@baylibre.com>,
Kevin Hilman <khilman@baylibre.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Subject: Re: [PATCH V2 0/3] Add S4 SoC clock controller driver
Date: Thu, 28 Jul 2022 16:06:25 +0800 [thread overview]
Message-ID: <032b3c3f-f899-bf53-ecbb-35191d39392b@amlogic.com> (raw)
In-Reply-To: <1j8rodhfn9.fsf@starbuckisacylon.baylibre.com>
Hi JB,
On 2022/7/28 15:08, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
>
> On Thu 28 Jul 2022 at 13:41, Yu Tu <yu.tu@amlogic.com> wrote:
>
>> 1. Add clock controller driver for S4 SOC.
>>
>> Yu Tu (3):
>> dt-bindings: clk: meson: add S4 SoC clock controller bindings
>> arm64: dts: meson: add S4 Soc clock controller in DT
>> clk: meson: s4: add s4 SoC clock controller driver
>>
>> V1 -> V2: Change format as discussed in the email.
>>
>> Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/
>>
>> .../bindings/clock/amlogic,gxbb-clkc.txt | 1 +
>> MAINTAINERS | 1 +
>> arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 11 +
>> drivers/clk/meson/Kconfig | 15 +
>> drivers/clk/meson/Makefile | 1 +
>> drivers/clk/meson/s4.c | 4732 +++++++++++++++++
>> drivers/clk/meson/s4.h | 296 ++
>> include/dt-bindings/clock/s4-clkc.h | 146 +
>> 8 files changed, 5203 insertions(+)
>> create mode 100644 drivers/clk/meson/s4.c
>> create mode 100644 drivers/clk/meson/s4.h
>> create mode 100644 include/dt-bindings/clock/s4-clkc.h
>>
>>
>> base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6
>
> Please don't post until you have addressed *ALL* the comments from the
> previous version.
The last email asked you to adopt A1 method, but you did not reply?
>
> At first glance, I can see that this is still a single driver for
> what is obviously 2 controllers with 2 register spaces. Simple comments
> like the "<< 2" in the register declaration have not been addressed either.
I understand that this should be a controller, just two address
descriptions. One is the various PLL registers and one is the clock for
the peripherals. And PLL is to provide a clock source for various
peripheral clocks. So a clock controller is reasonable. I think you got
it wrong.
Ok, if you insist on using two clock controllers,, please provide your
the reason and example code?
>
> Seeing that, I have not reviewed this version further.
> I won't until all the comments from v1 are either addressed or answer
>
> Regards
> Jerome
>
> .
next prev parent reply other threads:[~2022-07-28 8:06 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-28 5:41 [PATCH V2 0/3] Add S4 SoC clock controller driver Yu Tu
2022-07-28 5:42 ` [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings Yu Tu
2022-07-28 8:41 ` Krzysztof Kozlowski
2022-07-28 8:50 ` Jerome Brunet
2022-07-28 9:02 ` Krzysztof Kozlowski
2022-07-28 9:09 ` Jerome Brunet
2022-07-28 9:48 ` Krzysztof Kozlowski
2022-07-28 9:54 ` Jerome Brunet
2022-07-28 10:07 ` Krzysztof Kozlowski
2022-07-28 10:05 ` Yu Tu
2022-07-28 10:09 ` Krzysztof Kozlowski
2022-07-28 10:19 ` Yu Tu
2022-07-28 11:48 ` Jerome Brunet
2022-07-29 5:51 ` Yu Tu
2022-07-28 5:42 ` [PATCH V2 2/3] arm64: dts: meson: add S4 Soc clock controller in DT Yu Tu
2022-07-28 5:42 ` [PATCH V2 3/3] clk: meson: s4: add s4 SoC clock controller driver Yu Tu
2022-07-28 7:08 ` [PATCH V2 0/3] Add S4 " Jerome Brunet
2022-07-28 8:06 ` Yu Tu [this message]
2022-07-28 8:14 ` Yu Tu
2022-07-28 8:27 ` Jerome Brunet
2022-07-28 8:55 ` Yu Tu
2022-07-28 9:03 ` Jerome Brunet
2022-07-28 9:52 ` Yu Tu
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