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Thu, 24 Sep 2026 02:02:21 -0700 (PDT) X-Received: by 2002:a05:7022:3c86:b0:143:31ea:ebc2 with SMTP id a92af1059eb24-14503fc189bmr1394073c88.6.1790240540943; Thu, 24 Sep 2026 02:02:20 -0700 (PDT) Received: from [10.217.217.68] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33e95c7bf6bsm11632619eec.8.2026.09.24.02.02.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 24 Sep 2026 02:02:20 -0700 (PDT) Message-ID: <039ff147-713c-49b1-9d66-1901f4eeae56@oss.qualcomm.com> Date: Thu, 24 Sep 2026 14:32:14 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] clk: qcom: Add lpass audio clock controller driver for Glymur To: Srinivas Kandagatla , Bjorn Andersson , Stephen Boyd , Krzysztof Kozlowski , Rob Herring , Conor Dooley Cc: Abel Vesa , Brian Masney , Jerome Brunet , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260922184425.56114-1-srinivas.kandagatla@oss.qualcomm.com> <20260922184425.56114-4-srinivas.kandagatla@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: <20260922184425.56114-4-srinivas.kandagatla@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: sFDZ5dVwbhUPIZKLfSBkj-2kIx2oqg7L X-Proofpoint-ORIG-GUID: sFDZ5dVwbhUPIZKLfSBkj-2kIx2oqg7L X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI0MDAzNyBTYWx0ZWRfXzHjEutXxxsFX RNrSSj7xeO7YnPRHOEhOYNp5Ygn73xxWSNQRTYloo4OGa7pHSNj7ccddY9sorLz4NdxiGDwJX0R 3Abt9rMxlwRD4HJxwddRqyYCOkd6LH5+mB2+pReiORKvTMioQh/JU9byJY1FYtchENqk/Ldprta /itwh+1H94NEi7gcl4WBBm4nBHY+qvv4FzJO618nnLQ+RUP/HBeYSgzPDImrpjgG168k9AnmCfR Cm2PGebfp8BfcJbrp7Ax/IKsaI5oOABfl81eEg79KBdn0H19FQe5Hp61GPUUi17V1wofeclbgMi dEHgKuhPUI1ZPYlCh7qJXLYP963EAo729Z4kG8mVVkKfaB5xVSzMxj8o1wKz3YnvgLJdcxfXxdV DcMehUgsg4UnOWN2TIVmSpLxvKrXtGafeU+oybrlzLddcsBdieUAbq7wFzFln+XyK/9NA1GIigi mv45+mYcHjAh81gafLw== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI0MDAzNyBTYWx0ZWRfX7FYpg5V65VJB Q3ZmflQ3WosjhPnz+ZbwLfK/gioLI8TSxb0wK2aXP9bv/DBqExJYQmamaLYEKuyal+S8bQllq7T 2mLXUBdYQHoAg4L7iX8YuPkPUPzD16A= X-Authority-Analysis: v=2.4 cv=f7vdl+yM c=1 sm=1 tr=0 ts=6ab4e71e cx=c_pps a=kVLUcbK0zfr7ocalXnG1qA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=bxHXvwVPidUU7III3fYA:9 a=QEXdDO2ut3YA:10 a=vr4QvYf-bLy2KjpDp97w:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-24_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 bulkscore=0 impostorscore=0 adultscore=0 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609240037 On 9/23/2026 12:14 AM, Srinivas Kandagatla wrote: > Add support for the lpass audio clock controller found on Glymur based > devices. This would allow lpass peripheral loader drivers to control the > clocks and bring the subsystems out of reset. > > Currently this patch only supports resets as the Q6DSP is in control of > LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg > channel. > > Signed-off-by: Srinivas Kandagatla > --- > drivers/clk/qcom/Kconfig | 11 +++++ > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/lpasscc-glymur.c | 70 +++++++++++++++++++++++++++++++ > 3 files changed, 82 insertions(+) > create mode 100644 drivers/clk/qcom/lpasscc-glymur.c > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index b3ffe1dced01..1e571c237fc1 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -1253,6 +1253,17 @@ config SC_LPASSCC_8280XP > Say Y if you want to use the LPASS branch clocks of the LPASS clock > controller to reset the LPASS subsystem. > > +config SC_LPASSCC_GLYMUR > + tristate "GLYMUR Low Power Audio Subsystem (LPASS) Clock Controller" > + depends on ARM64 || COMPILE_TEST > + default m if ARCH_QCOM > + help > + Support for the LPASS clock controller on Glymur devices. > + Say Y if you want to use the LPASS branch clocks of the LPASS clock > + controller to reset the LPASS subsystem. Required for the LPASS > + audio macros and the SoundWire compute-mode controller to leave > + reset on Glymur. > + > config SC_LPASS_CORECC_7180 > tristate "SC7180 LPASS Core Clock Controller" > depends on ARM64 || COMPILE_TEST > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > index a6c676f68b79..c8348218b6b8 100644 > --- a/drivers/clk/qcom/Makefile > +++ b/drivers/clk/qcom/Makefile > @@ -149,6 +149,7 @@ obj-$(CONFIG_SC_LPASSCC_7280) += lpasscc-sc7280.o > obj-$(CONFIG_SC_LPASSCC_8280XP) += lpasscc-sc8280xp.o > obj-$(CONFIG_SC_LPASS_CORECC_7180) += lpasscorecc-sc7180.o > obj-$(CONFIG_SC_LPASS_CORECC_7280) += lpasscorecc-sc7280.o lpassaudiocc-sc7280.o > +obj-$(CONFIG_SC_LPASSCC_GLYMUR) += lpasscc-glymur.o > obj-$(CONFIG_SC_VIDEOCC_7180) += videocc-sc7180.o > obj-$(CONFIG_SC_VIDEOCC_7280) += videocc-sc7280.o > obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o > diff --git a/drivers/clk/qcom/lpasscc-glymur.c b/drivers/clk/qcom/lpasscc-glymur.c > new file mode 100644 > index 000000000000..97fc099983b6 > --- /dev/null > +++ b/drivers/clk/qcom/lpasscc-glymur.c > @@ -0,0 +1,70 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +#include > +#include > +#include > +#include Please remove. > +#include > +#include please remove. > +#include > +#include > + > +#include > + > +#include "common.h" > +#include "reset.h" > + > +static const struct qcom_reset_map lpass_audiocc_glymur_resets[] = { > + [LPASS_AUDIO_SWR_RX_CGCR] = { 0xA0, 1 }, > + [LPASS_AUDIO_SWR_WSA1_CGCR] = { 0xB0, 1 }, > + [LPASS_AUDIO_SWR_WSA2_CGCR] = { 0xD8, 1 }, > + [LPASS_AUDIO_SWR_WSA3_CGCR] = { 0x300C, 1 }, > + [LPASS_AUDIO_SWR_WSA4_CGCR] = { 0x301C, 1 }, lower case please. > +}; > + > +static const struct regmap_config lpass_audiocc_glymur_regmap_config = { > + .reg_bits = 32, > + .reg_stride = 4, > + .val_bits = 32, > + .name = "lpass-audio-csr", > + .max_register = 0x1000, > +}; > + > +static const struct qcom_cc_desc lpass_audiocc_glymur_reset_desc = { > + .config = &lpass_audiocc_glymur_regmap_config, > + .resets = lpass_audiocc_glymur_resets, > + .num_resets = ARRAY_SIZE(lpass_audiocc_glymur_resets), > +}; > + > +static const struct of_device_id lpasscc_glymur_match_table[] = { > + { > + .compatible = "qcom,glymur-lpassaudiocc", > + .data = &lpass_audiocc_glymur_reset_desc, > + }, > + { } > +}; > +MODULE_DEVICE_TABLE(of, lpasscc_glymur_match_table); > + > +static int lpasscc_glymur_probe(struct platform_device *pdev) > +{ > + const struct qcom_cc_desc *desc = of_device_get_match_data(&pdev->dev); > + > + return qcom_cc_probe_by_index(pdev, 0, desc); > +} > + > +static struct platform_driver lpasscc_glymur_driver = { > + .probe = lpasscc_glymur_probe, > + .driver = { > + .name = "lpasscc-glymur", > + .of_match_table = lpasscc_glymur_match_table, > + }, > +}; > + > +module_platform_driver(lpasscc_glymur_driver); > + > +MODULE_AUTHOR("Srinivas Kandagatla "); > +MODULE_DESCRIPTION("QTI LPASSCC Glymur Driver"); > +MODULE_LICENSE("GPL"); -- Thanks, Taniya Das