From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10F7815B13C; Sat, 28 Sep 2024 08:19:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727511547; cv=none; b=INvAy8sS4kz5Vu1EeSfYz4AIzcp9CfK5TYI49GEX+mNeHwkcvgKLnqdrD6hjvMyIYHuQnAjIcKoM5qj8uZIZlmFdcbbd4gOtZEa2xOtVGpQ1yYZVqrCTKuLBb4A2hZzBOXqKWvoU0Rkr7Yk3pmQS22ShR2jQvKvIlu9/cN7dSZU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727511547; c=relaxed/simple; bh=t95Q70yzSXRniYkGguehvKbeFe1PNoF1YMFWI2TbiNs=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=WKH6vEJ1EZtJwisWXS6OWpVZtUPTdwwxvM2wAq4NyjclaWR6kiW3+FPNMSYH+U49c8hhyho3rBaUhJ2+3KhdZ/XAU9bK0aKRoyNj/SGigecxqXiwshp4wc6SPDKOpSHuq3ny7Pl21vdStsQrm4mh9CphokIiA90vbBsdnLJKwQk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=m41TU5Kv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="m41TU5Kv" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 67814C4CEC3; Sat, 28 Sep 2024 08:19:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727511546; bh=t95Q70yzSXRniYkGguehvKbeFe1PNoF1YMFWI2TbiNs=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=m41TU5KvcV8AFVgBmJpblbhxbCmSJh3FPq4AACcVd9FXnSIa4V1awFedSKcuJe7Ki wi087SYdbAMXN6fV6cDwdHgxXD3vya/U/erhsJCLncXhnG7kSdC81CKJGvZfBabsfJ eyzUOn7ybqhuHO7zIRgwVxRdwn0UhC6Y8VhTZSXPnSHFlOKq97eV+ZsnXpX5jdyIBN ItbSROO0jMXFf9D/v9Nr6vCeuUwweKPDRWLmBIg1G8ZQGySSUvV8JiecHi6F1cc2AY aPdvdwQKbcPqttojEH0yyaAzkUGiVc80Huq5qNKRYyFo4HLFPkn6T1uf9nxvECnWWQ a2oP8DFtnivog== Message-ID: <03a1c7e7-c516-41ab-a668-7c6785ab1c4f@kernel.org> Date: Sat, 28 Sep 2024 10:19:01 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] dt-bindings: spi: xilinx: Add clocks & clock-names properties To: "Mahapatra, Amit Kumar" , Conor Dooley Cc: "broonie@kernel.org" , "robh@kernel.org" , "krzk+dt@kernel.org" , "conor+dt@kernel.org" , "Simek, Michal" , "linux-spi@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "git (AMD-Xilinx)" , "amitrkcian2002@gmail.com" References: <20240923123242.2101562-1-amit.kumar-mahapatra@amd.com> <20240924-impaired-starving-eef91b339f67@spud> <20240925-trapdoor-stunt-33516665fdc5@spud> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 27/09/2024 11:30, Mahapatra, Amit Kumar wrote: > Hello Conor, > > >>>> Subject: Re: [PATCH] dt-bindings: spi: xilinx: Add clocks & >>>> clock-names properties >>>> >>>> On Mon, Sep 23, 2024 at 06:02:42PM +0530, Amit Kumar Mahapatra wrote: >>>>> Include the 'clocks' and 'clock-names' properties in the AXI >>>>> Quad-SPI bindings. When the AXI4-Lite interface is enabled, the >>>>> core operates in legacy mode, maintaining backward compatibility >>>>> with version 1.00, and uses 's_axi_aclk' and 'ext_spi_clk'. For >>>>> the AXI interface, it uses 's_axi4_aclk' and 'ext_spi_clk'. >>>>> >>>>> Signed-off-by: Amit Kumar Mahapatra >>>>> --- >>>>> BRANCH: for-next >>>>> --- >>>>> .../devicetree/bindings/spi/spi-xilinx.yaml | 29 +++++++++++++++++++ >>>>> 1 file changed, 29 insertions(+) >>>>> >>>>> diff --git a/Documentation/devicetree/bindings/spi/spi-xilinx.yaml >>>>> b/Documentation/devicetree/bindings/spi/spi-xilinx.yaml >>>>> index 4beb3af0416d..9dfec195ecd4 100644 >>>>> --- a/Documentation/devicetree/bindings/spi/spi-xilinx.yaml >>>>> +++ b/Documentation/devicetree/bindings/spi/spi-xilinx.yaml >>>>> @@ -12,6 +12,25 @@ maintainers: >>>>> allOf: >>>>> - $ref: spi-controller.yaml# >>>> >>>> Please move the allOf block down to the end of the binding, after >>>> the property definitions. >>> >>> Sure, I'll take care of it in the next series >>>> >>>>> + - if: >>>>> + properties: >>>>> + compatible: >>>>> + contains: >>>>> + const: xlnx,axi-quad-spi-1.00.a >>>>> + then: >>>>> + properties: >>>>> + clock-names: >>>>> + items: >>>>> + - const: s_axi_aclk >>>>> + - const: ext_spi_clk >>>> >>>> These are all clocks, there should be no need to have "clk" in the names. >>> >>> These are the names exported by the IP and used by the DTG. >> >> So? This is a binding, not a verilog file. > > Axi Quad SPI is an FPGA-based IP, and the clock names are derived from the > IP signal names as specified in the IP documentation [1]. > We chose these names to ensure alignment with the I/O signal names listed > in Table 2-2 on page 19 of [1]. > > [1] chrome-extension://efaidnbmnnnibpcajpcglclefindmkaj/https://www.amd.com/content/dam/xilinx/support/documents/ip_documentation/axi_quad_spi/v3_2/pg153-axi-quad-spi.pdf So if hardware engineers call them "pink_pony_clk_aclk_really_clk" we should follow... - bus or axi - ext_spi or spi You have descriptions of each item to reference real signals. Conor's comment is valid - do no make it verilog file. > >> >>>>> + >>>>> + else: >>>>> + properties: >>>>> + clock-names: >>>>> + items: >>>>> + - const: s_axi4_aclk >>>>> + - const: ext_spi_clk Nah, these are the same. >>>>> + >>>>> properties: >>>>> compatible: >>>>> enum: >>>>> @@ -25,6 +44,12 @@ properties: >>>>> interrupts: >>>>> maxItems: 1 >>>>> >>>>> + clocks: >>>>> + maxItems: 2 >>>>> + >>>>> + clock-names: >>>>> + maxItems: 2 >>>>> + >>>>> xlnx,num-ss-bits: >>>>> description: Number of chip selects used. >>>>> minimum: 1 >>>>> @@ -39,6 +64,8 @@ required: >>>>> - compatible >>>>> - reg >>>>> - interrupts >>>>> + - clocks >>>>> + - clock-names >>>> >>>> New required properties are an ABI break, where is the driver patch >>>> that makes use of these clocks? >>> >>> Alright, I will remove these from the required properties to avoid >>> breaking the ABI. We're working on the driver patch and will send it >>> once it's ready. >> >> What changed to make the clocks needed now? It's possible that making them >> required is the correct thing to do, so breaking the ABI would be justified (provided >> the driver can still handle there being no clocks). > > Axi Quad SPI is an FPGA-based IP that was previously tested on MicroBlaze > soft-core systems, where the driver didn't need to enable the clock, as it > would already be enabled before the PL is loaded. However, when used > with ARM hard-core SoCs, the driver must explicitly enable the clocks, Commit msg should explain this. Including ABI break impact. Best regards, Krzysztof