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The hardware generates a fractional output frequency > from a fixed input clock (typically TCXO4) using the relation > Fout = Fin * (M / N), with duty cycle controlled by a separate D > register. The clock output is routed over a gpio controlled pin. > > Signed-off-by: Taniya Das > --- [...] > + clock-output-names: > + maxItems: 1 This should be deferred to the driver > + > + pinctrl-0: > + description: Pin configuration for the GP_MN output in the active state. > + > + pinctrl-names: > + items: > + - const: active I think these 2 are always allowed/defined > + > + assigned-clocks: > + maxItems: 1 > + description: Parent clock phandle used to set the input frequency. > + > + assigned-clock-rates: > + maxItems: 1 > + description: | > + Rate for the parent clock in Hz. > + Supported rates: 19200000, 9600000, 6400000, 4800000. Likewise, we could simply set_rate on the GCC clock which is the parent of this one, via something like CLK_SET_RATE_PARENT Konrad