* [PATCH v4 1/7] dt-bindings: loongarch: Add CPU bindings for LoongArch
2023-08-23 9:54 [PATCH v4 0/7] LoongArch: Add built-in dtb support Binbin Zhou
@ 2023-08-23 9:54 ` Binbin Zhou
2023-08-23 13:54 ` Conor Dooley
2023-08-23 9:54 ` [PATCH v4 2/7] dt-bindings: loongarch: Add Loongson SoC boards compatibles Binbin Zhou
` (6 subsequent siblings)
7 siblings, 1 reply; 19+ messages in thread
From: Binbin Zhou @ 2023-08-23 9:54 UTC (permalink / raw)
To: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree
Cc: Huacai Chen, loongson-kernel, Xuerui Wang, loongarch, Jiaxun Yang,
Hongliang Wang, Binbin Zhou
Add the available CPUs in LoongArch binding with DT schema format using
json-schema.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
.../devicetree/bindings/loongarch/cpus.yaml | 61 +++++++++++++++++++
1 file changed, 61 insertions(+)
create mode 100644 Documentation/devicetree/bindings/loongarch/cpus.yaml
diff --git a/Documentation/devicetree/bindings/loongarch/cpus.yaml b/Documentation/devicetree/bindings/loongarch/cpus.yaml
new file mode 100644
index 000000000000..f175872995e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/loongarch/cpus.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/loongarch/cpus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LoongArch CPUs
+
+maintainers:
+ - Binbin Zhou <zhoubinbin@loongson.cn>
+
+description:
+ This document describes the list of LoongArch CPU cores that support FDT,
+ it describe the layout of CPUs in a system through the "cpus" node.
+
+allOf:
+ - $ref: /schemas/cpu.yaml#
+
+properties:
+ compatible:
+ enum:
+ - loongson,la264
+ - loongson,la364
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/loongson,ls2k-clk.h>
+
+ cpus {
+ #size-cells = <0>;
+ #address-cells = <1>;
+
+ cpu@0 {
+ compatible = "loongson,la264";
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&clk LOONGSON2_NODE_CLK>;
+ };
+
+ cpu@1 {
+ compatible = "loongson,la264";
+ device_type = "cpu";
+ reg = <1>;
+ clocks = <&clk LOONGSON2_NODE_CLK>;
+ };
+ };
+
+...
--
2.39.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v4 1/7] dt-bindings: loongarch: Add CPU bindings for LoongArch
2023-08-23 9:54 ` [PATCH v4 1/7] dt-bindings: loongarch: Add CPU bindings for LoongArch Binbin Zhou
@ 2023-08-23 13:54 ` Conor Dooley
0 siblings, 0 replies; 19+ messages in thread
From: Conor Dooley @ 2023-08-23 13:54 UTC (permalink / raw)
To: Binbin Zhou
Cc: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree, Huacai Chen, loongson-kernel,
Xuerui Wang, loongarch, Jiaxun Yang, Hongliang Wang
[-- Attachment #1: Type: text/plain, Size: 289 bytes --]
On Wed, Aug 23, 2023 at 05:54:49PM +0800, Binbin Zhou wrote:
> Add the available CPUs in LoongArch binding with DT schema format using
> json-schema.
>
> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v4 2/7] dt-bindings: loongarch: Add Loongson SoC boards compatibles
2023-08-23 9:54 [PATCH v4 0/7] LoongArch: Add built-in dtb support Binbin Zhou
2023-08-23 9:54 ` [PATCH v4 1/7] dt-bindings: loongarch: Add CPU bindings for LoongArch Binbin Zhou
@ 2023-08-23 9:54 ` Binbin Zhou
2023-08-23 9:54 ` [PATCH v4 3/7] LoongArch: Allow device trees to be built into the kernel Binbin Zhou
` (5 subsequent siblings)
7 siblings, 0 replies; 19+ messages in thread
From: Binbin Zhou @ 2023-08-23 9:54 UTC (permalink / raw)
To: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree
Cc: Huacai Chen, loongson-kernel, Xuerui Wang, loongarch, Jiaxun Yang,
Hongliang Wang, Binbin Zhou, Conor Dooley
Add Loongson SoC boards binding with DT schema format using json-schema.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
.../bindings/loongarch/loongson.yaml | 34 +++++++++++++++++++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/loongarch/loongson.yaml
diff --git a/Documentation/devicetree/bindings/loongarch/loongson.yaml b/Documentation/devicetree/bindings/loongarch/loongson.yaml
new file mode 100644
index 000000000000..e1a4a97b7576
--- /dev/null
+++ b/Documentation/devicetree/bindings/loongarch/loongson.yaml
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/loongarch/loongson.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson SoC-based boards
+
+maintainers:
+ - Binbin Zhou <zhoubinbin@loongson.cn>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: Loongson-2K0500 processor based boards
+ items:
+ - const: loongson,ls2k0500-ref
+ - const: loongson,ls2k0500
+
+ - description: Loongson-2K1000 processor based boards
+ items:
+ - const: loongson,ls2k1000-ref
+ - const: loongson,ls2k1000
+
+ - description: Loongson-2K2000 processor based boards
+ items:
+ - const: loongson,ls2k2000-ref
+ - const: loongson,ls2k2000
+
+additionalProperties: true
+
+...
--
2.39.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v4 3/7] LoongArch: Allow device trees to be built into the kernel
2023-08-23 9:54 [PATCH v4 0/7] LoongArch: Add built-in dtb support Binbin Zhou
2023-08-23 9:54 ` [PATCH v4 1/7] dt-bindings: loongarch: Add CPU bindings for LoongArch Binbin Zhou
2023-08-23 9:54 ` [PATCH v4 2/7] dt-bindings: loongarch: Add Loongson SoC boards compatibles Binbin Zhou
@ 2023-08-23 9:54 ` Binbin Zhou
2023-08-23 19:42 ` Rob Herring
2023-08-23 9:55 ` [PATCH v4 4/7] LoongArch: dts: DeviceTree for Loongson-2K0500 Binbin Zhou
` (4 subsequent siblings)
7 siblings, 1 reply; 19+ messages in thread
From: Binbin Zhou @ 2023-08-23 9:54 UTC (permalink / raw)
To: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree
Cc: Huacai Chen, loongson-kernel, Xuerui Wang, loongarch, Jiaxun Yang,
Hongliang Wang, Binbin Zhou
Some systems do not provide a useful device tree to the kernel at boot
time. Let's keep a device tree table in the kernel, keyed by the dts
filename, containing the relevant DTBs.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
arch/loongarch/Kconfig | 16 ++++++++++++++++
arch/loongarch/Makefile | 10 ++++++++--
arch/loongarch/boot/dts/Makefile | 3 +--
arch/loongarch/kernel/setup.c | 9 +++++++--
4 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig
index 46b4c217da14..61febadd4fce 100644
--- a/arch/loongarch/Kconfig
+++ b/arch/loongarch/Kconfig
@@ -326,6 +326,22 @@ config 64KB_3LEVEL
endchoice
+config BUILTIN_DTB
+ bool "Enable builtin dtb in kernel"
+ depends on OF
+ help
+ Some systems do not provide a useful device tree to the kernel at boot
+ time. Let's keep a device tree table in the kernel, keyed by the dts
+ filename, containing the relevant DTBs.
+
+config BUILTIN_DTB_NAME
+ string "Source file for LoongArch builtin dtb"
+ depends on BUILTIN_DTB
+ help
+ Base name (without suffix, relative to arch/loongarch/boot/dts/)
+ for the DTS file that will be used to produce the DTB linked into the
+ kernel.
+
config CMDLINE
string "Built-in kernel command line"
help
diff --git a/arch/loongarch/Makefile b/arch/loongarch/Makefile
index fb0fada43197..abaa3df9fd6f 100644
--- a/arch/loongarch/Makefile
+++ b/arch/loongarch/Makefile
@@ -5,7 +5,8 @@
boot := arch/loongarch/boot
-KBUILD_DEFCONFIG := loongson3_defconfig
+KBUILD_DEFCONFIG := loongson3_defconfig
+KBUILD_DTBS := dtbs
image-name-y := vmlinux
image-name-$(CONFIG_EFI_ZBOOT) := vmlinuz
@@ -140,11 +141,14 @@ PHONY += vdso_install
vdso_install:
$(Q)$(MAKE) $(build)=arch/loongarch/vdso $@
-all: $(notdir $(KBUILD_IMAGE))
+all: $(notdir $(KBUILD_IMAGE)) $(KBUILD_DTBS)
vmlinux.elf vmlinux.efi vmlinuz.efi: vmlinux
$(Q)$(MAKE) $(build)=$(boot) $(bootvars-y) $(boot)/$@
+# device-trees
+core-y += arch/loongarch/boot/dts/
+
install:
$(Q)install -D -m 755 $(KBUILD_IMAGE) $(INSTALL_PATH)/$(image-name-y)-$(KERNELRELEASE)
$(Q)install -D -m 644 .config $(INSTALL_PATH)/config-$(KERNELRELEASE)
@@ -152,5 +156,7 @@ install:
define archhelp
echo ' install - install kernel into $(INSTALL_PATH)'
+ echo ' dtbs - Device-tree blobs for enabled boards'
+ echo ' dtbs_install - Install dtbs to $(INSTALL_DTBS_PATH)'
echo
endef
diff --git a/arch/loongarch/boot/dts/Makefile b/arch/loongarch/boot/dts/Makefile
index 5f1f55e911ad..1e24cdb5180a 100644
--- a/arch/loongarch/boot/dts/Makefile
+++ b/arch/loongarch/boot/dts/Makefile
@@ -1,4 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
-dtstree := $(srctree)/$(src)
-dtb-y := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts))
+obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_NAME))
diff --git a/arch/loongarch/kernel/setup.c b/arch/loongarch/kernel/setup.c
index 7783f0a3d742..e5008890beda 100644
--- a/arch/loongarch/kernel/setup.c
+++ b/arch/loongarch/kernel/setup.c
@@ -296,8 +296,13 @@ static void __init fdt_setup(void)
if (acpi_os_get_root_pointer())
return;
- /* Look for a device tree configuration table entry */
- fdt_pointer = efi_fdt_pointer();
+ /* We prefer to try to use built-in dtb, checking its legality first. */
+ if (!fdt_check_header(__dtb_start))
+ fdt_pointer = __dtb_start;
+ else
+ /* Fallback to efi dtb, when built-in dtb is not available. */
+ fdt_pointer = efi_fdt_pointer();
+
if (!fdt_pointer || fdt_check_header(fdt_pointer))
return;
--
2.39.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v4 3/7] LoongArch: Allow device trees to be built into the kernel
2023-08-23 9:54 ` [PATCH v4 3/7] LoongArch: Allow device trees to be built into the kernel Binbin Zhou
@ 2023-08-23 19:42 ` Rob Herring
2023-08-24 3:20 ` Binbin Zhou
0 siblings, 1 reply; 19+ messages in thread
From: Rob Herring @ 2023-08-23 19:42 UTC (permalink / raw)
To: Binbin Zhou
Cc: Binbin Zhou, Huacai Chen, Krzysztof Kozlowski, Conor Dooley,
devicetree, Huacai Chen, loongson-kernel, Xuerui Wang, loongarch,
Jiaxun Yang, Hongliang Wang
On Wed, Aug 23, 2023 at 05:54:51PM +0800, Binbin Zhou wrote:
> Some systems do not provide a useful device tree to the kernel at boot
> time. Let's keep a device tree table in the kernel, keyed by the dts
> filename, containing the relevant DTBs.
Support for this in other arches was added to support legacy bootloaders
with no DT support. You should not need this for a new architecture. Fix
the bootloader to provide a useful DT.
Rob
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v4 3/7] LoongArch: Allow device trees to be built into the kernel
2023-08-23 19:42 ` Rob Herring
@ 2023-08-24 3:20 ` Binbin Zhou
2023-08-25 12:00 ` Conor Dooley
0 siblings, 1 reply; 19+ messages in thread
From: Binbin Zhou @ 2023-08-24 3:20 UTC (permalink / raw)
To: Rob Herring
Cc: Binbin Zhou, Huacai Chen, Krzysztof Kozlowski, Conor Dooley,
devicetree, Huacai Chen, loongson-kernel, Xuerui Wang, loongarch,
Jiaxun Yang, Hongliang Wang
Hi Rob:
On Thu, Aug 24, 2023 at 3:42 AM Rob Herring <robh@kernel.org> wrote:
>
> On Wed, Aug 23, 2023 at 05:54:51PM +0800, Binbin Zhou wrote:
> > Some systems do not provide a useful device tree to the kernel at boot
> > time. Let's keep a device tree table in the kernel, keyed by the dts
> > filename, containing the relevant DTBs.
>
> Support for this in other arches was added to support legacy bootloaders
> with no DT support. You should not need this for a new architecture. Fix
> the bootloader to provide a useful DT.
>
Yes, our bootloader already supports DT.
Our original intention of providing kernel built-in DTS is to describe
all possible device information of that SoC, so that everyone can use
it as a reference during development; we will unlikely to add more
.dts files to the kernel besides the reference ones.
And as a reference, our built-in DTS provides the most basic bootable
combinations (so it is generic enough) as an alternative in case the
DTS in the bootloader is unexpected.
Does this make any sense?
Thanks.
Binbin
> Rob
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v4 3/7] LoongArch: Allow device trees to be built into the kernel
2023-08-24 3:20 ` Binbin Zhou
@ 2023-08-25 12:00 ` Conor Dooley
2023-08-25 15:13 ` Huacai Chen
0 siblings, 1 reply; 19+ messages in thread
From: Conor Dooley @ 2023-08-25 12:00 UTC (permalink / raw)
To: Binbin Zhou
Cc: Rob Herring, Binbin Zhou, Huacai Chen, Krzysztof Kozlowski,
Conor Dooley, devicetree, Huacai Chen, loongson-kernel,
Xuerui Wang, loongarch, Jiaxun Yang, Hongliang Wang
[-- Attachment #1: Type: text/plain, Size: 1402 bytes --]
On Thu, Aug 24, 2023 at 11:20:34AM +0800, Binbin Zhou wrote:
> Hi Rob:
>
> On Thu, Aug 24, 2023 at 3:42 AM Rob Herring <robh@kernel.org> wrote:
> >
> > On Wed, Aug 23, 2023 at 05:54:51PM +0800, Binbin Zhou wrote:
> > > Some systems do not provide a useful device tree to the kernel at boot
> > > time. Let's keep a device tree table in the kernel, keyed by the dts
> > > filename, containing the relevant DTBs.
> >
> > Support for this in other arches was added to support legacy bootloaders
> > with no DT support. You should not need this for a new architecture. Fix
> > the bootloader to provide a useful DT.
> >
> Yes, our bootloader already supports DT.
>
> Our original intention of providing kernel built-in DTS is to describe
> all possible device information of that SoC, so that everyone can use
> it as a reference during development; we will unlikely to add more
> .dts files to the kernel besides the reference ones.
>
> And as a reference, our built-in DTS provides the most basic bootable
> combinations (so it is generic enough) as an alternative in case the
> DTS in the bootloader is unexpected.
>
> Does this make any sense?
I don't see how this answers the question - as far as I can tell Rob was
asking specifically about the building the dtb into the kernel, whereas
your response seems to talk about havint the dts files in the kernel
tree.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v4 3/7] LoongArch: Allow device trees to be built into the kernel
2023-08-25 12:00 ` Conor Dooley
@ 2023-08-25 15:13 ` Huacai Chen
0 siblings, 0 replies; 19+ messages in thread
From: Huacai Chen @ 2023-08-25 15:13 UTC (permalink / raw)
To: Conor Dooley
Cc: Binbin Zhou, Rob Herring, Binbin Zhou, Huacai Chen,
Krzysztof Kozlowski, Conor Dooley, devicetree, loongson-kernel,
Xuerui Wang, loongarch, Jiaxun Yang, Hongliang Wang
Hi, Conor,
On Fri, Aug 25, 2023 at 8:01 PM Conor Dooley <conor.dooley@microchip.com> wrote:
>
> On Thu, Aug 24, 2023 at 11:20:34AM +0800, Binbin Zhou wrote:
> > Hi Rob:
> >
> > On Thu, Aug 24, 2023 at 3:42 AM Rob Herring <robh@kernel.org> wrote:
> > >
> > > On Wed, Aug 23, 2023 at 05:54:51PM +0800, Binbin Zhou wrote:
> > > > Some systems do not provide a useful device tree to the kernel at boot
> > > > time. Let's keep a device tree table in the kernel, keyed by the dts
> > > > filename, containing the relevant DTBs.
> > >
> > > Support for this in other arches was added to support legacy bootloaders
> > > with no DT support. You should not need this for a new architecture. Fix
> > > the bootloader to provide a useful DT.
> > >
> > Yes, our bootloader already supports DT.
> >
> > Our original intention of providing kernel built-in DTS is to describe
> > all possible device information of that SoC, so that everyone can use
> > it as a reference during development; we will unlikely to add more
> > .dts files to the kernel besides the reference ones.
> >
> > And as a reference, our built-in DTS provides the most basic bootable
> > combinations (so it is generic enough) as an alternative in case the
> > DTS in the bootloader is unexpected.
> >
> > Does this make any sense?
>
> I don't see how this answers the question - as far as I can tell Rob was
> asking specifically about the building the dtb into the kernel, whereas
> your response seems to talk about havint the dts files in the kernel
> tree.
I'm sorry, but from my point of view, giving users a chance to build
the reference dts file into the kernel is not a bad idea. Of course
the commit message can be improved.
Huacai
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v4 4/7] LoongArch: dts: DeviceTree for Loongson-2K0500
2023-08-23 9:54 [PATCH v4 0/7] LoongArch: Add built-in dtb support Binbin Zhou
` (2 preceding siblings ...)
2023-08-23 9:54 ` [PATCH v4 3/7] LoongArch: Allow device trees to be built into the kernel Binbin Zhou
@ 2023-08-23 9:55 ` Binbin Zhou
2023-08-23 21:11 ` Rob Herring
2023-08-23 9:55 ` [PATCH v4 5/7] LoongArch: dts: DeviceTree for Loongson-2K1000 Binbin Zhou
` (3 subsequent siblings)
7 siblings, 1 reply; 19+ messages in thread
From: Binbin Zhou @ 2023-08-23 9:55 UTC (permalink / raw)
To: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree
Cc: Huacai Chen, loongson-kernel, Xuerui Wang, loongarch, Jiaxun Yang,
Hongliang Wang, Binbin Zhou, Krzysztof Kozlowski
Add DeviceTree file for Loongson-2K0500 processor, which integrates one
64-bit dual emission superscalar LA264 processor core.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
arch/loongarch/boot/dts/Makefile | 2 +
.../boot/dts/loongson-2k0500-ref.dts | 89 ++++++
arch/loongarch/boot/dts/loongson-2k0500.dtsi | 254 ++++++++++++++++++
3 files changed, 345 insertions(+)
create mode 100644 arch/loongarch/boot/dts/loongson-2k0500-ref.dts
create mode 100644 arch/loongarch/boot/dts/loongson-2k0500.dtsi
diff --git a/arch/loongarch/boot/dts/Makefile b/arch/loongarch/boot/dts/Makefile
index 1e24cdb5180a..aa0b21d73d4e 100644
--- a/arch/loongarch/boot/dts/Makefile
+++ b/arch/loongarch/boot/dts/Makefile
@@ -1,3 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
+dtb-$(CONFIG_MACH_LOONGSON64) = loongson-2k0500-ref.dtb
+
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_NAME))
diff --git a/arch/loongarch/boot/dts/loongson-2k0500-ref.dts b/arch/loongarch/boot/dts/loongson-2k0500-ref.dts
new file mode 100644
index 000000000000..62615eeaa57b
--- /dev/null
+++ b/arch/loongarch/boot/dts/loongson-2k0500-ref.dts
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Loongson Technology Corporation Limited
+ */
+
+/dts-v1/;
+
+#include "loongson-2k0500.dtsi"
+
+/ {
+ compatible = "loongson,ls2k0500-ref", "loongson,ls2k0500";
+ model = "Loongson-2K0500 Reference Board";
+
+ aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory@200000 {
+ device_type = "memory";
+ reg = <0x0 0x200000 0x0 0xee00000>, /* 238 MB at 2 MB */
+ <0x0 0x90000000 0x0 0x60000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x2000000>;
+ linux,cma-default;
+ };
+ };
+};
+
+&gmac0 {
+ status = "okay";
+
+ phy-mode = "rgmii";
+ bus_id = <0x0>;
+};
+
+&gmac1 {
+ status = "okay";
+
+ phy-mode = "rgmii";
+ bus_id = <0x1>;
+};
+
+&i2c0 {
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ eeprom@57{
+ compatible = "atmel,24c16";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&rtc0 {
+ status = "okay";
+};
diff --git a/arch/loongarch/boot/dts/loongson-2k0500.dtsi b/arch/loongarch/boot/dts/loongson-2k0500.dtsi
new file mode 100644
index 000000000000..d1554a1cec49
--- /dev/null
+++ b/arch/loongarch/boot/dts/loongson-2k0500.dtsi
@@ -0,0 +1,254 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Loongson Technology Corporation Limited
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "loongson,la264";
+ device_type = "cpu";
+ reg = <0x0>;
+ clocks = <&cpu_clk>;
+ };
+ };
+
+ cpu_clk: cpu-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <500000000>;
+ };
+
+ cpuintc: interrupt-controller {
+ compatible = "loongson,cpu-interrupt-controller";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
+ bus@10000000 {
+ compatible = "simple-bus";
+ ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>,
+ <0x0 0x2000000 0x0 0x2000000 0x0 0x2000000>,
+ <0x0 0x20000000 0x0 0x20000000 0x0 0x10000000>,
+ <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
+ <0xfe 0x0 0xfe 0x0 0x0 0x40000000>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ isa@16400000 {
+ compatible = "isa";
+ ranges = <1 0x0 0x0 0x16400000 0x4000>;
+ #size-cells = <1>;
+ #address-cells = <2>;
+ };
+
+ liointc0: interrupt-controller@1fe11400 {
+ compatible = "loongson,liointc-2.0";
+ reg = <0x0 0x1fe11400 0x0 0x40>,
+ <0x0 0x1fe11040 0x0 0x8>;
+ reg-names = "main", "isr0";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ interrupt-names = "int0";
+
+ loongson,parent_int_map = <0xffffffff>, /* int0 */
+ <0x00000000>, /* int1 */
+ <0x00000000>, /* int2 */
+ <0x00000000>; /* int3 */
+ };
+
+ liointc1: interrupt-controller@1fe11440 {
+ compatible = "loongson,liointc-2.0";
+ reg = <0x0 0x1fe11440 0x0 0x40>,
+ <0x0 0x1fe11048 0x0 0x8>;
+ reg-names = "main", "isr0";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <4>;
+ interrupt-names = "int2";
+
+ loongson,parent_int_map = <0x00000000>, /* int0 */
+ <0x00000000>, /* int1 */
+ <0xffffffff>, /* int2 */
+ <0x00000000>; /* int3 */
+ };
+
+ eiointc: interrupt-controller@1fe11600 {
+ compatible = "loongson,ls2k0500-eiointc";
+ reg = <0x0 0x1fe11600 0x0 0xea00>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <3>;
+ };
+
+ gmac0: ethernet@1f020000 {
+ compatible = "snps,dwmac-3.70a";
+ reg = <0x0 0x1f020000 0x0 0x10000>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ status = "disable";
+ };
+
+ gmac1: ethernet@1f030000 {
+ compatible = "snps,dwmac-3.70a";
+ reg = <0x0 0x1f030000 0x0 0x10000>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ status = "disable";
+ };
+
+ sata: sata@1f040000 {
+ compatible = "snps,spear-ahci";
+ reg = <0x0 0x1f040000 0x0 0x10000>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <75>;
+ status = "disable";
+ };
+
+ ehci0: usb@1f050000 {
+ compatible = "generic-ehci";
+ reg = <0x0 0x1f050000 0x0 0x8000>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <71>;
+ status = "disable";
+ };
+
+ ohci0: usb@1f058000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0x1f058000 0x0 0x8000>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <72>;
+ status = "disable";
+ };
+
+ uart0: serial@1ff40800 {
+ compatible = "ns16550a";
+ reg = <0x0 0x1ff40800 0x0 0x10>;
+ clock-frequency = <100000000>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <2>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ i2c0: i2c@1ff48000 {
+ compatible = "loongson,ls2k-i2c";
+ reg = <0x0 0x1ff48000 0x0 0x0800>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <14>;
+ status = "disabled";
+ };
+
+ i2c@1ff48800 {
+ compatible = "loongson,ls2k-i2c";
+ reg = <0x0 0x1ff48800 0x0 0x0800>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <15>;
+ status = "disabled";
+ };
+
+ i2c@1ff49000 {
+ compatible = "loongson,ls2k-i2c";
+ reg = <0x0 0x1ff49000 0x0 0x0800>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <16>;
+ status = "disabled";
+ };
+
+ i2c@1ff49800 {
+ compatible = "loongson,ls2k-i2c";
+ reg = <0x0 0x1ff49800 0x0 0x0800>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <17>;
+ status = "disabled";
+ };
+
+ i2c@1ff4a000 {
+ compatible = "loongson,ls2k-i2c";
+ reg = <0x0 0x1ff4a000 0x0 0x0800>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <18>;
+ status = "disabled";
+ };
+
+ i2c@1ff4a800 {
+ compatible = "loongson,ls2k-i2c";
+ reg = <0x0 0x1ff4a800 0x0 0x0800>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <19>;
+ status = "disabled";
+ };
+
+ rtc0: rtc@1ff6c100 {
+ compatible = "loongson,ls2k0500-rtc", "loongson,ls7a-rtc";
+ reg = <0x0 0x1ff6c100 0x0 0x100>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <35>;
+ status = "disabled";
+ };
+
+ pcie@1a000000 {
+ compatible = "loongson,ls2k-pci";
+ reg = <0x0 0x1a000000 0x0 0x02000000>,
+ <0xfe 0x0 0x0 0x20000000>;
+
+ ranges = <0x2000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
+ <0x1000000 0x0 0x4000 0x0 0x16404000 0x0 0x4000>;
+
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ status = "disabled";
+
+ pcie@0,0 {
+ reg = <0x0000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupt-parent = <&eiointc>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &eiointc 81>;
+ ranges;
+ };
+
+ pcie@1,0 {
+ reg = <0x0800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupt-parent = <&eiointc>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &eiointc 82>;
+ ranges;
+ };
+ };
+ };
+};
--
2.39.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v4 4/7] LoongArch: dts: DeviceTree for Loongson-2K0500
2023-08-23 9:55 ` [PATCH v4 4/7] LoongArch: dts: DeviceTree for Loongson-2K0500 Binbin Zhou
@ 2023-08-23 21:11 ` Rob Herring
0 siblings, 0 replies; 19+ messages in thread
From: Rob Herring @ 2023-08-23 21:11 UTC (permalink / raw)
To: Binbin Zhou
Cc: Binbin Zhou, Huacai Chen, Krzysztof Kozlowski, Conor Dooley,
devicetree, Huacai Chen, loongson-kernel, Xuerui Wang, loongarch,
Jiaxun Yang, Hongliang Wang, Krzysztof Kozlowski
On Wed, Aug 23, 2023 at 4:55 AM Binbin Zhou <zhoubinbin@loongson.cn> wrote:
>
> Add DeviceTree file for Loongson-2K0500 processor, which integrates one
> 64-bit dual emission superscalar LA264 processor core.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> ---
> arch/loongarch/boot/dts/Makefile | 2 +
> .../boot/dts/loongson-2k0500-ref.dts | 89 ++++++
> arch/loongarch/boot/dts/loongson-2k0500.dtsi | 254 ++++++++++++++++++
> 3 files changed, 345 insertions(+)
> create mode 100644 arch/loongarch/boot/dts/loongson-2k0500-ref.dts
> create mode 100644 arch/loongarch/boot/dts/loongson-2k0500.dtsi
This introduces some warnings which don't seem to be addressed by your
fixes to loongson,liointc.yaml:
/home/rob/proj/linux-dt/.build-loongarch/arch/loongarch/boot/dts/loongson-2k0500-ref.dtb:
interrupt-controller@1fe11400: reg-names: ['main', 'isr0'] is too
short
from schema $id:
http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#
/home/rob/proj/linux-dt/.build-loongarch/arch/loongarch/boot/dts/loongson-2k0500-ref.dtb:
interrupt-controller@1fe11400: Unevaluated properties are not allowed
('reg-names' was unexpected)
from schema $id:
http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#
/home/rob/proj/linux-dt/.build-loongarch/arch/loongarch/boot/dts/loongson-2k0500-ref.dtb:
interrupt-controller@1fe11400: reg: [[0, 534844416, 0, 64], [0,
534843456, 0, 8]] is too short
from schema $id:
http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#
/home/rob/proj/linux-dt/.build-loongarch/arch/loongarch/boot/dts/loongson-2k0500-ref.dtb:
interrupt-controller@1fe11440: reg-names: ['main', 'isr0'] is too
short
from schema $id:
http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#
/home/rob/proj/linux-dt/.build-loongarch/arch/loongarch/boot/dts/loongson-2k0500-ref.dtb:
interrupt-controller@1fe11440: interrupt-names:0: 'int0' was expected
from schema $id:
http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#
/home/rob/proj/linux-dt/.build-loongarch/arch/loongarch/boot/dts/loongson-2k0500-ref.dtb:
interrupt-controller@1fe11440: Unevaluated properties are not allowed
('interrupt-names', 'reg-names' were unexpected)
from schema $id:
http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#
/home/rob/proj/linux-dt/.build-loongarch/arch/loongarch/boot/dts/loongson-2k0500-ref.dtb:
interrupt-controller@1fe11440: reg: [[0, 534844480, 0, 64], [0,
534843464, 0, 8]] is too short
from schema $id:
http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#
Rob
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v4 5/7] LoongArch: dts: DeviceTree for Loongson-2K1000
2023-08-23 9:54 [PATCH v4 0/7] LoongArch: Add built-in dtb support Binbin Zhou
` (3 preceding siblings ...)
2023-08-23 9:55 ` [PATCH v4 4/7] LoongArch: dts: DeviceTree for Loongson-2K0500 Binbin Zhou
@ 2023-08-23 9:55 ` Binbin Zhou
2023-08-23 9:55 ` [PATCH v4 6/7] LoongArch: dts: DeviceTree for Loongson-2K2000 Binbin Zhou
` (2 subsequent siblings)
7 siblings, 0 replies; 19+ messages in thread
From: Binbin Zhou @ 2023-08-23 9:55 UTC (permalink / raw)
To: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree
Cc: Huacai Chen, loongson-kernel, Xuerui Wang, loongarch, Jiaxun Yang,
Hongliang Wang, Binbin Zhou
Add DeviceTree file for Loongson-2K1000 processor, which integrates two
64-bit dual emission superscalar LA264 processor cores.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
arch/loongarch/boot/dts/Makefile | 3 +-
.../boot/dts/loongson-2k1000-ref.dts | 172 ++++++++
arch/loongarch/boot/dts/loongson-2k1000.dtsi | 397 ++++++++++++++++++
3 files changed, 571 insertions(+), 1 deletion(-)
create mode 100644 arch/loongarch/boot/dts/loongson-2k1000-ref.dts
create mode 100644 arch/loongarch/boot/dts/loongson-2k1000.dtsi
diff --git a/arch/loongarch/boot/dts/Makefile b/arch/loongarch/boot/dts/Makefile
index aa0b21d73d4e..dc0782315bed 100644
--- a/arch/loongarch/boot/dts/Makefile
+++ b/arch/loongarch/boot/dts/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
-dtb-$(CONFIG_MACH_LOONGSON64) = loongson-2k0500-ref.dtb
+dtb-$(CONFIG_MACH_LOONGSON64) = loongson-2k0500-ref.dtb \
+ loongson-2k1000-ref.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_NAME))
diff --git a/arch/loongarch/boot/dts/loongson-2k1000-ref.dts b/arch/loongarch/boot/dts/loongson-2k1000-ref.dts
new file mode 100644
index 000000000000..7468b4091268
--- /dev/null
+++ b/arch/loongarch/boot/dts/loongson-2k1000-ref.dts
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Loongson Technology Corporation Limited
+ */
+
+/dts-v1/;
+
+#include "loongson-2k1000.dtsi"
+
+/ {
+ compatible = "loongson,ls2k1000-ref", "loongson,ls2k1000";
+ model = "Loongson-2K1000 Reference Board";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory@200000 {
+ device_type = "memory";
+ reg = <0x0 0x200000 0x0 0x6e00000>,
+ <0x0 0x08000000 0x0 0x7000000>,
+ <0x0 0x90000000 0x1 0xe0000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x2000000>;
+ linux,cma-default;
+ };
+ };
+};
+
+&gmac0 {
+ status = "okay";
+
+ phy-mode = "rgmii";
+ phy-handle = <&phy0>;
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&gmac1 {
+ status = "okay";
+
+ phy-mode = "rgmii";
+ phy-handle = <&phy1>;
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy1: ethernet-phy@1 {
+ reg = <16>;
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ pinctrl-0 = <&i2c0_pins_default>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ eeprom@57{
+ compatible = "atmel,24c16";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&clk {
+ status = "okay";
+};
+
+&rtc0 {
+ status = "okay";
+};
+
+&pctrl {
+ status = "okay";
+
+ sdio_pins_default: sdio-pins {
+ sdio-pinmux {
+ groups = "sdio";
+ function = "sdio";
+ };
+ sdio-det-pinmux {
+ groups = "pwm2";
+ function = "gpio";
+ };
+ };
+
+ pwm1_pins_default: pwm1-pins {
+ pinmux {
+ groups = "pwm1";
+ function = "pwm1";
+ };
+ };
+
+ pwm0_pins_default: pwm0-pins {
+ pinmux {
+ groups = "pwm0";
+ function = "pwm0";
+ };
+ };
+
+ i2c1_pins_default: i2c1-pins {
+ pinmux {
+ groups = "i2c1";
+ function = "i2c1";
+ };
+ };
+
+ i2c0_pins_default: i2c0-pins {
+ pinmux {
+ groups = "i2c0";
+ function = "i2c0";
+ };
+ };
+
+ nand_pins_default: nand-pins {
+ pinmux {
+ groups = "nand";
+ function = "nand";
+ };
+ };
+
+ hda_pins_default: hda-pins {
+ grp0-pinmux {
+ groups = "hda";
+ function = "hda";
+ };
+ grp1-pinmux {
+ groups = "i2s";
+ function = "gpio";
+ };
+ };
+};
diff --git a/arch/loongarch/boot/dts/loongson-2k1000.dtsi b/arch/loongarch/boot/dts/loongson-2k1000.dtsi
new file mode 100644
index 000000000000..8c48b64834eb
--- /dev/null
+++ b/arch/loongarch/boot/dts/loongson-2k1000.dtsi
@@ -0,0 +1,397 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Loongson Technology Corporation Limited
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/loongson,ls2k-clk.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "loongson,la264";
+ device_type = "cpu";
+ reg= <0x0>;
+ clocks = <&clk LOONGSON2_NODE_CLK>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "loongson,la264";
+ device_type = "cpu";
+ reg = <0x1>;
+ clocks = <&clk LOONGSON2_NODE_CLK>;
+ };
+ };
+
+ ref_100m: clock-ref-100m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "ref_100m";
+ };
+
+ cpuintc: interrupt-controller {
+ compatible = "loongson,cpu-interrupt-controller";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
+ /* i2c of the dvi eeprom edid */
+ i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <5>; /* ~100 kHz */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ /* i2c of the eeprom edid */
+ i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ scl-gpios = <&gpio0 33 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 32 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <5>; /* ~100 kHz */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ bus@10000000 {
+ compatible = "simple-bus";
+ ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>,
+ <0x0 0x2000000 0x0 0x2000000 0x0 0x2000000>,
+ <0x0 0x20000000 0x0 0x20000000 0x0 0x10000000>,
+ <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
+ <0xfe 0x0 0xfe 0x0 0x0 0x40000000>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ dma-coherent;
+
+ liointc0: interrupt-controller@1fe01400 {
+ compatible = "loongson,liointc-2.0";
+ reg = <0x0 0x1fe01400 0x0 0x40>,
+ <0x0 0x1fe01040 0x0 0x8>,
+ <0x0 0x1fe01140 0x0 0x8>;
+ reg-names = "main", "isr0", "isr1";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ interrupt-names = "int0";
+ loongson,parent_int_map = <0xffffffff>, /* int0 */
+ <0x00000000>, /* int1 */
+ <0x00000000>, /* int2 */
+ <0x00000000>; /* int3 */
+ };
+
+ liointc1: interrupt-controller@1fe01440 {
+ compatible = "loongson,liointc-2.0";
+ reg = <0x0 0x1fe01440 0x0 0x40>,
+ <0x0 0x1fe01048 0x0 0x8>,
+ <0x0 0x1fe01148 0x0 0x8>;
+ reg-names = "main", "isr0", "isr1";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <3>;
+ interrupt-names = "int1";
+ loongson,parent_int_map = <0x00000000>, /* int0 */
+ <0xffffffff>, /* int1 */
+ <0x00000000>, /* int2 */
+ <0x00000000>; /* int3 */
+ };
+
+ chipid@1fe00000 {
+ compatible = "loongson,ls2k-chipid";
+ reg = <0x0 0x1fe00000 0x0 0x3ffc>;
+ little-endian;
+ };
+
+ pctrl: pinctrl@1fe00420 {
+ compatible = "loongson,ls2k-pinctrl";
+ reg = <0x0 0x1fe00420 0x0 0x18>;
+ status = "disabled";
+ };
+
+ clk: clock-controller@1fe00480 {
+ compatible = "loongson,ls2k-clk";
+ reg = <0x0 0x1fe00480 0x0 0x58>;
+ #clock-cells = <1>;
+ clocks = <&ref_100m>;
+ clock-names = "ref_100m";
+ status = "disabled";
+ };
+
+ gpio0: gpio@1fe00500 {
+ compatible = "loongson,ls2k-gpio";
+ reg = <0x0 0x1fe00500 0x0 0x38>;
+ ngpios = <64>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pctrl 0x0 0x0 15>,
+ <&pctrl 16 16 15>,
+ <&pctrl 32 32 10>,
+ <&pctrl 44 44 20>;
+ interrupt-parent = <&liointc1>;
+ interrupts = <28 IRQ_TYPE_LEVEL_HIGH>,
+ <29 IRQ_TYPE_LEVEL_HIGH>,
+ <30 IRQ_TYPE_LEVEL_HIGH>,
+ <30 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <>,
+ <>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ uart0: serial@1fe20000 {
+ compatible = "ns16550a";
+ reg = <0x0 0x1fe20000 0x0 0x10>;
+ clock-frequency = <125000000>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <0x0 IRQ_TYPE_LEVEL_HIGH>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ i2c2: i2c@1fe21000 {
+ compatible = "loongson,ls2k-i2c";
+ reg = <0x0 0x1fe21000 0x0 0x8>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@1fe21800 {
+ compatible = "loongson,ls2k-i2c";
+ reg = <0x0 0x1fe21800 0x0 0x8>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ rtc0: rtc@1fe27800 {
+ compatible = "loongson,ls2k1000-rtc";
+ reg = <0x0 0x1fe27800 0x0 0x100>;
+ interrupt-parent = <&liointc1>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ pcie@1a000000 {
+ compatible = "loongson,ls2k-pci";
+ reg = <0x0 0x1a000000 0x0 0x02000000>,
+ <0xfe 0x0 0x0 0x20000000>;
+
+ ranges = <0x1000000 0x0 0x8000 0x0 0x18008000 0x0 0x8000>,
+ <0x2000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>; /* mem */
+
+ device_type = "pci";
+ #size-cells = <2>;
+ #address-cells = <3>;
+
+ gmac0: ethernet@3,0 {
+ reg = <0x1800 0x0 0x0 0x0 0x0>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
+ <13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_lpi";
+ status = "disabled";
+ };
+
+ gmac1: ethernet@3,1 {
+ reg = <0x1900 0x0 0x0 0x0 0x0>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
+ <15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_lpi";
+ status = "disabled";
+ };
+
+ ehci0: usb@4,1 {
+ reg = <0x2100 0x0 0x0 0x0 0x0>;
+ interrupt-parent = <&liointc1>;
+ interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ ohci0: usb@4,2 {
+ reg = <0x2200 0x0 0x0 0x0 0x0>;
+ interrupt-parent = <&liointc1>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ display@6,0 {
+ reg = <0x3000 0x0 0x0 0x0 0x0>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ hda@7,0 {
+ reg = <0x3800 0x0 0x0 0x0 0x0>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ sata: sata@8,0 {
+ reg = <0x4000 0x0 0x0 0x0 0x0>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ pcie@9,0 {
+ reg = <0x4800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 0x0 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@a,0 {
+ reg = <0x5000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&liointc1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 1 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@b,0 {
+ reg = <0x5800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&liointc1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 2 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@c,0 {
+ reg = <0x6000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&liointc1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 3 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@d,0 {
+ reg = <0x6800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&liointc1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 4 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@e,0 {
+ reg = <0x7000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&liointc1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 5 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+ };
+ };
+};
--
2.39.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v4 6/7] LoongArch: dts: DeviceTree for Loongson-2K2000
2023-08-23 9:54 [PATCH v4 0/7] LoongArch: Add built-in dtb support Binbin Zhou
` (4 preceding siblings ...)
2023-08-23 9:55 ` [PATCH v4 5/7] LoongArch: dts: DeviceTree for Loongson-2K1000 Binbin Zhou
@ 2023-08-23 9:55 ` Binbin Zhou
2023-08-23 9:55 ` [PATCH v4 7/7] LoongArch: Parsing CPU-related information from DTS Binbin Zhou
2023-08-25 11:38 ` [PATCH v4 0/7] LoongArch: Add built-in dtb support Huacai Chen
7 siblings, 0 replies; 19+ messages in thread
From: Binbin Zhou @ 2023-08-23 9:55 UTC (permalink / raw)
To: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree
Cc: Huacai Chen, loongson-kernel, Xuerui Wang, loongarch, Jiaxun Yang,
Hongliang Wang, Binbin Zhou
Add DeviceTree file for Loongson-2K2000 processor, which integrates two
64-bit triple emission superscalar LA364 processor cores.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
arch/loongarch/boot/dts/Makefile | 3 +-
.../boot/dts/loongson-2k2000-ref.dts | 73 +++++
arch/loongarch/boot/dts/loongson-2k2000.dtsi | 291 ++++++++++++++++++
3 files changed, 366 insertions(+), 1 deletion(-)
create mode 100644 arch/loongarch/boot/dts/loongson-2k2000-ref.dts
create mode 100644 arch/loongarch/boot/dts/loongson-2k2000.dtsi
diff --git a/arch/loongarch/boot/dts/Makefile b/arch/loongarch/boot/dts/Makefile
index dc0782315bed..c019d6676f7e 100644
--- a/arch/loongarch/boot/dts/Makefile
+++ b/arch/loongarch/boot/dts/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
dtb-$(CONFIG_MACH_LOONGSON64) = loongson-2k0500-ref.dtb \
- loongson-2k1000-ref.dtb
+ loongson-2k1000-ref.dtb \
+ loongson-2k2000-ref.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_NAME))
diff --git a/arch/loongarch/boot/dts/loongson-2k2000-ref.dts b/arch/loongarch/boot/dts/loongson-2k2000-ref.dts
new file mode 100644
index 000000000000..27d1e2991aa1
--- /dev/null
+++ b/arch/loongarch/boot/dts/loongson-2k2000-ref.dts
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Loongson Technology Corporation Limited
+ */
+
+/dts-v1/;
+
+#include "loongson-2k2000.dtsi"
+
+/ {
+ compatible = "loongson,ls2k2000-ref", "loongson,ls2k2000";
+ model = "Loongson-2K2000 Reference Board";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory@200000 {
+ device_type = "memory";
+ reg = <0x0 0x200000 0x0 0xee00000>, /* 238 MB at 2 MB */
+ <0x0 0x90000000 0x0 0x70000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x2000000>;
+ linux,cma-default;
+ };
+ };
+};
+
+&sata {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&rtc0 {
+ status = "okay";
+};
+
+&xhci0 {
+ status = "okay";
+};
+
+&xhci1 {
+ status = "okay";
+};
+
+&gmac0 {
+ status = "okay";
+};
+
+&gmac1 {
+ status = "okay";
+};
+
+&gmac2 {
+ status = "okay";
+};
diff --git a/arch/loongarch/boot/dts/loongson-2k2000.dtsi b/arch/loongarch/boot/dts/loongson-2k2000.dtsi
new file mode 100644
index 000000000000..d4692074394e
--- /dev/null
+++ b/arch/loongarch/boot/dts/loongson-2k2000.dtsi
@@ -0,0 +1,291 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Loongson Technology Corporation Limited
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@1 {
+ compatible = "loongson,la364";
+ device_type = "cpu";
+ reg = <0x0>;
+ clocks = <&cpu_clk>;
+ };
+
+ cpu1: cpu@2 {
+ compatible = "loongson,la364";
+ device_type = "cpu";
+ reg = <0x1>;
+ clocks = <&cpu_clk>;
+ };
+ };
+
+ cpu_clk: cpu-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1200000000>;
+ };
+
+ cpuintc: interrupt-controller {
+ compatible = "loongson,cpu-interrupt-controller";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
+ bus@10000000 {
+ compatible = "simple-bus";
+ ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>,
+ <0x0 0x2000000 0x0 0x2000000 0x0 0x2000000>,
+ <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
+ <0xfe 0x0 0xfe 0x0 0x0 0x40000000>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ liointc: interrupt-controller@1fe01400 {
+ compatible = "loongson,liointc-1.0";
+ reg = <0x0 0x1fe01400 0x0 0x64>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ interrupt-names = "int0";
+ loongson,parent_int_map = <0xffffffff>, /* int0 */
+ <0x00000000>, /* int1 */
+ <0x00000000>, /* int2 */
+ <0x00000000>; /* int3 */
+ };
+
+ eiointc: interrupt-controller@1fe01600 {
+ compatible = "loongson,ls2k2000-eiointc";
+ reg = <0x0 0x1fe01600 0x0 0xea00>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <3>;
+ };
+
+ pic: interrupt-controller@10000000 {
+ compatible = "loongson,pch-pic-1.0";
+ reg = <0x0 0x10000000 0x0 0x400>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ loongson,pic-base-vec = <0>;
+ interrupt-parent = <&eiointc>;
+ };
+
+ msi: msi-controller@1fe01140 {
+ compatible = "loongson,pch-msi-1.0";
+ reg = <0x0 0x1fe01140 0x0 0x8>;
+ msi-controller;
+ loongson,msi-base-vec = <64>;
+ loongson,msi-num-vecs = <192>;
+ interrupt-parent = <&eiointc>;
+ };
+
+ rtc0: rtc@100d0100 {
+ compatible = "loongson,ls2k2000-rtc", "loongson,ls7a-rtc";
+ reg = <0x0 0x100d0100 0x0 0x100>;
+ interrupt-parent = <&pic>;
+ interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart0: serial@1fe001e0 {
+ compatible = "ns16550a";
+ reg = <0x0 0x1fe001e0 0x0 0x10>;
+ clock-frequency = <100000000>;
+ interrupt-parent = <&liointc>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ pcie@1a000000 {
+ compatible = "loongson,ls2k-pci";
+ reg = <0x0 0x1a000000 0x0 0x02000000>,
+ <0xfe 0x0 0x0 0x20000000>;
+
+ ranges = <0x2000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>,
+ <0x1000000 0x0 0x8000 0x0 0x18400000 0x0 0x8000>;
+
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ gmac0: ethernet@3,0 {
+ reg = <0x1800 0x0 0x0 0x0 0x0>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ status = "disabled";
+ };
+
+ gmac1: ethernet@3,1 {
+ reg = <0x1900 0x0 0x0 0x0 0x0>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ status = "disabled";
+ };
+
+ gmac2: ethernet@3,2 {
+ reg = <0x1a00 0x0 0x0 0x0 0x0>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ status = "disabled";
+ };
+
+ xhci0: usb@4,0 {
+ reg = <0x2000 0x0 0x0 0x0 0x0>;
+ interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ status = "disabled";
+ };
+
+ xhci1: usb@19,0 {
+ reg = <0xc800 0x0 0x0 0x0 0x0>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ status = "disabled";
+ };
+
+ display@6,1 {
+ reg = <0x3100 0x0 0x0 0x0 0x0>;
+ interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ status = "disabled";
+ };
+
+ hda@7,0 {
+ reg = <0x3800 0x0 0x0 0x0 0x0>;
+ interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ status = "disabled";
+ };
+
+ sata: sata@8,0 {
+ reg = <0x4000 0x0 0x0 0x0 0x0>;
+ interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ status = "disabled";
+ };
+
+ pcie@9,0 {
+ reg = <0x4800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&pic>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &pic 32 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@a,0 {
+ reg = <0x5000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&pic>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &pic 33 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@b,0 {
+ reg = <0x5800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&pic>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &pic 34 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@c,0 {
+ reg = <0x6000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&pic>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &pic 35 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@d,0 {
+ reg = <0x6800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&pic>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &pic 36 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@e,0 {
+ reg = <0x7000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&pic>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &pic 37 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@f,0 {
+ reg = <0x7800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&pic>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &pic 40 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@10,0 {
+ reg = <0x8000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&pic>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &pic 30 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+ };
+ };
+};
--
2.39.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v4 7/7] LoongArch: Parsing CPU-related information from DTS
2023-08-23 9:54 [PATCH v4 0/7] LoongArch: Add built-in dtb support Binbin Zhou
` (5 preceding siblings ...)
2023-08-23 9:55 ` [PATCH v4 6/7] LoongArch: dts: DeviceTree for Loongson-2K2000 Binbin Zhou
@ 2023-08-23 9:55 ` Binbin Zhou
2023-08-25 11:38 ` [PATCH v4 0/7] LoongArch: Add built-in dtb support Huacai Chen
7 siblings, 0 replies; 19+ messages in thread
From: Binbin Zhou @ 2023-08-23 9:55 UTC (permalink / raw)
To: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree
Cc: Huacai Chen, loongson-kernel, Xuerui Wang, loongarch, Jiaxun Yang,
Hongliang Wang, Binbin Zhou
Generally, we can get cpu-related information, such as model name, from
/proc/cpuinfo. for DT-based systems, we need to parse the relevant
information from DTS.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Signed-off-by: Hongliang Wang <wanghongliang@loongson.cn>
---
arch/loongarch/kernel/env.c | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/loongarch/kernel/env.c b/arch/loongarch/kernel/env.c
index 6b3bfb0092e6..0191fe20b535 100644
--- a/arch/loongarch/kernel/env.c
+++ b/arch/loongarch/kernel/env.c
@@ -5,13 +5,16 @@
* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
*/
#include <linux/acpi.h>
+#include <linux/clk.h>
#include <linux/efi.h>
#include <linux/export.h>
#include <linux/memblock.h>
+#include <linux/of_clk.h>
#include <asm/early_ioremap.h>
#include <asm/bootinfo.h>
#include <asm/loongson.h>
#include <asm/setup.h>
+#include <asm/time.h>
u64 efi_system_table;
struct loongson_system_configuration loongson_sysconf;
@@ -34,9 +37,39 @@ void __init init_environ(void)
efi_system_table = fw_arg2;
}
+static int __init fdt_cpu_clk_init(void)
+{
+ struct clk *clk;
+ struct device_node *np;
+
+ np = of_get_cpu_node(0, NULL);
+ if (!np)
+ return -ENODEV;
+
+ clk = of_clk_get(np, 0);
+ if (IS_ERR(clk))
+ return -ENODEV;
+
+ cpu_clock_freq = clk_get_rate(clk);
+ clk_put(clk);
+
+ return 0;
+}
+late_initcall(fdt_cpu_clk_init);
+
static int __init init_cpu_fullname(void)
{
int cpu;
+ char *prop;
+ struct device_node *root;
+
+ /* Parsing cpuname from DTS model property */
+ root = of_find_node_by_path("/");
+ if (root) {
+ of_property_read_string(root, "model", (const char **)&prop);
+ if (prop)
+ loongson_sysconf.cpuname = strsep(&prop, " ");
+ }
if (loongson_sysconf.cpuname && !strncmp(loongson_sysconf.cpuname, "Loongson", 8)) {
for (cpu = 0; cpu < NR_CPUS; cpu++)
--
2.39.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v4 0/7] LoongArch: Add built-in dtb support
2023-08-23 9:54 [PATCH v4 0/7] LoongArch: Add built-in dtb support Binbin Zhou
` (6 preceding siblings ...)
2023-08-23 9:55 ` [PATCH v4 7/7] LoongArch: Parsing CPU-related information from DTS Binbin Zhou
@ 2023-08-25 11:38 ` Huacai Chen
2023-08-25 11:57 ` Conor Dooley
7 siblings, 1 reply; 19+ messages in thread
From: Huacai Chen @ 2023-08-25 11:38 UTC (permalink / raw)
To: Binbin Zhou
Cc: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree, loongson-kernel, Xuerui Wang, loongarch,
Jiaxun Yang, Hongliang Wang
This series looks good enough to me now, if no one has objections, I
will queue it to loongarch-next.
Huacai
On Wed, Aug 23, 2023 at 5:55 PM Binbin Zhou <zhoubinbin@loongson.cn> wrote:
>
> Hi all:
>
> This patchset introduces LoongArch's built-in dtb support.
>
> As we know, the Loongson-2K family supports DT. Inevitably, some systems
> do not provide a useful device tree to the kernel at boot time. Chasing
> around bootloaders for these systems is a headache, so we just keep a
> device tree table in the kernel, keyed by the dts filename, that
> contains the relevant DTBs.
>
> Thanks.
>
> -----
> V4:
> patch(1/7):
> - Drop device_type property.
> patch(2/7):
> - Rename board.yaml to loongson.yaml.
> patch(4/7):
> - Keep the ranges attribute after compatible;
> - Add bootargs = "ttyS0,115200", which is needed for reference board;
> patch(5/7):
> - Keep the ranges attribute after compatible;
> - Add bootargs = "ttyS0,115200", which is needed for reference board;
> - Change node name global-utilities to chipid.
> patch(6/7):
> - Keep the ranges attribute after compatible;
> - Add bootargs = "ttyS0,115200", which is needed for reference board.
>
> Link to V3:
> https://lore.kernel.org/all/cover.1692618548.git.zhoubinbin@loongson.cn/
>
> V3:
> patch(1/7):
> - Add reference to the common cpu schema.
> patch(2/7):
> - Add reviewed-by tag.
> patch(4/7):
> - Drop bootargs;
> - Move the cpus node to dtsi, which is part of the SoC.
> patch(5/7):
> - Drop bootargs;
> - Move the cpus node to dtsi, which is part of the SoC;
> - Fix gmac0/1-mdio node: compatible is always the first property;
> - Drop i2c-gpio node.
> patch(6/7):
> - Drop bootargs;
> - Move the cpus node to dtsi, which is part of the SoC.
> - Changes liointc to liointc-1.0, for Loongson-2K2000 has 32 interrupt
> sources.
>
> Link to V2:
> https://lore.kernel.org/all/cover.1692088166.git.zhoubinbin@loongson.cn/
>
> V2:
> patch(1/7):
> - Drop model and clock-frequency properties;
> - Add clocks property;
> - Rewrite the description.
> patch(2/7):
> - Add the proper compatibles for boards.
> patch(4/7)(5/7)(6/7):
> - Format commit message head;
> - Drop undocumented compatible, such as pci_bridge compatible;
> - Distinguish the attributes, put SoC-related into DTSI and
> board-related into DTS;
> - Check DTS with 'make dtbs_check W=1'.
> patch(7/7)
> - New patch;
> - Parses Molde name and CPU MHz from the DTS attribute.
>
> Link to V1:
> https://lore.kernel.org/loongarch/cover.1686882123.git.zhoubinbin@loongson.cn/
>
> Binbin Zhou (7):
> dt-bindings: loongarch: Add CPU bindings for LoongArch
> dt-bindings: loongarch: Add Loongson SoC boards compatibles
> LoongArch: Allow device trees to be built into the kernel
> LoongArch: dts: DeviceTree for Loongson-2K0500
> LoongArch: dts: DeviceTree for Loongson-2K1000
> LoongArch: dts: DeviceTree for Loongson-2K2000
> LoongArch: Parsing CPU-related information from DTS
>
> .../devicetree/bindings/loongarch/cpus.yaml | 61 +++
> .../bindings/loongarch/loongson.yaml | 34 ++
> arch/loongarch/Kconfig | 16 +
> arch/loongarch/Makefile | 10 +-
> arch/loongarch/boot/dts/Makefile | 7 +-
> .../boot/dts/loongson-2k0500-ref.dts | 89 ++++
> arch/loongarch/boot/dts/loongson-2k0500.dtsi | 254 +++++++++++
> .../boot/dts/loongson-2k1000-ref.dts | 172 ++++++++
> arch/loongarch/boot/dts/loongson-2k1000.dtsi | 397 ++++++++++++++++++
> .../boot/dts/loongson-2k2000-ref.dts | 73 ++++
> arch/loongarch/boot/dts/loongson-2k2000.dtsi | 291 +++++++++++++
> arch/loongarch/kernel/env.c | 33 ++
> arch/loongarch/kernel/setup.c | 9 +-
> 13 files changed, 1440 insertions(+), 6 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/loongarch/cpus.yaml
> create mode 100644 Documentation/devicetree/bindings/loongarch/loongson.yaml
> create mode 100644 arch/loongarch/boot/dts/loongson-2k0500-ref.dts
> create mode 100644 arch/loongarch/boot/dts/loongson-2k0500.dtsi
> create mode 100644 arch/loongarch/boot/dts/loongson-2k1000-ref.dts
> create mode 100644 arch/loongarch/boot/dts/loongson-2k1000.dtsi
> create mode 100644 arch/loongarch/boot/dts/loongson-2k2000-ref.dts
> create mode 100644 arch/loongarch/boot/dts/loongson-2k2000.dtsi
>
> --
> 2.39.3
>
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v4 0/7] LoongArch: Add built-in dtb support
2023-08-25 11:38 ` [PATCH v4 0/7] LoongArch: Add built-in dtb support Huacai Chen
@ 2023-08-25 11:57 ` Conor Dooley
2023-08-25 15:06 ` Huacai Chen
0 siblings, 1 reply; 19+ messages in thread
From: Conor Dooley @ 2023-08-25 11:57 UTC (permalink / raw)
To: Huacai Chen
Cc: Binbin Zhou, Binbin Zhou, Huacai Chen, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree, loongson-kernel,
Xuerui Wang, loongarch, Jiaxun Yang, Hongliang Wang
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On Fri, Aug 25, 2023 at 07:38:31PM +0800, Huacai Chen wrote:
> This series looks good enough to me now, if no one has objections, I
> will queue it to loongarch-next.
Have you not read Rob's replies?
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^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v4 0/7] LoongArch: Add built-in dtb support
2023-08-25 11:57 ` Conor Dooley
@ 2023-08-25 15:06 ` Huacai Chen
2023-08-25 15:08 ` Conor Dooley
0 siblings, 1 reply; 19+ messages in thread
From: Huacai Chen @ 2023-08-25 15:06 UTC (permalink / raw)
To: Conor Dooley
Cc: Binbin Zhou, Binbin Zhou, Huacai Chen, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree, loongson-kernel,
Xuerui Wang, loongarch, Jiaxun Yang, Hongliang Wang
Hi, Conor,
On Fri, Aug 25, 2023 at 7:59 PM Conor Dooley <conor.dooley@microchip.com> wrote:
>
> On Fri, Aug 25, 2023 at 07:38:31PM +0800, Huacai Chen wrote:
> > This series looks good enough to me now, if no one has objections, I
> > will queue it to loongarch-next.
>
> Have you not read Rob's replies?
I'm sorry, I have read but I thought Binbin's reply has answered Rob's question.
Huacai
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v4 0/7] LoongArch: Add built-in dtb support
2023-08-25 15:06 ` Huacai Chen
@ 2023-08-25 15:08 ` Conor Dooley
2023-08-25 15:19 ` Huacai Chen
0 siblings, 1 reply; 19+ messages in thread
From: Conor Dooley @ 2023-08-25 15:08 UTC (permalink / raw)
To: Huacai Chen
Cc: Conor Dooley, Binbin Zhou, Binbin Zhou, Huacai Chen, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree, loongson-kernel,
Xuerui Wang, loongarch, Jiaxun Yang, Hongliang Wang
[-- Attachment #1: Type: text/plain, Size: 588 bytes --]
On Fri, Aug 25, 2023 at 11:06:40PM +0800, Huacai Chen wrote:
> Hi, Conor,
>
> On Fri, Aug 25, 2023 at 7:59 PM Conor Dooley <conor.dooley@microchip.com> wrote:
> >
> > On Fri, Aug 25, 2023 at 07:38:31PM +0800, Huacai Chen wrote:
> > > This series looks good enough to me now, if no one has objections, I
> > > will queue it to loongarch-next.
> >
> > Have you not read Rob's replies?
> I'm sorry, I have read but I thought Binbin's reply has answered Rob's question.
As far as I can tell, it didn't - but there were was a reply from Rob
about dtbs_check issues too IIRC.
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^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v4 0/7] LoongArch: Add built-in dtb support
2023-08-25 15:08 ` Conor Dooley
@ 2023-08-25 15:19 ` Huacai Chen
0 siblings, 0 replies; 19+ messages in thread
From: Huacai Chen @ 2023-08-25 15:19 UTC (permalink / raw)
To: Conor Dooley
Cc: Conor Dooley, Binbin Zhou, Binbin Zhou, Huacai Chen, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree, loongson-kernel,
Xuerui Wang, loongarch, Jiaxun Yang, Hongliang Wang
Hi, Conor,
On Fri, Aug 25, 2023 at 11:08 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Fri, Aug 25, 2023 at 11:06:40PM +0800, Huacai Chen wrote:
> > Hi, Conor,
> >
> > On Fri, Aug 25, 2023 at 7:59 PM Conor Dooley <conor.dooley@microchip.com> wrote:
> > >
> > > On Fri, Aug 25, 2023 at 07:38:31PM +0800, Huacai Chen wrote:
> > > > This series looks good enough to me now, if no one has objections, I
> > > > will queue it to loongarch-next.
> > >
> > > Have you not read Rob's replies?
> > I'm sorry, I have read but I thought Binbin's reply has answered Rob's question.
>
> As far as I can tell, it didn't - but there were was a reply from Rob
> about dtbs_check issues too IIRC.
OK, I see. The dtbs_check warning is being fixed in [1], but it seems
that Binbin hasn't got the key point of Krzysztof.
https://lore.kernel.org/linux-mips/d11873a1-b552-71f5-1100-7464687f8bb4@linaro.org/T/#t
Huacai
^ permalink raw reply [flat|nested] 19+ messages in thread