From: Krzysztof Kozlowski <krzk@kernel.org>
To: wangseok.lee@samsung.com,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
	"kishon@ti.com" <kishon@ti.com>,
	"vkoul@kernel.org" <vkoul@kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"jesper.nilsson@axis.com" <jesper.nilsson@axis.com>,
	"lars.persson@axis.com" <lars.persson@axis.com>
Cc: "bhelgaas@google.com" <bhelgaas@google.com>,
	"linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
	"kw@linux.com" <kw@linux.com>,
	"linux-arm-kernel@axis.com" <linux-arm-kernel@axis.com>,
	"kernel@axis.com" <kernel@axis.com>, 전문기 <moonki.jun@samsung.com>
Subject: Re: [PATCH 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller
Date: Mon, 28 Mar 2022 20:41:55 +0200	[thread overview]
Message-ID: <047cec5c-b9e4-5480-be96-01bae8610078@kernel.org> (raw)
In-Reply-To: <20220328014857epcms2p7d8cfd98d60f059916ef35ccc385bc004@epcms2p7>
On 28/03/2022 03:48, 이왕석 wrote:
> Add description to support Axis, ARTPEC-8 SoC.
> ARTPEC-8 is the SoC platform of Axis Communications
> and PCIe controller is designed based on Design-Ware PCIe controller.
> 
> Signed-off-by: Wangseok Lee <wangseok.lee@samsung.com>
> ---
>  .../bindings/pci/axis,artpec8-pcie-ep.yaml         | 110 +++++++++++++++++++
>  .../devicetree/bindings/pci/axis,artpec8-pcie.yaml | 117 +++++++++++++++++++++
>  2 files changed, 227 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml
>  create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml
> 
> diff --git a/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml
> new file mode 100644
> index 0000000..dc66965
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml
> @@ -0,0 +1,110 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/axis,artpec8-pcie-ep.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ARTPEC-8 SoC PCIe Controller Device Tree Bindings
> +
> +maintainers:
> +  - Jesper Nilsson <jesper.nilsson@axis.com>
> +
> +description: |+
> +  This PCIe end-point controller is based on the Synopsys DesignWare PCIe IP
> +  and thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
> +
> +allOf:
> +  - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
> +
> +properties:
> +  compatible:
> +    const: axis,artpec8-pcie-ep
> +
> +  reg:
> +    items:
> +      - description: Data Bus Interface (DBI) registers.
> +      - description: Data Bus Interface (DBI2) registers.
> +      - description: PCIe address space region.
> +
> +  reg-names:
> +    items:
> +      - const: dbi
> +      - const: dbi2
> +      - const: addr_space
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: PIPE clock, used by the controller to clock the PIPE
> +      - description: PCIe dbi clock, ungated version
> +      - description: PCIe master clock, ungated version
> +      - description: PCIe slave clock, ungated version
> +
> +  clock-names:
> +    items:
> +      - const: pipe_clk
> +      - const: dbi_clk
> +      - const: mstr_clk
> +      - const: slv_clk
> +
> +  phys:
> +    maxItems: 1
> +
> +  num-lanes:
> +    const: 2
> +
> +required:
compatible
> +  - clocks
> +  - clock-names
> +  - reg
> +  - reg-names
> +  - num-lanes
> +  - bus-range
> +  - interrupts
> +  - interrupt-names
> +  - samsung,fsys-sysreg
> +  - samsung,syscon-phandle
> +  - samsung,syscon-bus-s-fsys
> +  - samsung,syscon-bus-p-fsys
Why are they here but not in properties? Other properties are also
present here but not in properties.
> +  - phys
> +  - phy-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    artec8 {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +        pcie_ep: pcie-ep@17200000 {
> +            compatible = "axis,artpec8-pcie-ep";
> +            clocks = <&clock_cmu_fsys 39>,
> +                        <&clock_cmu_fsys 38>,
> +                        <&clock_cmu_fsys 37>,
> +                        <&clock_cmu_fsys 36>;
Align the indentation of continued lines/entries.
> +            clock-names = "pipe_clk", "dbi_clk", "mstr_clk", "slv_clk";
> +            reg = <0x0 0x17200000 0x0 0x1000>,
Put reg after compatible.
> +                    <0x0 0x17201000 0x0 0x1000>,
> +                    <0x2 0x00000000 0x6 0x00000000>;
> +            reg-names = "dbi", "dbi2", "addr_space";
> +            num-lanes = <2>;
> +            bus-range = <0x00 0xff>;
> +            interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> +            interrupt-names = "intr";
> +            #interrupt-cells = <1>;
> +            num-ib-windows = <16>;
> +            num-ob-windows = <16>;
Did you test the bindings with `make dt_binding_check`?
All comments apply also to your second file.
Best regards,
Krzysztof
     prev parent reply	other threads:[~2022-03-28 18:42 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20220328014857epcms2p7d8cfd98d60f059916ef35ccc385bc004@epcms2p7>
2022-03-28  1:48 ` [PATCH 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller 이왕석
2022-03-28 18:41   ` Krzysztof Kozlowski [this message]
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