[PATCH 0/3] ARM: dts: Add Lctech Pi F1C200s board support

[PATCH 0/3] ARM: dts: Add Lctech Pi F1C200s board support

[Andre Przywara]

Hi,

The Lctech Pi F1C200s is a small development board with the eponymous
Allwinner SoC.
It ships with SPI NAND flash, but I couldn't get that to work:
============
spi-nand spi0.0: unknown raw ID 00000000
spi-nand: probe of spi0.0 failed with error -524
============
I leave in the DT node anyway (minus partitions), matching the schematic.

The boards has two USB-C ports, one of which is connected to a USB
serial adapter chip. Since the other one (connected to the MUSB
controller) lacks any CC pin connections, I need to fix the OTG role
here, and went with peripheral. Forcing host mode worked as well, but
requires a separate power supply (although the other USB port works for
that as well).

The board was apparently also sold under the "Cherry Pi" brand before.

Patches 1 and 2 add the required DT bindings for the vendor and board
name strings, patch 3 adds the .dts file.

Please have a look!

Cheers,
Andre

Andre Przywara (3):
  dt-bindings: vendor-prefixes: add Lctech name
  dt-bindings: arm: sunxi: add compatible strings for Lctech Pi
  ARM: dts: suniv: Add Lctech Pi F1C200s devicetree

 .../devicetree/bindings/arm/sunxi.yaml        |  6 ++
 .../devicetree/bindings/vendor-prefixes.yaml  |  2 +
 arch/arm/boot/dts/Makefile                    |  1 +
 arch/arm/boot/dts/suniv-f1c100s.dtsi          |  5 ++
 arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts | 80 +++++++++++++++++++
 5 files changed, 94 insertions(+)
 create mode 100644 arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts

-- 
2.25.1

[PATCH 1/3] dt-bindings: vendor-prefixes: add Lctech name

[Andre Przywara]

Shenzen LC Technology [1] is a company making various boards and related
products around IoT and AI technology.
They used to use the "Cherry Pi" brand before.

Add it to the vendor prefixes list.

[1] http://www.chinalctech.com

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 035ef859fbc58..e273bf9235946 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -695,6 +695,8 @@ patternProperties:
     description: Lantiq Semiconductor
   "^lattice,.*":
     description: Lattice Semiconductor
+  "^lctech,.*":
+    description: Shenzen LC Technology Co,, Ltd.
   "^leadtek,.*":
     description: Shenzhen Leadtek Technology Co., Ltd.
   "^leez,.*":
-- 
2.25.1

[PATCH 2/3] dt-bindings: arm: sunxi: add compatible strings for Lctech Pi

[Andre Przywara]

The Lctech Pi F1C200s is a small development board using the Allwinner
F1C200s SoC.

Add the compatible string list to the bindings documentation.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 Documentation/devicetree/bindings/arm/sunxi.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml
index c6e0ad7f461dd..cbdfc1c247a2b 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.yaml
+++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
@@ -366,6 +366,12 @@ properties:
           - const: lamobo,lamobo-r1
           - const: allwinner,sun7i-a20
 
+      - description: Lctech Pi F1C200s
+        items:
+          - const: lctech,pi-f1c200s
+          - const: allwinner,suniv-f1c200s
+          - const: allwinner,suniv-f1c100s
+
       - description: Libre Computer Board ALL-H3-CC H2+
         items:
           - const: libretech,all-h3-cc-h2-plus
-- 
2.25.1

[PATCH 3/3] ARM: dts: suniv: Add Lctech Pi F1C200s devicetree

[Andre Przywara]

The Lctech Pi F1C200s (also previously known under the Cherry Pi brand)
is a small development board with the Allwinner F1C200s SoC. This is the
same as the F1C100s, but with 64MB instead of 32MB co-packaged DRAM.

Alongside the obligatory micro-SD card slot, the board features a
SPI-NAND flash chip, LCD and touch connectors, and unpopulated
expansion header pins.
There are two USB Type-C ports on the board: One supplies the power, also
connects to the USB MUSB OTG controller port. The other one is connected
to an CH340 USB serial chip, which in turn is connected to UART1.

Add a devicetree file, so that the board can be used easily.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/boot/dts/Makefile                    |  1 +
 arch/arm/boot/dts/suniv-f1c100s.dtsi          |  5 ++
 arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts | 80 +++++++++++++++++++
 3 files changed, 86 insertions(+)
 create mode 100644 arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 6abf6434eb372..f99c5c20bf7ef 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1394,6 +1394,7 @@ dtb-$(CONFIG_MACH_SUN9I) += \
 	sun9i-a80-cubieboard4.dtb
 dtb-$(CONFIG_MACH_SUNIV) += \
 	suniv-f1c100s-licheepi-nano.dtb \
+	suniv-f1c200s-lctech-pi.dtb \
 	suniv-f1c200s-popstick-v1.1.dtb
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
 	tegra20-acer-a500-picasso.dtb \
diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 0f24c766c9fc5..2ec022e92eea8 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -201,6 +201,11 @@ uart0_pe_pins: uart0-pe-pins {
 				pins = "PE0", "PE1";
 				function = "uart0";
 			};
+
+			uart1_pa_pins: uart1-pa-pins {
+				pins = "PA2", "PA3";
+				function = "uart1";
+			};
 		};
 
 		timer@1c20c00 {
diff --git a/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts b/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
new file mode 100644
index 0000000000000..a9d1778395438
--- /dev/null
+++ b/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Arm Ltd,
+ * based on work:
+ *   Copyright 2022 Icenowy Zheng <uwu@icenowy.me>
+ */
+
+/dts-v1/;
+#include "suniv-f1c100s.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Lctech Pi F1C200s";
+	compatible = "lctech,pi-f1c200s", "allwinner,suniv-f1c200s",
+		     "allwinner,suniv-f1c100s";
+
+	aliases {
+		mmc0 = &mmc0;
+		serial0 = &uart1;
+		spi0 = &spi0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	reg_vcc3v3: regulator-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+};
+
+&mmc0 {
+	broken-cd;
+	bus-width = <4>;
+	disable-wp;
+	vmmc-supply = <&reg_vcc3v3>;
+	status = "okay";
+};
+
+&otg_sram {
+	status = "okay";
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pc_pins>;
+	status = "okay";
+
+	flash@0 {
+		compatible = "spi-nand";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <40000000>;
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pa_pins>;
+	status = "okay";
+};
+
+/*
+ * This is a Type-C socket, but CC1/2 are not connected, and VBUS is connected
+ * to Vin, which supplies the board. Host mode works (if the board is powered
+ * otherwise), but peripheral is probably the intention.
+ */
+&usb_otg {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&usbphy {
+	status = "okay";
+};
-- 
2.25.1

Re: [PATCH 3/3] ARM: dts: suniv: Add Lctech Pi F1C200s devicetree

[Icenowy Zheng]

在 2022-10-25星期二的 15:59 +0100，Andre Przywara写道：
> The Lctech Pi F1C200s (also previously known under the Cherry Pi
> brand)

Oh? Are they the same hardware?

> is a small development board with the Allwinner F1C200s SoC. This is
> the
> same as the F1C100s, but with 64MB instead of 32MB co-packaged DRAM.
> 
> Alongside the obligatory micro-SD card slot, the board features a
> SPI-NAND flash chip, LCD and touch connectors, and unpopulated
> expansion header pins.
> There are two USB Type-C ports on the board: One supplies the power,
> also
> connects to the USB MUSB OTG controller port. The other one is
> connected
> to an CH340 USB serial chip, which in turn is connected to UART1.
> 
> Add a devicetree file, so that the board can be used easily.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  arch/arm/boot/dts/Makefile                    |  1 +
>  arch/arm/boot/dts/suniv-f1c100s.dtsi          |  5 ++
>  arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts | 80
> +++++++++++++++++++
>  3 files changed, 86 insertions(+)
>  create mode 100644 arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 6abf6434eb372..f99c5c20bf7ef 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1394,6 +1394,7 @@ dtb-$(CONFIG_MACH_SUN9I) += \
>         sun9i-a80-cubieboard4.dtb
>  dtb-$(CONFIG_MACH_SUNIV) += \
>         suniv-f1c100s-licheepi-nano.dtb \
> +       suniv-f1c200s-lctech-pi.dtb \
>         suniv-f1c200s-popstick-v1.1.dtb
>  dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
>         tegra20-acer-a500-picasso.dtb \
> diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> index 0f24c766c9fc5..2ec022e92eea8 100644
> --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> @@ -201,6 +201,11 @@ uart0_pe_pins: uart0-pe-pins {
>                                 pins = "PE0", "PE1";
>                                 function = "uart0";
>                         };
> +
> +                       uart1_pa_pins: uart1-pa-pins {
> +                               pins = "PA2", "PA3";
> +                               function = "uart1";
> +                       };

Should this be in a splitted commit?

>                 };
>  
>                 timer@1c20c00 {
> diff --git a/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
> b/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
> new file mode 100644
> index 0000000000000..a9d1778395438
> --- /dev/null
> +++ b/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
> @@ -0,0 +1,80 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2022 Arm Ltd,
> + * based on work:
> + *   Copyright 2022 Icenowy Zheng <uwu@icenowy.me>
> + */
> +
> +/dts-v1/;
> +#include "suniv-f1c100s.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> +       model = "Lctech Pi F1C200s";
> +       compatible = "lctech,pi-f1c200s", "allwinner,suniv-f1c200s",
> +                    "allwinner,suniv-f1c100s";
> +
> +       aliases {
> +               mmc0 = &mmc0;
> +               serial0 = &uart1;
> +               spi0 = &spi0;
> +       };
> +
> +       chosen {
> +               stdout-path = "serial0:115200n8";
> +       };
> +
> +       reg_vcc3v3: regulator-3v3 {
> +               compatible = "regulator-fixed";
> +               regulator-name = "vcc3v3";
> +               regulator-min-microvolt = <3300000>;
> +               regulator-max-microvolt = <3300000>;
> +       };
> +};
> +
> +&mmc0 {
> +       broken-cd;
> +       bus-width = <4>;
> +       disable-wp;
> +       vmmc-supply = <&reg_vcc3v3>;
> +       status = "okay";
> +};
> +
> +&otg_sram {
> +       status = "okay";
> +};
> +
> +&spi0 {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&spi0_pc_pins>;
> +       status = "okay";
> +
> +       flash@0 {
> +               compatible = "spi-nand";
> +               reg = <0>;
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               spi-max-frequency = <40000000>;
> +       };
> +};
> +
> +&uart1 {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&uart1_pa_pins>;
> +       status = "okay";
> +};
> +
> +/*
> + * This is a Type-C socket, but CC1/2 are not connected, and VBUS is
> connected
> + * to Vin, which supplies the board. Host mode works (if the board
> is powered
> + * otherwise), but peripheral is probably the intention.
> + */
> +&usb_otg {
> +       dr_mode = "peripheral";
> +       status = "okay";
> +};

Finally we should get able to override dr_mode just by HW.

> +
> +&usbphy {
> +       status = "okay";
> +};

Re: [PATCH 3/3] ARM: dts: suniv: Add Lctech Pi F1C200s devicetree

[Andre Przywara]

On Tue, 25 Oct 2022 23:30:26 +0800
Icenowy Zheng <uwu@icenowy.me> wrote:

Hi Icenowy,

thanks for having a look!
And btw, forgot to mention in the cover letter: this relies on the USB bits
in your series. Which works nicely, even in host mode.

> 在 2022-10-25星期二的 15:59 +0100，Andre Przywara写道：
> > The Lctech Pi F1C200s (also previously known under the Cherry Pi
> > brand)  
> 
> Oh? Are they the same hardware?

My board looks identical to this one:
https://www.cnx-software.com/2022/02/03/more-allwinner-f1c200s-arm9-boards-mangopi-r3-and-cherrypi-f1c200s/#cherrypi-f1c200s

The only difference is the silkscreen, there is no cherry logo on mine,
but the (no longer working) URL is the same, so it's the same board from
the same company. I guess legal troubles?

> > is a small development board with the Allwinner F1C200s SoC. This is
> > the
> > same as the F1C100s, but with 64MB instead of 32MB co-packaged DRAM.
> > 
> > Alongside the obligatory micro-SD card slot, the board features a
> > SPI-NAND flash chip, LCD and touch connectors, and unpopulated
> > expansion header pins.
> > There are two USB Type-C ports on the board: One supplies the power,
> > also
> > connects to the USB MUSB OTG controller port. The other one is
> > connected
> > to an CH340 USB serial chip, which in turn is connected to UART1.
> > 
> > Add a devicetree file, so that the board can be used easily.
> > 
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > ---
> >  arch/arm/boot/dts/Makefile                    |  1 +
> >  arch/arm/boot/dts/suniv-f1c100s.dtsi          |  5 ++
> >  arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts | 80
> > +++++++++++++++++++
> >  3 files changed, 86 insertions(+)
> >  create mode 100644 arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
> > 
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index 6abf6434eb372..f99c5c20bf7ef 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -1394,6 +1394,7 @@ dtb-$(CONFIG_MACH_SUN9I) += \
> >         sun9i-a80-cubieboard4.dtb
> >  dtb-$(CONFIG_MACH_SUNIV) += \
> >         suniv-f1c100s-licheepi-nano.dtb \
> > +       suniv-f1c200s-lctech-pi.dtb \
> >         suniv-f1c200s-popstick-v1.1.dtb
> >  dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
> >         tegra20-acer-a500-picasso.dtb \
> > diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> > b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> > index 0f24c766c9fc5..2ec022e92eea8 100644
> > --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> > +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> > @@ -201,6 +201,11 @@ uart0_pe_pins: uart0-pe-pins {
> >                                 pins = "PE0", "PE1";
> >                                 function = "uart0";
> >                         };
> > +
> > +                       uart1_pa_pins: uart1-pa-pins {
> > +                               pins = "PA2", "PA3";
> > +                               function = "uart1";
> > +                       };  
> 
> Should this be in a splitted commit?

I don't know if this is really necessary, but am of course happy to spin
this one out, if needed.

> >                 };
> >  
> >                 timer@1c20c00 {
> > diff --git a/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
> > b/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
> > new file mode 100644
> > index 0000000000000..a9d1778395438
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
> > @@ -0,0 +1,80 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Copyright 2022 Arm Ltd,
> > + * based on work:
> > + *   Copyright 2022 Icenowy Zheng <uwu@icenowy.me>
> > + */
> > +
> > +/dts-v1/;
> > +#include "suniv-f1c100s.dtsi"
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +
> > +/ {
> > +       model = "Lctech Pi F1C200s";
> > +       compatible = "lctech,pi-f1c200s", "allwinner,suniv-f1c200s",
> > +                    "allwinner,suniv-f1c100s";
> > +
> > +       aliases {
> > +               mmc0 = &mmc0;
> > +               serial0 = &uart1;
> > +               spi0 = &spi0;
> > +       };
> > +
> > +       chosen {
> > +               stdout-path = "serial0:115200n8";
> > +       };
> > +
> > +       reg_vcc3v3: regulator-3v3 {
> > +               compatible = "regulator-fixed";
> > +               regulator-name = "vcc3v3";
> > +               regulator-min-microvolt = <3300000>;
> > +               regulator-max-microvolt = <3300000>;
> > +       };
> > +};
> > +
> > +&mmc0 {
> > +       broken-cd;
> > +       bus-width = <4>;
> > +       disable-wp;
> > +       vmmc-supply = <&reg_vcc3v3>;
> > +       status = "okay";
> > +};
> > +
> > +&otg_sram {
> > +       status = "okay";
> > +};
> > +
> > +&spi0 {
> > +       pinctrl-names = "default";
> > +       pinctrl-0 = <&spi0_pc_pins>;
> > +       status = "okay";
> > +
> > +       flash@0 {
> > +               compatible = "spi-nand";
> > +               reg = <0>;
> > +               #address-cells = <1>;
> > +               #size-cells = <1>;
> > +               spi-max-frequency = <40000000>;
> > +       };
> > +};
> > +
> > +&uart1 {
> > +       pinctrl-names = "default";
> > +       pinctrl-0 = <&uart1_pa_pins>;
> > +       status = "okay";
> > +};
> > +
> > +/*
> > + * This is a Type-C socket, but CC1/2 are not connected, and VBUS is
> > connected
> > + * to Vin, which supplies the board. Host mode works (if the board
> > is powered
> > + * otherwise), but peripheral is probably the intention.
> > + */
> > +&usb_otg {
> > +       dr_mode = "peripheral";
> > +       status = "okay";
> > +};  
> 
> Finally we should get able to override dr_mode just by HW.

Do you mean by software? Yeah, that would be useful. Otherwise one could
dedicate a GPIO to a fake ID_DET pin, I guess. Or use a DT overlay.

Cheers,
Andre

> > +
> > +&usbphy {
> > +       status = "okay";
> > +};  
> 

Re: [PATCH 3/3] ARM: dts: suniv: Add Lctech Pi F1C200s devicetree

[Icenowy Zheng]

在 2022-10-25星期二的 16:44 +0100，Andre Przywara写道：
> On Tue, 25 Oct 2022 23:30:26 +0800
> Icenowy Zheng <uwu@icenowy.me> wrote:
> 
> Hi Icenowy,
> 
> thanks for having a look!
> And btw, forgot to mention in the cover letter: this relies on the
> USB bits
> in your series. Which works nicely, even in host mode.
> 
> > 在 2022-10-25星期二的 15:59 +0100，Andre Przywara写道：
> > > The Lctech Pi F1C200s (also previously known under the Cherry Pi
> > > brand)  
> > 
> > Oh? Are they the same hardware?
> 
> My board looks identical to this one:
> https://www.cnx-software.com/2022/02/03/more-allwinner-f1c200s-arm9-boards-mangopi-r3-and-cherrypi-f1c200s/#cherrypi-f1c200s
> 
> The only difference is the silkscreen, there is no cherry logo on
> mine,
> but the (no longer working) URL is the same, so it's the same board
> from
> the same company. I guess legal troubles?
> 
> > > is a small development board with the Allwinner F1C200s SoC. This
> > > is
> > > the
> > > same as the F1C100s, but with 64MB instead of 32MB co-packaged
> > > DRAM.
> > > 
> > > Alongside the obligatory micro-SD card slot, the board features a
> > > SPI-NAND flash chip, LCD and touch connectors, and unpopulated
> > > expansion header pins.
> > > There are two USB Type-C ports on the board: One supplies the
> > > power,
> > > also
> > > connects to the USB MUSB OTG controller port. The other one is
> > > connected
> > > to an CH340 USB serial chip, which in turn is connected to UART1.
> > > 
> > > Add a devicetree file, so that the board can be used easily.
> > > 
> > > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > > ---
> > >  arch/arm/boot/dts/Makefile                    |  1 +
> > >  arch/arm/boot/dts/suniv-f1c100s.dtsi          |  5 ++
> > >  arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts | 80
> > > +++++++++++++++++++
> > >  3 files changed, 86 insertions(+)
> > >  create mode 100644 arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
> > > 
> > > diff --git a/arch/arm/boot/dts/Makefile
> > > b/arch/arm/boot/dts/Makefile
> > > index 6abf6434eb372..f99c5c20bf7ef 100644
> > > --- a/arch/arm/boot/dts/Makefile
> > > +++ b/arch/arm/boot/dts/Makefile
> > > @@ -1394,6 +1394,7 @@ dtb-$(CONFIG_MACH_SUN9I) += \
> > >         sun9i-a80-cubieboard4.dtb
> > >  dtb-$(CONFIG_MACH_SUNIV) += \
> > >         suniv-f1c100s-licheepi-nano.dtb \
> > > +       suniv-f1c200s-lctech-pi.dtb \
> > >         suniv-f1c200s-popstick-v1.1.dtb
> > >  dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
> > >         tegra20-acer-a500-picasso.dtb \
> > > diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> > > b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> > > index 0f24c766c9fc5..2ec022e92eea8 100644
> > > --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> > > +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> > > @@ -201,6 +201,11 @@ uart0_pe_pins: uart0-pe-pins {
> > >                                 pins = "PE0", "PE1";
> > >                                 function = "uart0";
> > >                         };
> > > +
> > > +                       uart1_pa_pins: uart1-pa-pins {
> > > +                               pins = "PA2", "PA3";
> > > +                               function = "uart1";
> > > +                       };  
> > 
> > Should this be in a splitted commit?
> 
> I don't know if this is really necessary, but am of course happy to
> spin
> this one out, if needed.
> 
> > >                 };
> > >  
> > >                 timer@1c20c00 {
> > > diff --git a/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
> > > b/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
> > > new file mode 100644
> > > index 0000000000000..a9d1778395438
> > > --- /dev/null
> > > +++ b/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
> > > @@ -0,0 +1,80 @@
> > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > +/*
> > > + * Copyright 2022 Arm Ltd,
> > > + * based on work:
> > > + *   Copyright 2022 Icenowy Zheng <uwu@icenowy.me>
> > > + */
> > > +
> > > +/dts-v1/;
> > > +#include "suniv-f1c100s.dtsi"
> > > +
> > > +#include <dt-bindings/gpio/gpio.h>
> > > +
> > > +/ {
> > > +       model = "Lctech Pi F1C200s";
> > > +       compatible = "lctech,pi-f1c200s", "allwinner,suniv-
> > > f1c200s",
> > > +                    "allwinner,suniv-f1c100s";
> > > +
> > > +       aliases {
> > > +               mmc0 = &mmc0;
> > > +               serial0 = &uart1;
> > > +               spi0 = &spi0;
> > > +       };
> > > +
> > > +       chosen {
> > > +               stdout-path = "serial0:115200n8";
> > > +       };
> > > +
> > > +       reg_vcc3v3: regulator-3v3 {
> > > +               compatible = "regulator-fixed";
> > > +               regulator-name = "vcc3v3";
> > > +               regulator-min-microvolt = <3300000>;
> > > +               regulator-max-microvolt = <3300000>;
> > > +       };
> > > +};
> > > +
> > > +&mmc0 {
> > > +       broken-cd;
> > > +       bus-width = <4>;
> > > +       disable-wp;
> > > +       vmmc-supply = <&reg_vcc3v3>;
> > > +       status = "okay";
> > > +};
> > > +
> > > +&otg_sram {
> > > +       status = "okay";
> > > +};
> > > +
> > > +&spi0 {
> > > +       pinctrl-names = "default";
> > > +       pinctrl-0 = <&spi0_pc_pins>;
> > > +       status = "okay";
> > > +
> > > +       flash@0 {
> > > +               compatible = "spi-nand";
> > > +               reg = <0>;
> > > +               #address-cells = <1>;
> > > +               #size-cells = <1>;
> > > +               spi-max-frequency = <40000000>;
> > > +       };
> > > +};
> > > +
> > > +&uart1 {
> > > +       pinctrl-names = "default";
> > > +       pinctrl-0 = <&uart1_pa_pins>;
> > > +       status = "okay";
> > > +};
> > > +
> > > +/*
> > > + * This is a Type-C socket, but CC1/2 are not connected, and
> > > VBUS is
> > > connected
> > > + * to Vin, which supplies the board. Host mode works (if the
> > > board
> > > is powered
> > > + * otherwise), but peripheral is probably the intention.
> > > + */
> > > +&usb_otg {
> > > +       dr_mode = "peripheral";
> > > +       status = "okay";
> > > +};  
> > 
> > Finally we should get able to override dr_mode just by HW.
> 
> Do you mean by software? Yeah, that would be useful. Otherwise one
> could

Yes, by SW. It's a typo (I think it's some kind of nerve link bit-flip
when I was typing this).

BTW I think the further utilization of something like a proper Type-C
controller (e.g. FUSB302) needs the driver to implement a new interface
in kernel, usb role switch.

> dedicate a GPIO to a fake ID_DET pin, I guess. Or use a DT overlay.
> 
> Cheers,
> Andre
> 
> > > +
> > > +&usbphy {
> > > +       status = "okay";
> > > +};  
> > 
> 

Re: [PATCH 1/3] dt-bindings: vendor-prefixes: add Lctech name

[Krzysztof Kozlowski]

On 25/10/2022 10:59, Andre Przywara wrote:
> Shenzen LC Technology [1] is a company making various boards and related
> products around IoT and AI technology.
> They used to use the "Cherry Pi" brand before.
> 
> Add it to the vendor prefixes list.
> 
> [1] http://www.chinalctech.com
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index 035ef859fbc58..e273bf9235946 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -695,6 +695,8 @@ patternProperties:
>      description: Lantiq Semiconductor
>    "^lattice,.*":
>      description: Lattice Semiconductor
> +  "^lctech,.*":
> +    description: Shenzen LC Technology Co,, Ltd.

Drop one comma.

Best regards,
Krzysztof

Re: [PATCH 2/3] dt-bindings: arm: sunxi: add compatible strings for Lctech Pi

[Krzysztof Kozlowski]

On 25/10/2022 10:59, Andre Przywara wrote:
> The Lctech Pi F1C200s is a small development board using the Allwinner
> F1C200s SoC.
> 
> Add the compatible string list to the bindings documentation.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 3/3] ARM: dts: suniv: Add Lctech Pi F1C200s devicetree

[Jernej Škrabec]

Hi Andre,

sorry for late review.

Dne torek, 25. oktober 2022 ob 16:59:09 CET je Andre Przywara napisal(a):
> The Lctech Pi F1C200s (also previously known under the Cherry Pi brand)
> is a small development board with the Allwinner F1C200s SoC. This is the
> same as the F1C100s, but with 64MB instead of 32MB co-packaged DRAM.
> 
> Alongside the obligatory micro-SD card slot, the board features a
> SPI-NAND flash chip, LCD and touch connectors, and unpopulated
> expansion header pins.
> There are two USB Type-C ports on the board: One supplies the power, also
> connects to the USB MUSB OTG controller port. The other one is connected
> to an CH340 USB serial chip, which in turn is connected to UART1.
> 
> Add a devicetree file, so that the board can be used easily.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  arch/arm/boot/dts/Makefile                    |  1 +
>  arch/arm/boot/dts/suniv-f1c100s.dtsi          |  5 ++
>  arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts | 80 +++++++++++++++++++
>  3 files changed, 86 insertions(+)
>  create mode 100644 arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 6abf6434eb372..f99c5c20bf7ef 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1394,6 +1394,7 @@ dtb-$(CONFIG_MACH_SUN9I) += \
>  	sun9i-a80-cubieboard4.dtb
>  dtb-$(CONFIG_MACH_SUNIV) += \
>  	suniv-f1c100s-licheepi-nano.dtb \
> +	suniv-f1c200s-lctech-pi.dtb \
>  	suniv-f1c200s-popstick-v1.1.dtb
>  dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
>  	tegra20-acer-a500-picasso.dtb \
> diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 0f24c766c9fc5..2ec022e92eea8
> 100644
> --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> @@ -201,6 +201,11 @@ uart0_pe_pins: uart0-pe-pins {
>  				pins = "PE0", "PE1";
>  				function = "uart0";
>  			};
> +
> +			uart1_pa_pins: uart1-pa-pins {
> +				pins = "PA2", "PA3";
> +				function = "uart1";
> +			};

/omit-if-no-ref/

>  		};
> 
>  		timer@1c20c00 {
> diff --git a/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
> b/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts new file mode 100644
> index 0000000000000..a9d1778395438
> --- /dev/null
> +++ b/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
> @@ -0,0 +1,80 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2022 Arm Ltd,
> + * based on work:
> + *   Copyright 2022 Icenowy Zheng <uwu@icenowy.me>
> + */
> +
> +/dts-v1/;
> +#include "suniv-f1c100s.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> +	model = "Lctech Pi F1C200s";
> +	compatible = "lctech,pi-f1c200s", "allwinner,suniv-f1c200s",
> +		     "allwinner,suniv-f1c100s";
> +
> +	aliases {
> +		mmc0 = &mmc0;
> +		serial0 = &uart1;
> +		spi0 = &spi0;

We don't do aliases for mmc nor spi.

Best regards,
Jernej

> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	reg_vcc3v3: regulator-3v3 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "vcc3v3";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +	};
> +};
> +
> +&mmc0 {
> +	broken-cd;
> +	bus-width = <4>;
> +	disable-wp;
> +	vmmc-supply = <&reg_vcc3v3>;
> +	status = "okay";
> +};
> +
> +&otg_sram {
> +	status = "okay";
> +};
> +
> +&spi0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spi0_pc_pins>;
> +	status = "okay";
> +
> +	flash@0 {
> +		compatible = "spi-nand";
> +		reg = <0>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		spi-max-frequency = <40000000>;
> +	};
> +};
> +
> +&uart1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart1_pa_pins>;
> +	status = "okay";
> +};
> +
> +/*
> + * This is a Type-C socket, but CC1/2 are not connected, and VBUS is
> connected + * to Vin, which supplies the board. Host mode works (if the
> board is powered + * otherwise), but peripheral is probably the intention.
> + */
> +&usb_otg {
> +	dr_mode = "peripheral";
> +	status = "okay";
> +};
> +
> +&usbphy {
> +	status = "okay";
> +};