From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Conor Dooley <conor@kernel.org>
Cc: Kris Chaplin <kris.chaplin@amd.com>,
thomas.delev@amd.com, michal.simek@amd.com, robh+dt@kernel.org,
conor+dt@kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, git@amd.com
Subject: Re: [PATCH 1/2] dt-bindings: w1: Add YAML DT Schema for AMD w1 master and MAINTAINERS entry
Date: Fri, 13 Oct 2023 17:22:17 +0200 [thread overview]
Message-ID: <0494c270-e3db-4621-88a6-313ccdb562ec@linaro.org> (raw)
In-Reply-To: <20231013-january-caliber-2e7acbee15ec@spud>
On 13/10/2023 17:07, Conor Dooley wrote:
>>> +maintainers:
>>> + - Kris Chaplin <kris.chaplin@amd.com>
>>> +
>>> +properties:
>>> + compatible:
>>> + const: amd,axi-1wire-master
>>
>> That's a quite generic compatible. axi is ARM term, 1-wire is the name
>> of the bus and master is the role. Concatenating three common words does
>> not create unique device name. Compatibles are supposed to be specific
>> and this is really relaxed. Anything can be over AXI, everything in
>> 1wire is 1wire and every master device is a master.
>
> Given the vendor (and the title of the binding) this is almost certainly
> an FPGA IP core, so the generic name is understandable. Using the exact
> name of the IP in the AMD/Xilinx catalog probably is the best choice?
Other option is that it is a part of some Zynq SoC.
Best regards,
Krzysztof
next prev parent reply other threads:[~2023-10-13 15:22 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-13 9:30 [PATCH 0/2] w1: Add 1-wire master driver for AMD programmable logic IP Core Kris Chaplin
2023-10-13 9:30 ` [PATCH 1/2] dt-bindings: w1: Add YAML DT Schema for AMD w1 master and MAINTAINERS entry Kris Chaplin
2023-10-13 15:01 ` Conor Dooley
2023-10-13 15:04 ` Krzysztof Kozlowski
2023-10-13 15:07 ` Conor Dooley
2023-10-13 15:22 ` Krzysztof Kozlowski [this message]
2023-10-13 15:23 ` Kris Chaplin
2023-10-13 15:29 ` Krzysztof Kozlowski
2023-10-13 15:36 ` Kris Chaplin
2023-10-13 17:18 ` Rob Herring
2023-10-13 17:58 ` Kris Chaplin
2023-10-13 9:30 ` [PATCH 2/2] w1: Add 1-wire master driver for AMD programmable logic IP Core Kris Chaplin
2023-10-13 15:20 ` Krzysztof Kozlowski
2023-10-18 15:54 ` Kris Chaplin
2023-10-18 16:00 ` Krzysztof Kozlowski
2023-10-19 14:24 ` [PATCH v2 0/2] w1: Add AXI 1-wire host driver for AMD programmable logic IP core Kris Chaplin
2023-10-19 14:24 ` [PATCH v2 1/2] dt-bindings: w1: Add YAML DT schema for AMD AXI w1 host and MAINTAINERS entry Kris Chaplin
2023-10-19 14:30 ` Conor Dooley
2023-10-19 14:35 ` Michal Simek
2023-10-19 14:39 ` Kris Chaplin
2023-10-19 14:24 ` [PATCH v2 2/2] w1: Add AXI 1-wire host driver for AMD programmable logic IP core Kris Chaplin
2023-10-19 14:28 ` [PATCH v2 0/2] " Conor Dooley
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