Re: [PATCH v2] arm64: dts: qcom: Add coresight nodes for QCS8300

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 9.12.2024 3:01 AM, Jie Gan wrote:
> 
> 
> On 12/8/2024 12:28 AM, Aiqun Yu (Maria) wrote:
>>
>>
>> On 12/5/2024 4:44 PM, Jie Gan wrote:
>>> Add following coresight components for QCS8300 platform.
>>> It includes CTI, dummy sink, dynamic Funnel, Replicator, STM,
>>> TPDM, TPDA and TMC ETF.
>>>
>>> Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
>>> ---
>>> Changes in V2:
>>> 1. Rebased on tag next-20241204.
>>> 2. Padding the register address to 8 bits.
>>> Link to V1 - https://lore.kernel.org/linux-arm-msm/20240929-add_coresight_devices_for_qcs8300-v1-1-4f14e8cb8955@quicinc.com/
>>> ---
>>>   arch/arm64/boot/dts/qcom/qcs8300.dtsi | 2150 +++++++++++++++++++++++++
>>>   1 file changed, 2150 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>> index 73abf2ef9c9f..eaec674950d8 100644
>>> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>> @@ -293,6 +293,18 @@ system_sleep: domain-sleep {
>>>           };
>>>       };
>>>   +    dummy_eud: dummy-sink {
>>> +        compatible = "arm,coresight-dummy-sink";
>>> +
>>> +        in-ports {
>>> +            port {
>>> +                eud_in: endpoint {
>>> +                    remote-endpoint = <&swao_rep_out1>;
>>> +                };
>>> +            };
>>> +        };
>>> +    };
>>> +
> 
> [...]
> 
>>> +
>>> +        tpdm@482c000 {
>>> +            compatible = "qcom,coresight-tpdm", "arm,primecell";
>>> +            reg = <0x0 0x0482c000 0x0 0x1000>;
>>> +
>>> +            clocks = <&aoss_qmp>;
>>> +            clock-names = "apb_pclk";
>>> +
>>> +            qcom,dsb-element-bits = <32>;
>>> +            qcom,dsb-msrs-num = <32>;
>>> +            status = "disabled";
>>
>> Could you please provide more detailed information on why some TPDM
>> nodes are disabled by default while others are not?
> Some of TPDM nodes are disabled by default because the one of the following reasons:
> 1. TPDM device are designed to generate HW events, it needs a clock source to read&write its registers. Coresight driver cannot control the clock source ouside AP core, so those TPDM devices without enabled clock source will crash device in probe.
> 2. Some of TPDM devices can't bootup with fused devices.
> 3. Some of TPDM devices have known hardware issues that not resolved.
> 
> I put those disabled TPDM devices in DT in case some of them may be "fixed" in future.

Please mark them as

/* Hardware issues */
status = "fail";

Konrad