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([2001:a61:34c9:ea01:14b4:7ed9:5135:9381]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b13309sm9524649f8f.3.2024.10.28.06.34.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Oct 2024 06:34:27 -0700 (PDT) Message-ID: <04e90dcf73bf87495e06639bd31160b848bde207.camel@gmail.com> Subject: Re: [PATCH v8 7/8] iio: dac: ad3552r: add high-speed platform driver From: Nuno =?ISO-8859-1?Q?S=E1?= To: Angelo Dureghello , Lars-Peter Clausen , Michael Hennerich , Nuno =?ISO-8859-1?Q?S=E1?= , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown , dlechner@baylibre.com Date: Mon, 28 Oct 2024 14:34:26 +0100 In-Reply-To: <20241025-wip-bl-ad3552r-axi-v0-iio-testing-v8-7-74ca7dd60567@baylibre.com> References: <20241025-wip-bl-ad3552r-axi-v0-iio-testing-v8-0-74ca7dd60567@baylibre.com> <20241025-wip-bl-ad3552r-axi-v0-iio-testing-v8-7-74ca7dd60567@baylibre.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.4 (3.52.4-2.fc40) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Fri, 2024-10-25 at 11:49 +0200, Angelo Dureghello wrote: > From: Angelo Dureghello >=20 > Add High Speed ad3552r platform driver. >=20 > The ad3552r DAC is controlled by a custom (fpga-based) DAC IP > through the current AXI backend, or similar alternative IIO backend. >=20 > Compared to the existing driver (ad3552r.c), that is a simple SPI > driver, this driver is coupled with a DAC IIO backend that finally > controls the ad3552r by a fpga-based "QSPI+DDR" interface, to reach > maximum transfer rate of 33MUPS using dma stream capabilities. >=20 > All commands involving QSPI bus read/write are delegated to the backend > through the provided APIs for bus read/write. >=20 > Signed-off-by: Angelo Dureghello > --- LGTM, just one question inline. If not an issue: Reviewed-by: Nuno Sa > =C2=A0drivers/iio/dac/Kconfig=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 14 ++ > =C2=A0drivers/iio/dac/Makefile=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 1 + > =C2=A0drivers/iio/dac/ad3552r-hs.c | 530 ++++++++++++++++++++++++++++++++= +++++++++++ > =C2=A0drivers/iio/dac/ad3552r-hs.h |=C2=A0 19 ++ > =C2=A0drivers/iio/dac/ad3552r.h=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 4 + > =C2=A05 files changed, 568 insertions(+) >=20 > diff --git a/drivers/iio/dac/Kconfig b/drivers/iio/dac/Kconfig > index 26f9de55b79f..f76eaba140d8 100644 > --- a/drivers/iio/dac/Kconfig > +++ b/drivers/iio/dac/Kconfig > @@ -6,6 +6,20 @@ > =C2=A0 > =C2=A0menu "Digital to analog converters" > =C2=A0 > +config AD3552R_HS > + tristate "Analog Devices AD3552R DAC High Speed driver" > + select ADI_AXI_DAC > + help > + =C2=A0 Say yes here to build support for Analog Devices AD3552R > + =C2=A0 Digital to Analog Converter High Speed driver. > + > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 The driver requir= es the assistance of an IP core to operate, > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 since data is str= eamed into target device via DMA, sent over a > + =C2=A0 QSPI + DDR (Double Data Rate) bus. > + > + =C2=A0 To compile this driver as a module, choose M here: the > + =C2=A0 module will be called ad3552r-hs. > + > =C2=A0config AD3552R > =C2=A0 tristate "Analog Devices AD3552R DAC driver" > =C2=A0 depends on SPI_MASTER > diff --git a/drivers/iio/dac/Makefile b/drivers/iio/dac/Makefile > index c92de0366238..d92e08ca93ca 100644 > --- a/drivers/iio/dac/Makefile > +++ b/drivers/iio/dac/Makefile > @@ -4,6 +4,7 @@ > =C2=A0# > =C2=A0 > =C2=A0# When adding new entries keep the list in alphabetical order > +obj-$(CONFIG_AD3552R_HS) +=3D ad3552r-hs.o ad3552r-common.o > =C2=A0obj-$(CONFIG_AD3552R) +=3D ad3552r.o ad3552r-common.o > =C2=A0obj-$(CONFIG_AD5360) +=3D ad5360.o > =C2=A0obj-$(CONFIG_AD5380) +=3D ad5380.o > diff --git a/drivers/iio/dac/ad3552r-hs.c b/drivers/iio/dac/ad3552r-hs.c > new file mode 100644 > index 000000000000..97dfc598aec6 > --- /dev/null > +++ b/drivers/iio/dac/ad3552r-hs.c > @@ -0,0 +1,530 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Analog Devices AD3552R > + * Digital to Analog converter driver, High Speed version > + * > + * Copyright 2024 Analog Devices Inc. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "ad3552r.h" > +#include "ad3552r-hs.h" > + > +struct ad3552r_hs_state { > + const struct ad3552r_model_data *model_data; > + struct gpio_desc *reset_gpio; > + struct device *dev; > + struct iio_backend *back; > + bool single_channel; > + struct ad3552r_ch_data ch_data[AD3552R_MAX_CH]; > + struct ad3552r_hs_platform_data *data; > +}; > + > +static int ad3552r_qspi_update_reg_bits(struct ad3552r_hs_state *st, > + u32 reg, u32 mask, u32 val, > + size_t xfer_size) > +{ > + u32 rval; > + int ret; > + > + ret =3D st->data->bus_reg_read(st->back, reg, &rval, xfer_size); > + if (ret) > + return ret; > + > + rval =3D (rval & ~mask) | val; > + > + return st->data->bus_reg_write(st->back, reg, rval, xfer_size); > +} > + > +static int ad3552r_hs_read_raw(struct iio_dev *indio_dev, > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 struct iio_chan_spec const *chan= , > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 int *val, int *val2, long mask) > +{ > + struct ad3552r_hs_state *st =3D iio_priv(indio_dev); > + int ret; > + int ch =3D chan->channel; > + > + switch (mask) { > + case IIO_CHAN_INFO_SAMP_FREQ: > + /* > + * Using 4 lanes (QSPI), then using 2 as DDR mode is > + * considered always on (considering buffering mode always). > + */ > + *val =3D DIV_ROUND_CLOSEST(st->data->bus_sample_data_clock_hz * > + 4 * 2, chan->scan_type.realbits); > + > + return IIO_VAL_INT; > + > + case IIO_CHAN_INFO_RAW: > + ret =3D st->data->bus_reg_read(st->back, > + AD3552R_REG_ADDR_CH_DAC_16B(chan->channel), > + val, 2); > + if (ret) > + return ret; Is there any potential issue by doing a raw access when streaming? - Nuno S=C3=A1