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([2a02:810d:15c0:828:9827:5f65:8269:a95f]) by smtp.gmail.com with ESMTPSA id e20-20020a50d4d4000000b004fbf6b35a56sm3363840edj.76.2023.03.16.00.09.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 16 Mar 2023 00:09:52 -0700 (PDT) Message-ID: <04f9336b-2a49-ca3f-fd28-1f04db78d2bd@linaro.org> Date: Thu, 16 Mar 2023 08:09:51 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v4 02/14] dt-bindings: display/msm/gmu: Add GMU wrapper Content-Language: en-US To: Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten References: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> <20230223-topic-gmuwrapper-v4-2-e987eb79d03f@linaro.org> From: Krzysztof Kozlowski In-Reply-To: <20230223-topic-gmuwrapper-v4-2-e987eb79d03f@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 14/03/2023 16:28, Konrad Dybcio wrote: > The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks > we'd normally assign to the GMU as if they were a part of the GMU, even > though they are not". It's a (good) software representation of the GMU_CX > and GMU_GX register spaces within the GPUSS that helps us programatically > treat these de-facto GMU-less parts in a way that's very similar to their > GMU-equipped cousins, massively saving up on code duplication. > > The "wrapper" register space was specifically designed to mimic the layout > of a real GMU, though it rather obviously does not have the M3 core et al. > > To sum it all up, the GMU wrapper is essentially a register space within > the GPU, which Linux sees as a dumbed-down regular GMU: there's no clocks, > interrupts, multiple reg spaces, iommus and OPP. Document it. > > Signed-off-by: Konrad Dybcio > --- > .../devicetree/bindings/display/msm/gmu.yaml | 49 ++++++++++++++++------ > 1 file changed, 37 insertions(+), 12 deletions(-) > > diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml > index ab14e81cb050..021373e686e1 100644 > --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml > +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml > @@ -19,16 +19,18 @@ description: | > > properties: > compatible: > - items: > - - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' > - - const: qcom,adreno-gmu > + oneOf: > + - items: > + - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' > + - const: qcom,adreno-gmu > + - const: qcom,adreno-gmu-wrapper > > reg: > - minItems: 3 > + minItems: 1 > maxItems: 4 > > reg-names: > - minItems: 3 > + minItems: 1 > maxItems: 4 > > clocks: > @@ -44,7 +46,6 @@ properties: > - description: GMU HFI interrupt > - description: GMU interrupt > > - > interrupt-names: > items: > - const: hfi > @@ -72,14 +73,8 @@ required: > - compatible > - reg > - reg-names > - - clocks > - - clock-names > - - interrupts > - - interrupt-names > - power-domains > - power-domain-names > - - iommus > - - operating-points-v2 > > additionalProperties: false > > @@ -216,6 +211,27 @@ allOf: > - const: cxo > - const: axi > - const: memnoc Blank line (you added such between ifs in previous patch) Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof