* [PATCH v2 1/3] dt-bindings: pci: qcom: Add opp table [not found] <1692192264-18515-1-git-send-email-quic_krichai@quicinc.com> @ 2023-08-16 13:24 ` Krishna chaitanya chundru 2023-08-18 9:19 ` Krzysztof Kozlowski 2023-08-16 13:24 ` [PATCH v2 2/3] arm64: dts: qcom: sm8450: Add opp table support to PCIe Krishna chaitanya chundru 1 sibling, 1 reply; 5+ messages in thread From: Krishna chaitanya chundru @ 2023-08-16 13:24 UTC (permalink / raw) To: manivannan.sadhasivam Cc: helgaas, linux-pci, linux-arm-msm, linux-kernel, quic_vbadigan, quic_nitegupt, quic_skananth, quic_ramkri, quic_parass, krzysztof.kozlowski, Krishna chaitanya chundru, Andy Gross, Bjorn Andersson, Konrad Dybcio, Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS PCIe needs to choose the appropriate performance state of RPMH power domain based upon the PCIe gen speed. Adding the Operating Performance Points table allows to adjust power domain performance state, depending on the PCIe gen speed. Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 81971be4..779339c 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -121,6 +121,10 @@ properties: description: GPIO controlled connection to WAKE# signal maxItems: 1 + operating-points-v2: true + opp-table: + type: object + required: - compatible - reg -- 2.7.4 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: pci: qcom: Add opp table 2023-08-16 13:24 ` [PATCH v2 1/3] dt-bindings: pci: qcom: Add opp table Krishna chaitanya chundru @ 2023-08-18 9:19 ` Krzysztof Kozlowski 0 siblings, 0 replies; 5+ messages in thread From: Krzysztof Kozlowski @ 2023-08-18 9:19 UTC (permalink / raw) To: Krishna chaitanya chundru, manivannan.sadhasivam Cc: helgaas, linux-pci, linux-arm-msm, linux-kernel, quic_vbadigan, quic_nitegupt, quic_skananth, quic_ramkri, quic_parass, Andy Gross, Bjorn Andersson, Konrad Dybcio, Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS On 16/08/2023 15:24, Krishna chaitanya chundru wrote: > PCIe needs to choose the appropriate performance state of RPMH power > domain based upon the PCIe gen speed. > > Adding the Operating Performance Points table allows to adjust power domain > performance state, depending on the PCIe gen speed. > > Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> > --- Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 2/3] arm64: dts: qcom: sm8450: Add opp table support to PCIe [not found] <1692192264-18515-1-git-send-email-quic_krichai@quicinc.com> 2023-08-16 13:24 ` [PATCH v2 1/3] dt-bindings: pci: qcom: Add opp table Krishna chaitanya chundru @ 2023-08-16 13:24 ` Krishna chaitanya chundru 2023-08-16 13:40 ` Dmitry Baryshkov 1 sibling, 1 reply; 5+ messages in thread From: Krishna chaitanya chundru @ 2023-08-16 13:24 UTC (permalink / raw) To: manivannan.sadhasivam Cc: helgaas, linux-pci, linux-arm-msm, linux-kernel, quic_vbadigan, quic_nitegupt, quic_skananth, quic_ramkri, quic_parass, krzysztof.kozlowski, Krishna chaitanya chundru, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS PCIe needs to choose the appropriate performance state of RPMH power domain based upon the PCIe gen speed. So let's add the OPP table support to specify RPMH performance states. Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 47 ++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 595533a..c77a683 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1803,7 +1803,28 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; + operating-points-v2 = <&pcie0_opp_table>; + status = "disabled"; + + pcie0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; pcie0_phy: phy@1c06000 { @@ -1915,7 +1936,33 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; + operating-points-v2 = <&pcie1_opp_table>; + status = "disabled"; + + pcie1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-16000000 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; pcie1_phy: phy@1c0f000 { -- 2.7.4 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: qcom: sm8450: Add opp table support to PCIe 2023-08-16 13:24 ` [PATCH v2 2/3] arm64: dts: qcom: sm8450: Add opp table support to PCIe Krishna chaitanya chundru @ 2023-08-16 13:40 ` Dmitry Baryshkov 2023-08-16 15:07 ` Krishna Chaitanya Chundru 0 siblings, 1 reply; 5+ messages in thread From: Dmitry Baryshkov @ 2023-08-16 13:40 UTC (permalink / raw) To: Krishna chaitanya chundru Cc: manivannan.sadhasivam, helgaas, linux-pci, linux-arm-msm, linux-kernel, quic_vbadigan, quic_nitegupt, quic_skananth, quic_ramkri, quic_parass, krzysztof.kozlowski, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS On Wed, 16 Aug 2023 at 16:25, Krishna chaitanya chundru <quic_krichai@quicinc.com> wrote: > > PCIe needs to choose the appropriate performance state of RPMH power > domain based upon the PCIe gen speed. > > So let's add the OPP table support to specify RPMH performance states. > > Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 47 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 47 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 595533a..c77a683 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -1803,7 +1803,28 @@ > pinctrl-names = "default"; > pinctrl-0 = <&pcie0_default_state>; > > + operating-points-v2 = <&pcie0_opp_table>; > + > status = "disabled"; > + > + pcie0_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-2500000 { As a random suggestion: these frequencies are calculated by the driver. It might be easier to use opp-level for the PCIe generation instead. This way this OPP entry can become: opp-1 { opp-level = <1>; required-opps = <&rpmhpd_opp_low_svs>; }; > + opp-hz = /bits/ 64 <2500000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-5000000 { > + opp-hz = /bits/ 64 <5000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-8000000 { > + opp-hz = /bits/ 64 <8000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > }; > > pcie0_phy: phy@1c06000 { > @@ -1915,7 +1936,33 @@ > pinctrl-names = "default"; > pinctrl-0 = <&pcie1_default_state>; > > + operating-points-v2 = <&pcie1_opp_table>; > + > status = "disabled"; > + > + pcie1_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-2500000 { > + opp-hz = /bits/ 64 <2500000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-5000000 { > + opp-hz = /bits/ 64 <5000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-8000000 { > + opp-hz = /bits/ 64 <8000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-16000000 { > + opp-hz = /bits/ 64 <16000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > }; > > pcie1_phy: phy@1c0f000 { > -- > 2.7.4 > -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: qcom: sm8450: Add opp table support to PCIe 2023-08-16 13:40 ` Dmitry Baryshkov @ 2023-08-16 15:07 ` Krishna Chaitanya Chundru 0 siblings, 0 replies; 5+ messages in thread From: Krishna Chaitanya Chundru @ 2023-08-16 15:07 UTC (permalink / raw) To: Dmitry Baryshkov Cc: manivannan.sadhasivam, helgaas, linux-pci, linux-arm-msm, linux-kernel, quic_vbadigan, quic_nitegupt, quic_skananth, quic_ramkri, quic_parass, krzysztof.kozlowski, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS On 8/16/2023 7:10 PM, Dmitry Baryshkov wrote: > On Wed, 16 Aug 2023 at 16:25, Krishna chaitanya chundru > <quic_krichai@quicinc.com> wrote: >> PCIe needs to choose the appropriate performance state of RPMH power >> domain based upon the PCIe gen speed. >> >> So let's add the OPP table support to specify RPMH performance states. >> >> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sm8450.dtsi | 47 ++++++++++++++++++++++++++++++++++++ >> 1 file changed, 47 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi >> index 595533a..c77a683 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi >> @@ -1803,7 +1803,28 @@ >> pinctrl-names = "default"; >> pinctrl-0 = <&pcie0_default_state>; >> >> + operating-points-v2 = <&pcie0_opp_table>; >> + >> status = "disabled"; >> + >> + pcie0_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-2500000 { > As a random suggestion: these frequencies are calculated by the > driver. It might be easier to use opp-level for the PCIe generation > instead. > > This way this OPP entry can become: > > opp-1 { > opp-level = <1>; > required-opps = <&rpmhpd_opp_low_svs>; > }; This looks good I will try to do in this approach in the next patch if there are no other comments. - KC > >> + opp-hz = /bits/ 64 <2500000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-5000000 { >> + opp-hz = /bits/ 64 <5000000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-8000000 { >> + opp-hz = /bits/ 64 <8000000>; >> + required-opps = <&rpmhpd_opp_nom>; >> + }; >> + }; >> }; >> >> pcie0_phy: phy@1c06000 { >> @@ -1915,7 +1936,33 @@ >> pinctrl-names = "default"; >> pinctrl-0 = <&pcie1_default_state>; >> >> + operating-points-v2 = <&pcie1_opp_table>; >> + >> status = "disabled"; >> + >> + pcie1_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-2500000 { >> + opp-hz = /bits/ 64 <2500000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-5000000 { >> + opp-hz = /bits/ 64 <5000000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-8000000 { >> + opp-hz = /bits/ 64 <8000000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-16000000 { >> + opp-hz = /bits/ 64 <16000000>; >> + required-opps = <&rpmhpd_opp_nom>; >> + }; >> + }; >> }; >> >> pcie1_phy: phy@1c0f000 { >> -- >> 2.7.4 >> > ^ permalink raw reply [flat|nested] 5+ messages in thread
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[not found] <1692192264-18515-1-git-send-email-quic_krichai@quicinc.com>
2023-08-16 13:24 ` [PATCH v2 1/3] dt-bindings: pci: qcom: Add opp table Krishna chaitanya chundru
2023-08-18 9:19 ` Krzysztof Kozlowski
2023-08-16 13:24 ` [PATCH v2 2/3] arm64: dts: qcom: sm8450: Add opp table support to PCIe Krishna chaitanya chundru
2023-08-16 13:40 ` Dmitry Baryshkov
2023-08-16 15:07 ` Krishna Chaitanya Chundru
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