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[83.9.29.26]) by smtp.gmail.com with ESMTPSA id r4-20020a19ac44000000b004fba5c20ab1sm2527946lfc.167.2023.07.04.05.33.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 04 Jul 2023 05:33:06 -0700 (PDT) Message-ID: <05666bf0-07f8-1e3a-22bf-fc779e2b7367@linaro.org> Date: Tue, 4 Jul 2023 14:33:04 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH V2] PCI: qcom: Use PARF_SLV_ADDR_SPACE_SIZE for ops_2_3_3 Content-Language: en-US To: Sricharan Ramabadhran , agross@kernel.org, andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, mani@kernel.org, lpieralisi@kernel.org, bhelgaas@google.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pci@vger.kernel.org Cc: stable@vger.kernel.org References: <20230703175757.2425540-1-quic_srichara@quicinc.com> From: Konrad Dybcio In-Reply-To: <20230703175757.2425540-1-quic_srichara@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 3.07.2023 19:57, Sricharan Ramabadhran wrote: > PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro is used for IPQ8074 > 2_3_3 post_init ops. pcie slave addr size was initially set > to 0x358, but was wrongly changed to 0x168 as a part of > "PCI: qcom: Remove PCIE20_ prefix from register definitions" > Fixing it, by using the right macro PARF_SLV_ADDR_SPACE_SIZE > and removing the unused PARF_SLV_ADDR_SPACE_SIZE_2_3_3. > > Without this pcie bring up on IPQ8074 is broken now. > > Fixes: 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from register definitions") > Signed-off-by: Sricharan Ramabadhran > --- Reviewed-by: Konrad Dybcio Konrad > [V2] Fixed the 'fixes tag' correctly, subject, right macro usage > > drivers/pci/controller/dwc/pcie-qcom.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 4ab30892f6ef..1689d072fe86 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -43,7 +43,6 @@ > #define PARF_PHY_REFCLK 0x4c > #define PARF_CONFIG_BITS 0x50 > #define PARF_DBI_BASE_ADDR 0x168 > -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16c /* Register offset specific to IP ver 2.3.3 */ > #define PARF_MHI_CLOCK_RESET_CTRL 0x174 > #define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 > #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 > @@ -811,7 +810,7 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) > u32 val; > > writel(SLV_ADDR_SPACE_SZ, > - pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_2_3_3); > + pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); > > val = readl(pcie->parf + PARF_PHY_CTRL); > val &= ~PHY_TEST_PWR_DOWN;