[PATCH 0/2] arm64: dts: ti: k3-j784s4-evm: SERDES0 lane cleanup

[PATCH 0/2] arm64: dts: ti: k3-j784s4-evm: SERDES0 lane cleanup

[Andrew Halaney]

This fixes a splat caused due to overlapping lane usage of SERDES0 by
PCIe1 and USB0. It also cleans up the dts a hair to be more readable.

Link: https://lore.kernel.org/all/yhtb4clns57t7qo5yxil3oofisdlzfubyiwrvjo2ufw2ngv67m@g6p7ktxfgfv3/
Signed-off-by: Andrew Halaney <ahalaney@redhat.com>
---
Andrew Halaney (2):
      arm64: dts: ti: k3-j784s4-evm: Assign only lanes 0 and 1 to PCIe1
      arm64: dts: ti: k3-j784s4-evm: Consolidate serdes0 references

 arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 25 ++++++++-----------------
 1 file changed, 8 insertions(+), 17 deletions(-)
---
base-commit: 523b23f0bee3014a7a752c9bb9f5c54f0eddae88
change-id: 20240710-k3-j784s4-evm-serdes0-cleanup-871401b860b8

Best regards,
-- 
Andrew Halaney <ahalaney@redhat.com>

[PATCH 1/2] arm64: dts: ti: k3-j784s4-evm: Assign only lanes 0 and 1 to PCIe1

[Andrew Halaney]

Currently PCIe1 is setup to use SERDES0 lanes 0 thru 3, and USB0 is
setup to use SERDES0 lane 3 as well.

This overlap in lanes causes the following reset related lane splat:

    [    4.846266] WARNING: CPU: 4 PID: 308 at drivers/reset/core.c:792 __reset_control_get_internal+0x128/0x160
    ...
    [    4.846405] Call trace:
    [    4.846407]  __reset_control_get_internal+0x128/0x160
    [    4.846413]  __of_reset_control_get+0x4e0/0x528
    [    4.846418]  of_reset_control_array_get+0xa4/0x1f8
    [    4.846423]  cdns_torrent_phy_probe+0xbc8/0x1068 [phy_cadence_torrent]
    [    4.846445]  platform_probe+0xb4/0xe8
    ...
    [    4.846577] cdns-torrent-phy 5060000.serdes: phy@0: failed to get reset

Let's limit the PCIe1 SERDES0 lanes to 0 and 1 to avoid overlap here.
This works since PCIe1 operates in x2 mode and doesn't need 4 SERDES0
lanes.

Fixes: 27ce26fe52d4 ("arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode")
Suggested-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Andrew Halaney <ahalaney@redhat.com>
---
 arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index 9338d987180d7..e54ccf4f37955 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -1391,11 +1391,10 @@ &serdes0 {
 
 	serdes0_pcie1_link: phy@0 {
 		reg = <0>;
-		cdns,num-lanes = <4>;
+		cdns,num-lanes = <2>;
 		#phy-cells = <0>;
 		cdns,phy-type = <PHY_TYPE_PCIE>;
-		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>,
-			 <&serdes_wiz0 3>, <&serdes_wiz0 4>;
+		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
 	};
 };
 

-- 
2.45.2

Re: [PATCH 1/2] arm64: dts: ti: k3-j784s4-evm: Assign only lanes 0 and 1 to PCIe1

[Siddharth Vadapalli]

On Wed, Jul 10, 2024 at 10:36:13AM -0500, Andrew Halaney wrote:
> Currently PCIe1 is setup to use SERDES0 lanes 0 thru 3, and USB0 is
> setup to use SERDES0 lane 3 as well.
> 
> This overlap in lanes causes the following reset related lane splat:
> 
>     [    4.846266] WARNING: CPU: 4 PID: 308 at drivers/reset/core.c:792 __reset_control_get_internal+0x128/0x160
>     ...
>     [    4.846405] Call trace:
>     [    4.846407]  __reset_control_get_internal+0x128/0x160
>     [    4.846413]  __of_reset_control_get+0x4e0/0x528
>     [    4.846418]  of_reset_control_array_get+0xa4/0x1f8
>     [    4.846423]  cdns_torrent_phy_probe+0xbc8/0x1068 [phy_cadence_torrent]
>     [    4.846445]  platform_probe+0xb4/0xe8
>     ...
>     [    4.846577] cdns-torrent-phy 5060000.serdes: phy@0: failed to get reset
> 
> Let's limit the PCIe1 SERDES0 lanes to 0 and 1 to avoid overlap here.
> This works since PCIe1 operates in x2 mode and doesn't need 4 SERDES0
> lanes.
> 
> Fixes: 27ce26fe52d4 ("arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode")
> Suggested-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> Signed-off-by: Andrew Halaney <ahalaney@redhat.com>

Thank you for posting this patch.

Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>

Regards,
Siddharth.

[PATCH 2/2] arm64: dts: ti: k3-j784s4-evm: Consolidate serdes0 references

[Andrew Halaney]

Subnodes were added to serdes0 in two different spots (due to independent
development of their consumer usage). Let's go ahead and combine those
into one reference for readability's sake.

Signed-off-by: Andrew Halaney <ahalaney@redhat.com>
---
 arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 24 ++++++++----------------
 1 file changed, 8 insertions(+), 16 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index e54ccf4f37955..ffa38f41679d8 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -1262,6 +1262,14 @@ &dss {
 &serdes0 {
 	status = "okay";
 
+	serdes0_pcie1_link: phy@0 {
+		reg = <0>;
+		cdns,num-lanes = <2>;
+		#phy-cells = <0>;
+		cdns,phy-type = <PHY_TYPE_PCIE>;
+		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
+	};
+
 	serdes0_usb_link: phy@3 {
 		reg = <3>;
 		cdns,num-lanes = <1>;
@@ -1386,22 +1394,6 @@ &main_mcan4 {
 	phys = <&transceiver3>;
 };
 
-&serdes0 {
-	status = "okay";
-
-	serdes0_pcie1_link: phy@0 {
-		reg = <0>;
-		cdns,num-lanes = <2>;
-		#phy-cells = <0>;
-		cdns,phy-type = <PHY_TYPE_PCIE>;
-		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
-	};
-};
-
-&serdes_wiz0 {
-	status = "okay";
-};
-
 &pcie1_rc {
 	status = "okay";
 	num-lanes = <2>;

-- 
2.45.2

Re: [PATCH 2/2] arm64: dts: ti: k3-j784s4-evm: Consolidate serdes0 references

[Siddharth Vadapalli]

On Wed, Jul 10, 2024 at 10:36:14AM -0500, Andrew Halaney wrote:
> Subnodes were added to serdes0 in two different spots (due to independent
> development of their consumer usage). Let's go ahead and combine those
> into one reference for readability's sake.
> 
> Signed-off-by: Andrew Halaney <ahalaney@redhat.com>

This patch could probably be squashed into the previous one.
Irrespective of that,

Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>

[...]

Regards,
Siddharth.

Re: [PATCH 0/2] arm64: dts: ti: k3-j784s4-evm: SERDES0 lane cleanup

[Vignesh Raghavendra]

Hi Andrew Halaney,

On Wed, 10 Jul 2024 10:36:12 -0500, Andrew Halaney wrote:
> This fixes a splat caused due to overlapping lane usage of SERDES0 by
> PCIe1 and USB0. It also cleans up the dts a hair to be more readable.
> 
> 

I have applied the following to branch ti-k3-dts-next on [1].
Thank you!

[1/2] arm64: dts: ti: k3-j784s4-evm: Assign only lanes 0 and 1 to PCIe1
      commit: 84f78178b6fe37b5eb8b90b5bb1239abce0b64d8
[2/2] arm64: dts: ti: k3-j784s4-evm: Consolidate serdes0 references
      commit: cc5049007d722364bca4a4eeb619d5629733a004

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh