[PATCH V3 0/3] Add APSS clock driver support for IPQ5018

[PATCH V3 0/3] Add APSS clock driver support for IPQ5018

[Gokul Sriram Palanisamy]

This series adds support for the APSS clock to bump the CPU frequency
above 800MHz. APSS PLL found in the IPQ5018 is of type Stromer. 

- The first patch in the series adds the required a53pll compatible.

- The second patch reuses Stormer Plus PLL offsets, adds configuration values
  for Stromer.

- The third patch adds dts nodes to enable the pll along with the cpu
  operating frequency table.

This series depends on below series
https://patchwork.kernel.org/project/linux-arm-msm/cover/20230913-gpll_cleanup-v2-0-c8ceb1a37680@quicinc.com/

Changes in v3:
- Addressed review comment by Dmitry in patch 3.

Changes in v2:
- Addressed review comments
- Adds dependency on above mentioned patch series for dropping
  CLK_SET_RATE_PARENT flag from GPLL clocks, GPLL0 clock provider for
  mailbox
- Add CPU operating point at 800MHz based on the review comments.

Gokul Sriram Palanisamy (3):
  dt-bindings: clock: qcom,a53pll: add IPQ5018 compatible
  clk: qcom: apss-ipq-pll: add support for IPQ5018
  arm64: dts: qcom: ipq5018: enable the CPUFreq support

 .../bindings/clock/qcom,a53pll.yaml           |  1 +
 arch/arm64/boot/dts/qcom/ipq5018.dtsi         | 40 +++++++++++++++++++
 drivers/clk/qcom/apss-ipq-pll.c               | 21 ++++++++++
 3 files changed, 62 insertions(+)

-- 
2.34.1

[PATCH V3 1/3] dt-bindings: clock: qcom,a53pll: add IPQ5018 compatible

[Gokul Sriram Palanisamy]

Add IPQ5018 compatible to A53 PLL bindings.

Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/clock/qcom,a53pll.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
index 9436266828af..5ca927a8b1d5 100644
--- a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
@@ -16,6 +16,7 @@ description:
 properties:
   compatible:
     enum:
+      - qcom,ipq5018-a53pll
       - qcom,ipq5332-a53pll
       - qcom,ipq6018-a53pll
       - qcom,ipq8074-a53pll
-- 
2.34.1

[PATCH V3 2/3] clk: qcom: apss-ipq-pll: add support for IPQ5018

[Gokul Sriram Palanisamy]

IPQ5018 APSS PLL is of type Stromer. Reuse Stromer Plus PLL offsets,
add configuration values and the compatible.

Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/apss-ipq-pll.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
index e170331858cc..bebbc8c5ab68 100644
--- a/drivers/clk/qcom/apss-ipq-pll.c
+++ b/drivers/clk/qcom/apss-ipq-pll.c
@@ -73,6 +73,20 @@ static struct clk_alpha_pll ipq_pll_stromer_plus = {
 	},
 };
 
+static const struct alpha_pll_config ipq5018_pll_config = {
+	.l = 0x32,
+	.config_ctl_val = 0x4001075b,
+	.config_ctl_hi_val = 0x304,
+	.main_output_mask = BIT(0),
+	.aux_output_mask = BIT(1),
+	.early_output_mask = BIT(3),
+	.alpha_en_mask = BIT(24),
+	.status_val = 0x3,
+	.status_mask = GENMASK(10, 8),
+	.lock_det = BIT(2),
+	.test_ctl_hi_val = 0x00400003,
+};
+
 static const struct alpha_pll_config ipq5332_pll_config = {
 	.l = 0x3e,
 	.config_ctl_val = 0x4001075b,
@@ -129,6 +143,12 @@ struct apss_pll_data {
 	const struct alpha_pll_config *pll_config;
 };
 
+static const struct apss_pll_data ipq5018_pll_data = {
+	.pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
+	.pll = &ipq_pll_stromer_plus,
+	.pll_config = &ipq5018_pll_config,
+};
+
 static struct apss_pll_data ipq5332_pll_data = {
 	.pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
 	.pll = &ipq_pll_stromer_plus,
@@ -195,6 +215,7 @@ static int apss_ipq_pll_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id apss_ipq_pll_match_table[] = {
+	{ .compatible = "qcom,ipq5018-a53pll", .data = &ipq5018_pll_data },
 	{ .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data },
 	{ .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data },
 	{ .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data },
-- 
2.34.1

[PATCH V3 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support

[Gokul Sriram Palanisamy]

Add the APCS, A53 PLL, cpu-opp-table nodes to set
the CPU frequency at 800MHz (idle) or 1.008GHz.

Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm64/boot/dts/qcom/ipq5018.dtsi | 40 +++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index 9f13d2dcdfd5..56f3c5260bbd 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -5,6 +5,7 @@
  * Copyright (c) 2023 The Linux Foundation. All rights reserved.
  */
 
+#include <dt-bindings/clock/qcom,apss-ipq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
 #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
@@ -36,6 +37,8 @@ CPU0: cpu@0 {
 			reg = <0x0>;
 			enable-method = "psci";
 			next-level-cache = <&L2_0>;
+			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+			operating-points-v2 = <&cpu_opp_table>;
 		};
 
 		CPU1: cpu@1 {
@@ -44,6 +47,8 @@ CPU1: cpu@1 {
 			reg = <0x1>;
 			enable-method = "psci";
 			next-level-cache = <&L2_0>;
+			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+			operating-points-v2 = <&cpu_opp_table>;
 		};
 
 		L2_0: l2-cache {
@@ -54,6 +59,23 @@ L2_0: l2-cache {
 		};
 	};
 
+	cpu_opp_table: opp-table-cpu {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <200000>;
+		};
+
+		opp-1008000000 {
+			opp-hz = /bits/ 64 <1008000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <200000>;
+		};
+	};
+
 	firmware {
 		scm {
 			compatible = "qcom,scm-ipq5018", "qcom,scm";
@@ -181,6 +203,24 @@ v2m1: v2m@1000 {
 			};
 		};
 
+		apcs_glb: mailbox@b111000 {
+			compatible = "qcom,ipq5018-apcs-apps-global",
+				     "qcom,ipq6018-apcs-apps-global";
+			reg = <0x0b111000 0x1000>;
+			#clock-cells = <1>;
+			clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>;
+			clock-names = "pll", "xo", "gpll0";
+			#mbox-cells = <1>;
+		};
+
+		a53pll: clock@b116000 {
+			compatible = "qcom,ipq5018-a53pll";
+			reg = <0x0b116000 0x40>;
+			#clock-cells = <0>;
+			clocks = <&xo_board_clk>;
+			clock-names = "xo";
+		};
+
 		timer@b120000 {
 			compatible = "arm,armv7-timer-mem";
 			reg = <0x0b120000 0x1000>;
-- 
2.34.1

Re: [PATCH V3 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support

[Krzysztof Kozlowski]

On 25/09/2023 12:28, Gokul Sriram Palanisamy wrote:
> Add the APCS, A53 PLL, cpu-opp-table nodes to set
> the CPU frequency at 800MHz (idle) or 1.008GHz.
> 
> Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/ipq5018.dtsi | 40 +++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
> 

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH V3 0/3] Add APSS clock driver support for IPQ5018

[Gokul Sriram P]

Hi everyone, a gentle remainder to review and acknowledge the change.

Regards,
Gokul

On 9/25/2023 3:58 PM, Gokul Sriram Palanisamy wrote:
> This series adds support for the APSS clock to bump the CPU frequency
> above 800MHz. APSS PLL found in the IPQ5018 is of type Stromer.
>
> - The first patch in the series adds the required a53pll compatible.
>
> - The second patch reuses Stormer Plus PLL offsets, adds configuration values
>    for Stromer.
>
> - The third patch adds dts nodes to enable the pll along with the cpu
>    operating frequency table.
>
> This series depends on below series
> https://patchwork.kernel.org/project/linux-arm-msm/cover/20230913-gpll_cleanup-v2-0-c8ceb1a37680@quicinc.com/
>
> Changes in v3:
> - Addressed review comment by Dmitry in patch 3.
>
> Changes in v2:
> - Addressed review comments
> - Adds dependency on above mentioned patch series for dropping
>    CLK_SET_RATE_PARENT flag from GPLL clocks, GPLL0 clock provider for
>    mailbox
> - Add CPU operating point at 800MHz based on the review comments.
>
> Gokul Sriram Palanisamy (3):
>    dt-bindings: clock: qcom,a53pll: add IPQ5018 compatible
>    clk: qcom: apss-ipq-pll: add support for IPQ5018
>    arm64: dts: qcom: ipq5018: enable the CPUFreq support
>
>   .../bindings/clock/qcom,a53pll.yaml           |  1 +
>   arch/arm64/boot/dts/qcom/ipq5018.dtsi         | 40 +++++++++++++++++++
>   drivers/clk/qcom/apss-ipq-pll.c               | 21 ++++++++++
>   3 files changed, 62 insertions(+)
>

Re: [PATCH V3 0/3] Add APSS clock driver support for IPQ5018

[Krzysztof Kozlowski]

On 27/10/2023 10:02, Gokul Sriram P wrote:
> Hi everyone, a gentle remainder to review and acknowledge the change.

Really everyone? So what do you miss from me? Any why do you think that
I did not perform my duties?

Best regards,
Krzysztof

Re: (subset) [PATCH V3 0/3] Add APSS clock driver support for IPQ5018

[Bjorn Andersson]

On Mon, 25 Sep 2023 15:58:23 +0530, Gokul Sriram Palanisamy wrote:
> This series adds support for the APSS clock to bump the CPU frequency
> above 800MHz. APSS PLL found in the IPQ5018 is of type Stromer.
> 
> - The first patch in the series adds the required a53pll compatible.
> 
> - The second patch reuses Stormer Plus PLL offsets, adds configuration values
>   for Stromer.
> 
> [...]

Applied, thanks!

[3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support
      commit: 3e4b53e04281ed3d9c7a4329c027097265c04d54

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>