From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC11B184E; Sat, 11 Oct 2025 00:08:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760141340; cv=none; b=fOHKE1Q4AsNGhiyJgZd3IEBHqN/01swgoOJ2mPHCU8SccIxeK9OCGmFZyaYvlDM3q4wtqW7caUZya2GAl4js6HZYA4H5wYAw0V4Hl7EbukMnjkoxNW4SdGeA8ASCA5pWFz1J9fj/0tbeFQfAN7E+v3Kzl5tzLk4NBIpRXDrTUW8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760141340; c=relaxed/simple; bh=vVjv/jkicIgDmt3y7lRnnSSaepw4Ybyi1G9k7ei9veA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=e4OjEWXJPTpQMiNI6QIBec9u9m6tdKtTDAtCjp8iEBEHujbteHa/5+ZnX68aEY3d8cOPb5wii3h/HLKf8SOVdRW3CjoNvKrQicekcYhzrkZqiMnR3jHVK7mn06V2JJjcqgE1hsvK1Dmb3Ha8mmHAcjKSLnQO1xw2lJSKrlpfYAI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=G3up2+qx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="G3up2+qx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9E01FC4CEF1; Sat, 11 Oct 2025 00:08:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760141339; bh=vVjv/jkicIgDmt3y7lRnnSSaepw4Ybyi1G9k7ei9veA=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=G3up2+qx9y2G3wkWHB1NdGx1RVFwoeM8rBaVOD+ERCM94xt9KZkJo4zsqvAUcrhu/ z2jAG5PrSDjQKMW0Fat8WDvUZ/AFXzHSUrxOlK3zHswrlSk12pY1+vcz+mUgc0hxY/ Vfnwhug2ar83M+h+j5byUex/Y7676kzze0Z0m+UaWl4JtUCIvaQFiE9A9CxaMTLT3W I/ZB4GvG5qPDfrUkreGnCAN4B/YtdsYnejogva+04eYSux8k5RnLgSiq01C9xA4XMM KAM12MZlrEHqhUSHyFOzUm1+jNEVhld48VB5I9cGvBOEBXaOiRzqG46c/KDHyNbTVH kPqD2gjcYNgCA== Message-ID: <066a9598-ad30-4327-be68-87299bba6fda@kernel.org> Date: Sat, 11 Oct 2025 02:08:49 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/4] dt-bindings: usb: dwc3: Add Google Tensor G5 DWC3 To: Roy Luo , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Thinh Nguyen , Philipp Zabel , Peter Griffin , =?UTF-8?Q?Andr=C3=A9_Draszik?= , Tudor Ambarus Cc: Joy Chakraborty , Naveen Kumar , Badhri Jagan Sridharan , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org References: <20251010201607.1190967-1-royluo@google.com> <20251010201607.1190967-2-royluo@google.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 10/10/2025 22:16, Roy Luo wrote: > Document the device tree bindings for the DWC3 USB controller found in > Google Tensor SoCs, starting with the G5 generation. > > The Tensor G5 silicon represents a complete architectural departure from > previous generations (like gs101), including entirely new clock/reset > schemes, top-level wrapper and register interface. Consequently, > existing Samsung/Exynos DWC3 USB bindings are incompatible, necessitating > this new device tree binding. > > The USB controller on Tensor G5 is based on Synopsys DWC3 IP and features > Dual-Role Device single port with hibernation support. You still mix, completely unnecessarily, subsystems. For Greg this is actually even undesired, but regardless don't do this for any cases because it just makes everything slower or more difficult to apply. Really, think how maintainers should deal with your patches. > > Signed-off-by: Roy Luo > --- > .../bindings/usb/google,gs5-dwc3.yaml | 141 ++++++++++++++++++ > 1 file changed, 141 insertions(+) > create mode 100644 Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml > > diff --git a/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml b/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml > new file mode 100644 > index 000000000000..6fadea7f41e8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml > @@ -0,0 +1,141 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +# Copyright (c) 2025, Google LLC > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/usb/google,gs5-dwc3.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Google Tensor Series (G5+) DWC3 USB SoC Controller > + > +maintainers: > + - Roy Luo > + > +description: > + Describes the DWC3 USB controller block implemented on Google Tensor SoCs, > + starting with the G5 generation. Based on Synopsys DWC3 IP, the controller > + features Dual-Role Device single port with hibernation add-on. > + > +properties: > + compatible: > + const: google,gs5-dwc3 > + > + reg: > + items: > + - description: Core DWC3 IP registers. > + - description: USB host controller configuration registers. > + - description: USB custom interrrupts control registers. > + > + reg-names: > + items: > + - const: dwc3_core > + - const: host_cfg > + - const: usbint_cfg > + > + interrupts: > + items: > + - description: Core DWC3 interrupt. > + - description: High speed power management event for remote wakeup from hibernation. > + - description: Super speed power management event for remote wakeup from hibernation. Wrap at 80 (see coding style) or just shorten these. > + > + interrupt-names: > + items: > + - const: dwc_usb3 So just "core"? > + - const: hs_pme > + - const: ss_pme > + > + clocks: > + items: > + - description: Non-sticky module clock. > + - description: Sticky module clock. > + - description: USB2 PHY APB clock. This looks wrong. This is not the USB2 phy, so how can it consume APB clock? > + > + clock-names: > + items: > + - const: non_sticky > + - const: sticky > + - const: u2phy_apb > + > + resets: > + items: > + - description: Non-sticky module reset. > + - description: Sticky module reset. > + - description: USB2 PHY APB reset. This as well. > + - description: DRD bus reset. > + - description: Top-level reset. > + > + reset-names: > + items: > + - const: non_sticky > + - const: sticky > + - const: u2phy_apb > + - const: drd_bus > + - const: top Best regards, Krzysztof