From: Stephen Boyd <sboyd@kernel.org>
To: Chen Wang <unicornxw@gmail.com>,
aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org,
devicetree@vger.kernel.org, guoren@kernel.org,
haijiao.liu@sophgo.com, inochiama@outlook.com,
jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, mturquette@baylibre.com,
palmer@dabbelt.com, paul.walmsley@sifive.com,
richardcochran@gmail.com, robh+dt@kernel.org,
samuel.holland@sifive.com, xiaoguang.xing@sophgo.com
Cc: Chen Wang <unicorn_wang@outlook.com>
Subject: Re: [PATCH v11 2/5] dt-bindings: clock: sophgo: add RP gate clocks for SG2042
Date: Fri, 08 Mar 2024 18:15:12 -0800 [thread overview]
Message-ID: <066c6fa4b537561ae6b20388a5497d9e.sboyd@kernel.org> (raw)
In-Reply-To: <49faf8ff209673e27338d4b83948ade86b3c66e4.1708397315.git.unicorn_wang@outlook.com>
Quoting Chen Wang (2024-02-19 19:08:59)
> +required:
> + - compatible
> + - reg
> + - clocks
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + clock-controller@10000000 {
This is the same address as the pll binding before this. How does that
work? It's the same register area as the pll node. The resulting DTB
should only have one compatible for this node.
> + compatible = "sophgo,sg2042-rpgate";
> + reg = <0x10000000 0x10000>;
> + clocks = <&clkgen 85>;
> + #clock-cells = <1>;
> + };
next prev parent reply other threads:[~2024-03-09 2:15 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-20 3:08 [PATCH v11 0/5] riscv: sophgo: add clock support for sg2042 Chen Wang
2024-02-20 3:08 ` [PATCH v11 1/5] dt-bindings: clock: sophgo: add pll clocks for SG2042 Chen Wang
2024-03-09 2:12 ` Stephen Boyd
2024-03-10 1:35 ` Chen Wang
2024-02-20 3:08 ` [PATCH v11 2/5] dt-bindings: clock: sophgo: add RP gate " Chen Wang
2024-02-23 0:17 ` Rob Herring
2024-03-09 2:12 ` Stephen Boyd
2024-03-09 2:15 ` Stephen Boyd [this message]
2024-03-10 1:28 ` Chen Wang
2024-02-20 3:09 ` [PATCH v11 3/5] dt-bindings: clock: sophgo: add clkgen " Chen Wang
2024-02-23 0:18 ` Rob Herring
2024-03-09 2:12 ` Stephen Boyd
2024-02-20 3:09 ` [PATCH v11 4/5] clk: sophgo: Add SG2042 clock driver Chen Wang
2024-02-23 3:01 ` Chen Wang
2024-02-27 1:09 ` Chen Wang
2024-03-09 2:11 ` Stephen Boyd
2024-03-19 7:40 ` Chen Wang
2024-02-20 3:10 ` [PATCH v11 5/5] riscv: dts: add clock generator for Sophgo SG2042 SoC Chen Wang
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