[PATCH v5 0/4] Add driver nodes for MT8192 SoC

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* [PATCH v5 0/4] Add driver nodes for MT8192 SoC
@ 2022-03-30 13:38 Allen-KH Cheng
  2022-03-30 13:38 ` [PATCH v5 1/4] arm64: dts: mt8192: Add PCIe node Allen-KH Cheng
                   ` (3 more replies)
  0 siblings, 4 replies; 10+ messages in thread
From: Allen-KH Cheng @ 2022-03-30 13:38 UTC (permalink / raw)
  To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski
  Cc: Project_Global_Chrome_Upstream_Group, devicetree,
	linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
	Ryder Lee, Hui Liu, Allen-KH Cheng

Add driver nodes for MT8192 SoC and this series are based on matthias.bgg/linux.git, v5.18-next/dts64
(PCIe, mmc, H264 venc, vcodec lat and core nodes)

In order to track the dependencies of some patches, I remove them from this series and will
send a new series for each node. (spmi, gce, infracfg_rst, mipi_tx, dpi, display, dsi, gce info and pwm)

changes since v4:
- remove some patches from this series.
- PCIe: remove reset node, correct the clk names
- mmc: reserve msdc node
- vcodec: correct the clk names (remove vdec- prefix)

changes since v3:
- add patch: add the mmsys reset bit to reset the dsi0
- dsi0: use mmsys for reset controller support
- mmc: reorder clocks as specified in the dt-bindings
- vcodec: use ranges for regs of subnodes

changes since v2:
- rebase on next-20220304
- remove power domains controller patch from series (already in linux-next)
- scp: fix indentation
- t-phy: change node name from usb-phy to t-phy and set ranges address
- usb: change node name from xhci to usb and add disabled status
- audsys: syscon: add increasing the address range's length info in commit message
- infracfg_rst: add simple-mfd info in commit message
- nor_flash: add Fixes tag d0a197a0d064a in  commit message
- efuse: use lower case characters
- mmc: use single line for reg
- mipi_tx: change node name from mipi-dphy to dsi-phy, drop clock-names and add disabled status
- m4u and smi: fixing the formatting of the mediatek,larbs properties and remove smi-id property
- H264 venc: fix indentation, remove '0x' prefix for node address
- vcodec lat and core: use '-' instead of '_' in the node name, fix indentation and
  set mtk-vcodec-lat and mtk-vcodec-core as subnodes of vcodec-dec
- dpi: add disabled status
- display: appended "mediatek,mt8183-disp-aal" for ccorr
- dsi: fix indentation and add disabled status
- gce info: add drivers' CMDQ support inn commit message
- pwm: add disabled status
- i2c aliases: move the aliases at the board level.

changes since v1:
- add usb-phy node for xhci node
- move infracfg_rst patch in front of PCIe patch
- add display nodes, i2c aliases and pwm node.

Allen-KH Cheng (4):
  arm64: dts: mt8192: Add PCIe node
  arm64: dts: mt8192: Add mmc device nodes
  arm64: dts: mt8192: Add H264 venc device node
  arm64: dts: mt8192: Add vcodec lat and core nodes

 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 150 +++++++++++++++++++++++
 1 file changed, 150 insertions(+)

-- 
2.18.0


^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH v5 1/4] arm64: dts: mt8192: Add PCIe node
  2022-03-30 13:38 [PATCH v5 0/4] Add driver nodes for MT8192 SoC Allen-KH Cheng
@ 2022-03-30 13:38 ` Allen-KH Cheng
  2022-03-31 11:56   ` Matthias Brugger
  2022-03-30 13:38 ` [PATCH v5 2/4] arm64: dts: mt8192: Add mmc device nodes Allen-KH Cheng
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 10+ messages in thread
From: Allen-KH Cheng @ 2022-03-30 13:38 UTC (permalink / raw)
  To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski
  Cc: Project_Global_Chrome_Upstream_Group, devicetree,
	linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
	Ryder Lee, Hui Liu, Allen-KH Cheng

Add PCIe node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 35 ++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 579abbf4488e..69e8d1934d53 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -716,6 +716,41 @@
 			status = "disabled";
 		};
 
+		pcie: pcie@11230000 {
+			compatible = "mediatek,mt8192-pcie";
+			device_type = "pci";
+			reg = <0 0x11230000 0 0x2000>;
+			reg-names = "pcie-mac";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>,
+				 <&infracfg CLK_INFRA_PCIE_TL_26M>,
+				 <&infracfg CLK_INFRA_PCIE_TL_96M>,
+				 <&infracfg CLK_INFRA_PCIE_TL_32K>,
+				 <&infracfg CLK_INFRA_PCIE_PERI_26M>,
+				 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>;
+			clock-names = "pl_250m", "tl_26m", "tl_96m",
+				      "tl_32k", "peri_26m", "top_133m";
+			assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
+			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
+			bus-range = <0x00 0xff>;
+			ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
+				 <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+					<0 0 0 2 &pcie_intc0 1>,
+					<0 0 0 3 &pcie_intc0 2>,
+					<0 0 0 4 &pcie_intc0 3>;
+
+			pcie_intc0: interrupt-controller {
+				interrupt-controller;
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+			};
+		};
+
 		nor_flash: spi@11234000 {
 			compatible = "mediatek,mt8192-nor";
 			reg = <0 0x11234000 0 0xe0>;
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 10+ messages in thread

* Re: [PATCH v5 1/4] arm64: dts: mt8192: Add PCIe node
  2022-03-30 13:38 ` [PATCH v5 1/4] arm64: dts: mt8192: Add PCIe node Allen-KH Cheng
@ 2022-03-31 11:56   ` Matthias Brugger
  0 siblings, 0 replies; 10+ messages in thread
From: Matthias Brugger @ 2022-03-31 11:56 UTC (permalink / raw)
  To: Allen-KH Cheng, Rob Herring, Krzysztof Kozlowski
  Cc: Project_Global_Chrome_Upstream_Group, devicetree,
	linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
	Ryder Lee, Hui Liu



On 30/03/2022 15:38, Allen-KH Cheng wrote:
> Add PCIe node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

I wonder why you left Nicolas Reviewed-by but not the one from Angelo. Anyway 
when sending a new version, be sure to drop the reviewed-by tags if there are 
substantial changes in the patch. We can argue if changing the clock names is a 
substantial change or not. Maybe that's why you left just one reviewed-by tag ;)
I'm just joking, I'll add the other tag myself.

Applied thanks.

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 35 ++++++++++++++++++++++++
>   1 file changed, 35 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 579abbf4488e..69e8d1934d53 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -716,6 +716,41 @@
>   			status = "disabled";
>   		};
>   
> +		pcie: pcie@11230000 {
> +			compatible = "mediatek,mt8192-pcie";
> +			device_type = "pci";
> +			reg = <0 0x11230000 0 0x2000>;
> +			reg-names = "pcie-mac";
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>,
> +				 <&infracfg CLK_INFRA_PCIE_TL_26M>,
> +				 <&infracfg CLK_INFRA_PCIE_TL_96M>,
> +				 <&infracfg CLK_INFRA_PCIE_TL_32K>,
> +				 <&infracfg CLK_INFRA_PCIE_PERI_26M>,
> +				 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>;
> +			clock-names = "pl_250m", "tl_26m", "tl_96m",
> +				      "tl_32k", "peri_26m", "top_133m";
> +			assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
> +			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
> +			bus-range = <0x00 0xff>;
> +			ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
> +				 <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0 0 0 7>;
> +			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
> +					<0 0 0 2 &pcie_intc0 1>,
> +					<0 0 0 3 &pcie_intc0 2>,
> +					<0 0 0 4 &pcie_intc0 3>;
> +
> +			pcie_intc0: interrupt-controller {
> +				interrupt-controller;
> +				#address-cells = <0>;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
>   		nor_flash: spi@11234000 {
>   			compatible = "mediatek,mt8192-nor";
>   			reg = <0 0x11234000 0 0xe0>;

^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH v5 2/4] arm64: dts: mt8192: Add mmc device nodes
  2022-03-30 13:38 [PATCH v5 0/4] Add driver nodes for MT8192 SoC Allen-KH Cheng
  2022-03-30 13:38 ` [PATCH v5 1/4] arm64: dts: mt8192: Add PCIe node Allen-KH Cheng
@ 2022-03-30 13:38 ` Allen-KH Cheng
  2022-03-31 12:02   ` Matthias Brugger
  2022-03-30 13:38 ` [PATCH v5 3/4] arm64: dts: mt8192: Add H264 venc device node Allen-KH Cheng
  2022-03-30 13:38 ` [PATCH v5 4/4] arm64: dts: mt8192: Add vcodec lat and core nodes Allen-KH Cheng
  3 siblings, 1 reply; 10+ messages in thread
From: Allen-KH Cheng @ 2022-03-30 13:38 UTC (permalink / raw)
  To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski
  Cc: Project_Global_Chrome_Upstream_Group, devicetree,
	linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
	Ryder Lee, Hui Liu, Allen-KH Cheng

Add mmc nodes for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 32 ++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 69e8d1934d53..c1057878e2c6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -991,6 +991,38 @@
 			#clock-cells = <1>;
 		};
 
+		mmc0: mmc@11f60000 {
+			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+			reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>;
+			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+				 <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
+				 <&msdc_top CLK_MSDC_TOP_SRC_0P>,
+				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
+				 <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
+				 <&msdc_top CLK_MSDC_TOP_AXI>,
+				 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
+			clock-names = "source", "hclk", "source_cg", "sys_cg",
+				      "pclk_cg", "axi_cg", "ahb_cg";
+			status = "disabled";
+		};
+
+		mmc1: mmc@11f70000 {
+			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+			reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>;
+			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
+				 <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
+				 <&msdc_top CLK_MSDC_TOP_SRC_1P>,
+				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
+				 <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
+				 <&msdc_top CLK_MSDC_TOP_AXI>,
+				 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
+			clock-names = "source", "hclk", "source_cg", "sys_cg",
+				      "pclk_cg", "axi_cg", "ahb_cg";
+			status = "disabled";
+		};
+
 		mfgcfg: clock-controller@13fbf000 {
 			compatible = "mediatek,mt8192-mfgcfg";
 			reg = <0 0x13fbf000 0 0x1000>;
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 10+ messages in thread

* Re: [PATCH v5 2/4] arm64: dts: mt8192: Add mmc device nodes
  2022-03-30 13:38 ` [PATCH v5 2/4] arm64: dts: mt8192: Add mmc device nodes Allen-KH Cheng
@ 2022-03-31 12:02   ` Matthias Brugger
       [not found]     ` <ccd28405c8f2c420354f3355fc9d4ef1dd7ea35d.camel@mediatek.com>
  0 siblings, 1 reply; 10+ messages in thread
From: Matthias Brugger @ 2022-03-31 12:02 UTC (permalink / raw)
  To: Allen-KH Cheng, Rob Herring, Krzysztof Kozlowski
  Cc: Project_Global_Chrome_Upstream_Group, devicetree,
	linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
	Ryder Lee, Hui Liu



On 30/03/2022 15:38, Allen-KH Cheng wrote:
> Add mmc nodes for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

You forgot to disable the msdc clock node, which I understood we agreed on in in 
v4. I would consider this change as an substantial one, so in this case please 
delete the reviewed-by tags.

Regards,
Matthias

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 32 ++++++++++++++++++++++++
>   1 file changed, 32 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 69e8d1934d53..c1057878e2c6 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -991,6 +991,38 @@
>   			#clock-cells = <1>;
>   		};
>   
> +		mmc0: mmc@11f60000 {
> +			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
> +			reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>;
> +			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
> +				 <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
> +				 <&msdc_top CLK_MSDC_TOP_SRC_0P>,
> +				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
> +				 <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
> +				 <&msdc_top CLK_MSDC_TOP_AXI>,
> +				 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
> +			clock-names = "source", "hclk", "source_cg", "sys_cg",
> +				      "pclk_cg", "axi_cg", "ahb_cg";
> +			status = "disabled";
> +		};
> +
> +		mmc1: mmc@11f70000 {
> +			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
> +			reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>;
> +			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
> +				 <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
> +				 <&msdc_top CLK_MSDC_TOP_SRC_1P>,
> +				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
> +				 <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
> +				 <&msdc_top CLK_MSDC_TOP_AXI>,
> +				 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
> +			clock-names = "source", "hclk", "source_cg", "sys_cg",
> +				      "pclk_cg", "axi_cg", "ahb_cg";
> +			status = "disabled";
> +		};
> +
>   		mfgcfg: clock-controller@13fbf000 {
>   			compatible = "mediatek,mt8192-mfgcfg";
>   			reg = <0 0x13fbf000 0 0x1000>;

^ permalink raw reply	[flat|nested] 10+ messages in thread

[parent not found: <ccd28405c8f2c420354f3355fc9d4ef1dd7ea35d.camel@mediatek.com>]

* Re: [PATCH v5 2/4] arm64: dts: mt8192: Add mmc device nodes
       [not found]     ` <ccd28405c8f2c420354f3355fc9d4ef1dd7ea35d.camel@mediatek.com>
@ 2022-03-31 14:19       ` Matthias Brugger
  0 siblings, 0 replies; 10+ messages in thread
From: Matthias Brugger @ 2022-03-31 14:19 UTC (permalink / raw)
  To: allen-kh.cheng, Rob Herring, Krzysztof Kozlowski
  Cc: Project_Global_Chrome_Upstream_Group, devicetree,
	linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
	Ryder Lee, Hui Liu



On 31/03/2022 14:48, allen-kh.cheng wrote:
> Hi Matthias,
> 
> On Thu, 2022-03-31 at 14:02 +0200, Matthias Brugger wrote:
>>
>> On 30/03/2022 15:38, Allen-KH Cheng wrote:
>>> Add mmc nodes for mt8192 SoC.
>>>
>>> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>>> Reviewed-by: AngeloGioacchino Del Regno <
>>> angelogioacchino.delregno@collabora.com>
>>
>> You forgot to disable the msdc clock node, which I understood we
>> agreed on in in
>> v4. I would consider this change as an substantial one, so in this
>> case please
>> delete the reviewed-by tags.
>>
>> Regards,
>> Matthias
>>
> 
> Is it ok I send a new patch for this instead of a series?

Yes sure.

Matthias

> 
> Best regards,
> Allen
> 
>>> ---
>>>    arch/arm64/boot/dts/mediatek/mt8192.dtsi | 32
>>> ++++++++++++++++++++++++
>>>    1 file changed, 32 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> index 69e8d1934d53..c1057878e2c6 100644
>>> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> @@ -991,6 +991,38 @@
>>>    			#clock-cells = <1>;
>>>    		};
>>>    
>>> +		mmc0: mmc@11f60000 {
>>> +			compatible = "mediatek,mt8192-mmc",
>>> "mediatek,mt8183-mmc";
>>> +			reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0
>>> 0x1000>;
>>> +			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH
>>> 0>;
>>> +			clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
>>> +				 <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
>>> +				 <&msdc_top CLK_MSDC_TOP_SRC_0P>,
>>> +				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
>>> +				 <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
>>> +				 <&msdc_top CLK_MSDC_TOP_AXI>,
>>> +				 <&msdc_top
>>> CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
>>> +			clock-names = "source", "hclk", "source_cg",
>>> "sys_cg",
>>> +				      "pclk_cg", "axi_cg", "ahb_cg";
>>> +			status = "disabled";
>>> +		};
>>> +
>>> +		mmc1: mmc@11f70000 {
>>> +			compatible = "mediatek,mt8192-mmc",
>>> "mediatek,mt8183-mmc";
>>> +			reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0
>>> 0x1000>;
>>> +			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH
>>> 0>;
>>> +			clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
>>> +				 <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
>>> +				 <&msdc_top CLK_MSDC_TOP_SRC_1P>,
>>> +				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
>>> +				 <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
>>> +				 <&msdc_top CLK_MSDC_TOP_AXI>,
>>> +				 <&msdc_top
>>> CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
>>> +			clock-names = "source", "hclk", "source_cg",
>>> "sys_cg",
>>> +				      "pclk_cg", "axi_cg", "ahb_cg";
>>> +			status = "disabled";
>>> +		};
>>> +
>>>    		mfgcfg: clock-controller@13fbf000 {
>>>    			compatible = "mediatek,mt8192-mfgcfg";
>>>    			reg = <0 0x13fbf000 0 0x1000>;
> 

^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH v5 3/4] arm64: dts: mt8192: Add H264 venc device node
  2022-03-30 13:38 [PATCH v5 0/4] Add driver nodes for MT8192 SoC Allen-KH Cheng
  2022-03-30 13:38 ` [PATCH v5 1/4] arm64: dts: mt8192: Add PCIe node Allen-KH Cheng
  2022-03-30 13:38 ` [PATCH v5 2/4] arm64: dts: mt8192: Add mmc device nodes Allen-KH Cheng
@ 2022-03-30 13:38 ` Allen-KH Cheng
  2022-03-31 12:07   ` Matthias Brugger
  2022-03-30 13:38 ` [PATCH v5 4/4] arm64: dts: mt8192: Add vcodec lat and core nodes Allen-KH Cheng
  3 siblings, 1 reply; 10+ messages in thread
From: Allen-KH Cheng @ 2022-03-30 13:38 UTC (permalink / raw)
  To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski
  Cc: Project_Global_Chrome_Upstream_Group, devicetree,
	linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
	Ryder Lee, Hui Liu, Allen-KH Cheng

Adds H264 venc node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index c1057878e2c6..3d61238fb102 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1166,6 +1166,29 @@
 			power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
 		};
 
+		vcodec_enc: vcodec@17020000 {
+			compatible = "mediatek,mt8192-vcodec-enc";
+			reg = <0 0x17020000 0 0x2000>;
+			iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
+				 <&iommu0 M4U_PORT_L7_VENC_REC>,
+				 <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
+				 <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
+				 <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
+				 <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
+				 <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
+				 <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
+				 <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
+				 <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
+				 <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
+			interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;
+			mediatek,scp = <&scp>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
+			clocks = <&vencsys CLK_VENC_SET1_VENC>;
+			clock-names = "venc-set1";
+			assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
+		};
+
 		camsys: clock-controller@1a000000 {
 			compatible = "mediatek,mt8192-camsys";
 			reg = <0 0x1a000000 0 0x1000>;
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 10+ messages in thread

* Re: [PATCH v5 3/4] arm64: dts: mt8192: Add H264 venc device node
  2022-03-30 13:38 ` [PATCH v5 3/4] arm64: dts: mt8192: Add H264 venc device node Allen-KH Cheng
@ 2022-03-31 12:07   ` Matthias Brugger
  0 siblings, 0 replies; 10+ messages in thread
From: Matthias Brugger @ 2022-03-31 12:07 UTC (permalink / raw)
  To: Allen-KH Cheng, Rob Herring, Krzysztof Kozlowski
  Cc: Project_Global_Chrome_Upstream_Group, devicetree,
	linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
	Ryder Lee, Hui Liu



On 30/03/2022 15:38, Allen-KH Cheng wrote:
> Adds H264 venc node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

I told you in v4 that I'll apply it, but it's not in the repo. It seemed I 
accidentely dropped that one, so I apply it again now. If you realize something 
like this in the future don't hesitate to tell me :)

Thanks!

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 23 +++++++++++++++++++++++
>   1 file changed, 23 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index c1057878e2c6..3d61238fb102 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1166,6 +1166,29 @@
>   			power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
>   		};
>   
> +		vcodec_enc: vcodec@17020000 {
> +			compatible = "mediatek,mt8192-vcodec-enc";
> +			reg = <0 0x17020000 0 0x2000>;
> +			iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
> +				 <&iommu0 M4U_PORT_L7_VENC_REC>,
> +				 <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
> +				 <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
> +				 <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
> +				 <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
> +				 <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
> +				 <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
> +				 <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
> +				 <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
> +				 <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
> +			interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;
> +			mediatek,scp = <&scp>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
> +			clocks = <&vencsys CLK_VENC_SET1_VENC>;
> +			clock-names = "venc-set1";
> +			assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
> +		};
> +
>   		camsys: clock-controller@1a000000 {
>   			compatible = "mediatek,mt8192-camsys";
>   			reg = <0 0x1a000000 0 0x1000>;

^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH v5 4/4] arm64: dts: mt8192: Add vcodec lat and core nodes
  2022-03-30 13:38 [PATCH v5 0/4] Add driver nodes for MT8192 SoC Allen-KH Cheng
                   ` (2 preceding siblings ...)
  2022-03-30 13:38 ` [PATCH v5 3/4] arm64: dts: mt8192: Add H264 venc device node Allen-KH Cheng
@ 2022-03-30 13:38 ` Allen-KH Cheng
  2022-03-31 14:09   ` Matthias Brugger
  3 siblings, 1 reply; 10+ messages in thread
From: Allen-KH Cheng @ 2022-03-30 13:38 UTC (permalink / raw)
  To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski
  Cc: Project_Global_Chrome_Upstream_Group, devicetree,
	linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
	Ryder Lee, Hui Liu, Allen-KH Cheng

Add vcodec lat and core nodes for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60 ++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 3d61238fb102..0b2b52a8f5ed 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1115,6 +1115,66 @@
 			power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
 		};
 
+		vcodec_dec: vcodec-dec@16000000 {
+			compatible = "mediatek,mt8192-vcodec-dec";
+			reg = <0 0x16000000 0 0x1000>;	/* VDEC_SYS */
+			mediatek,scp = <&scp>;
+			iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
+			dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0 0 0 0x16000000 0 0x26000>;
+
+			vcodec_lat: vcodec-lat@10000 {
+				compatible = "mediatek,mtk-vcodec-lat";
+				reg = <0x0 0x10000 0 0x800>;		/* VDEC_MISC */
+				interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
+				iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
+				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+					 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+					 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
+					 <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+					 <&topckgen CLK_TOP_MAINPLL_D4>;
+				clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
+				assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+				assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+				power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+			};
+
+			vcodec_core: vcodec-core@25000 {
+				compatible = "mediatek,mtk-vcodec-core";
+				reg = <0 0x25000 0 0x1000>;	/* VDEC_CORE_MISC */
+				interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
+				iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
+				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+					 <&vdecsys CLK_VDEC_VDEC>,
+					 <&vdecsys CLK_VDEC_LAT>,
+					 <&vdecsys CLK_VDEC_LARB1>,
+					 <&topckgen CLK_TOP_MAINPLL_D4>;
+				clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
+				assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+				assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+				power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+			};
+		};
+
 		larb5: larb@1600d000 {
 			compatible = "mediatek,mt8192-smi-larb";
 			reg = <0 0x1600d000 0 0x1000>;
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 10+ messages in thread

* Re: [PATCH v5 4/4] arm64: dts: mt8192: Add vcodec lat and core nodes
  2022-03-30 13:38 ` [PATCH v5 4/4] arm64: dts: mt8192: Add vcodec lat and core nodes Allen-KH Cheng
@ 2022-03-31 14:09   ` Matthias Brugger
  0 siblings, 0 replies; 10+ messages in thread
From: Matthias Brugger @ 2022-03-31 14:09 UTC (permalink / raw)
  To: Allen-KH Cheng, Rob Herring, Krzysztof Kozlowski
  Cc: Project_Global_Chrome_Upstream_Group, devicetree,
	linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
	Ryder Lee, Hui Liu



On 30/03/2022 15:38, Allen-KH Cheng wrote:
> Add vcodec lat and core nodes for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Please drop reviewed-by as of comments below.

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60 ++++++++++++++++++++++++
>   1 file changed, 60 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 3d61238fb102..0b2b52a8f5ed 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1115,6 +1115,66 @@
>   			power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
>   		};
>   
> +		vcodec_dec: vcodec-dec@16000000 {
> +			compatible = "mediatek,mt8192-vcodec-dec";
> +			reg = <0 0x16000000 0 0x1000>;	/* VDEC_SYS */
> +			mediatek,scp = <&scp>;
> +			iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> +			dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;

Change that was not part of the changelog. Please mention any change you make to 
the patch in the change log.

> +			#address-cells = <2>;
> +			#size-cells = <2>;

Binding description says address-cells and size-cells should be of value 1.


> +			ranges = <0 0 0 0x16000000 0 0x26000>;
> +
> +			vcodec_lat: vcodec-lat@10000 {
> +				compatible = "mediatek,mtk-vcodec-lat";
> +				reg = <0x0 0x10000 0 0x800>;		/* VDEC_MISC */

I suppose we would need to fix the reg value here then. Also IMHO the comment 
can be deleted.

> +				interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
> +				iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> +				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> +					 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> +					 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> +					 <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> +					 <&topckgen CLK_TOP_MAINPLL_D4>;
> +				clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
> +				assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> +				assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> +				power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
> +			};
> +
> +			vcodec_core: vcodec-core@25000 {
> +				compatible = "mediatek,mtk-vcodec-core";
> +				reg = <0 0x25000 0 0x1000>;	/* VDEC_CORE_MISC */

same here.

Regards,
Matthias

> +				interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
> +				iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> +				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> +					 <&vdecsys CLK_VDEC_VDEC>,
> +					 <&vdecsys CLK_VDEC_LAT>,
> +					 <&vdecsys CLK_VDEC_LARB1>,
> +					 <&topckgen CLK_TOP_MAINPLL_D4>;
> +				clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
> +				assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> +				assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> +				power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
> +			};
> +		};
> +
>   		larb5: larb@1600d000 {
>   			compatible = "mediatek,mt8192-smi-larb";
>   			reg = <0 0x1600d000 0 0x1000>;

^ permalink raw reply	[flat|nested] 10+ messages in thread

end of thread, other threads:[~2022-03-31 14:19 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-03-30 13:38 [PATCH v5 0/4] Add driver nodes for MT8192 SoC Allen-KH Cheng
2022-03-30 13:38 ` [PATCH v5 1/4] arm64: dts: mt8192: Add PCIe node Allen-KH Cheng
2022-03-31 11:56   ` Matthias Brugger
2022-03-30 13:38 ` [PATCH v5 2/4] arm64: dts: mt8192: Add mmc device nodes Allen-KH Cheng
2022-03-31 12:02   ` Matthias Brugger
     [not found]     ` <ccd28405c8f2c420354f3355fc9d4ef1dd7ea35d.camel@mediatek.com>
2022-03-31 14:19       ` Matthias Brugger
2022-03-30 13:38 ` [PATCH v5 3/4] arm64: dts: mt8192: Add H264 venc device node Allen-KH Cheng
2022-03-31 12:07   ` Matthias Brugger
2022-03-30 13:38 ` [PATCH v5 4/4] arm64: dts: mt8192: Add vcodec lat and core nodes Allen-KH Cheng
2022-03-31 14:09   ` Matthias Brugger

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