From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Yu Tu <yu.tu@amlogic.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Jerome Brunet <jbrunet@baylibre.com>,
Kevin Hilman <khilman@baylibre.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: kelvin.zhang@amlogic.com
Subject: Re: [PATCH V5 1/4] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver and bindings
Date: Wed, 23 Nov 2022 14:05:27 +0100 [thread overview]
Message-ID: <06fa6b50-bd69-c118-4c82-89d153fe049e@linaro.org> (raw)
In-Reply-To: <92b570ea-3ddc-8e91-5a7a-ed601bb7c02c@amlogic.com>
On 23/11/2022 12:16, Yu Tu wrote:
> Hi Krzysztof,
> Thank you for your reply.
>
> On 2022/11/23 18:08, Krzysztof Kozlowski wrote:
>> [ EXTERNAL EMAIL ]
>>
>> On 23/11/2022 03:13, Yu Tu wrote:
>>> Add the S4 PLL clock controller found and bindings in the s4 SoC family.
>>>
>>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>>> ---
>>> .../bindings/clock/amlogic,s4-pll-clkc.yaml | 51 +
>>
>> This is v5 and still bindings are here? Bindings are always separate
>> patches. Use subject prefixes matching the subsystem (git log --oneline
>> -- ...).
>>
>> And this was split, wasn't it? What happened here?!?
>
> Put bindings and clock driver patch together from Jerome. Maybe you can
> read this chat history.
> https://lore.kernel.or/all/1jy1v6z14n.fsf@starbuckisacylon.baylibre.com/
Link does not explain me anything. It mentions series, which is totally
different than mixing it one patch!
Anyway you should have warnings from checkpatch.
Bindings are always separate patches.
(...)
>>
>>> +
>>> +properties:
>>> + compatible:
>>> + const: amlogic,s4-pll-clkc
>>> +
>>> + reg:
>>> + maxItems: 1
>>> +
>>> + clocks:
>>> + maxItems: 1
>>> +
>>> + clock-names:
>>> + items:
>>> + - const: xtal
>>> +
>>> + "#clock-cells":
>>> + const: 1
>>> +
>>> +required:
>>> + - compatible
>>> + - reg
>>> + - clocks
>>> + - clock-names
>>> + - "#clock-cells"
>>> +
>>> +additionalProperties: false
>>> +
>>> +examples:
>>> + - |
>>> + clkc_pll: clock-controller@fe008000 {
>>> + compatible = "amlogic,s4-pll-clkc";
>>> + reg = <0xfe008000 0x1e8>;
>>> + clocks = <&xtal>;
>>> + clock-names = "xtal";
>>> + #clock-cells = <1>;
>>> + };
>>
>>
>>> +#endif /* __MESON_S4_PLL_H__ */
>>> diff --git a/include/dt-bindings/clock/amlogic,s4-pll-clkc.h b/include/dt-bindings/clock/amlogic,s4-pll-clkc.h
>>> new file mode 100644
>>> index 000000000000..345f87023886
>>> --- /dev/null
>>> +++ b/include/dt-bindings/clock/amlogic,s4-pll-clkc.h
>>
>> This belongs to bindings patch, not driver.
>>
>>> @@ -0,0 +1,30 @@
>>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>>> +/*
>>> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
>>> + * Author: Yu Tu <yu.tu@amlogic.com>
>>> + */
>>> +
>>> +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H
>>> +#define _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H
>>> +
>>> +/*
>>> + * CLKID index values
>>> + */
>>> +
>>> +#define CLKID_FIXED_PLL 1
>>> +#define CLKID_FCLK_DIV2 3
>>
>> Indexes start from 0 and are incremented by 1. Not by 2.
>>
>> NAK.
>
> I remember Jerome discussing this with you.You can look at this
> submission history.
> https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
You pointed to my arguments, so what is this proving? That you ignored
feedback? Or was there some other mail?
Best regards,
Krzysztof
next prev parent reply other threads:[~2022-11-23 13:26 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-23 2:13 [PATCH V5 0/4] Add S4 SoC PLL and Peripheral clock controller Yu Tu
2022-11-23 2:13 ` [PATCH V5 1/4] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver and bindings Yu Tu
2022-11-23 10:08 ` Krzysztof Kozlowski
2022-11-23 11:16 ` Yu Tu
2022-11-23 13:05 ` Krzysztof Kozlowski [this message]
2022-11-23 13:23 ` Neil Armstrong
2022-11-23 13:53 ` Krzysztof Kozlowski
2022-11-25 9:23 ` Jerome Brunet
2022-11-28 7:39 ` Yu Tu
2022-11-28 12:33 ` Jerome Brunet
2022-11-28 13:30 ` Yu Tu
2022-12-01 8:36 ` neil.armstrong
2022-12-01 11:33 ` Yu Tu
2022-11-23 13:54 ` Yu Tu
2022-11-23 13:57 ` neil.armstrong
2022-11-23 2:13 ` [PATCH V5 2/4] arm64: dts: meson: add S4 Soc PLL clock controller in DT Yu Tu
2022-11-23 2:13 ` [PATCH V5 3/4] clk: meson: s4: add s4 SoC peripheral clock controller driver and bindings Yu Tu
2022-11-23 10:09 ` Krzysztof Kozlowski
2022-11-23 11:22 ` Yu Tu
2022-11-23 13:06 ` Krzysztof Kozlowski
2022-11-23 14:08 ` Yu Tu
2022-11-25 9:54 ` Jerome Brunet
2022-11-28 8:08 ` Yu Tu
2022-11-28 12:23 ` Jerome Brunet
2022-11-28 14:02 ` Yu Tu
2022-11-23 2:13 ` [PATCH V5 4/4] arm64: dts: meson: add S4 Soc Peripheral clock controller in DT Yu Tu
2022-11-23 10:10 ` Krzysztof Kozlowski
2022-11-23 11:27 ` Yu Tu
2022-11-23 13:02 ` Krzysztof Kozlowski
2022-11-23 13:23 ` Yu Tu
2022-11-23 14:12 ` Krzysztof Kozlowski
2022-11-23 14:23 ` Yu Tu
2022-11-23 13:27 ` Neil Armstrong
2022-11-23 13:38 ` Yu Tu
2022-11-23 14:13 ` Krzysztof Kozlowski
2022-11-23 14:21 ` neil.armstrong
2022-11-23 14:27 ` Yu Tu
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