Re: [PATCH] arm64: dts: qcom: ipq5018: Add pinctrl for MDIO bus

[Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>]

On 8/11/2026 7:06 PM, Luo Jie wrote:
> The external MDIO bus (mdio1) needs its MDC/MDIO lines configured via
> TLMM pinctrl; without this the pins are left in their default state and
> the bus does not function on boards that enable it.

Should we move the TLMM definitions to the board DTS file rather than 
keeping it in the SoC DTSI?

>
> Add a mdio_pins pinctrl state for gpio36 (mdc) and gpio37 (mdio) with
> 8mA drive strength and pull-up, and reference it from the mdio1 node
> via pinctrl-0/pinctrl-names.
>
> Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
> ---
>   arch/arm64/boot/dts/qcom/ipq5018.dtsi | 18 ++++++++++++++++++
>   1 file changed, 18 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> index 4fc627b47fe7..a8a89a9c8160 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> @@ -241,6 +241,8 @@ mdio1: mdio@90000 {
>   			reg = <0x00090000 0x64>;
>   			#address-cells = <1>;
>   			#size-cells = <0>;
> +			pinctrl-0 = <&mdio_pins>;
> +			pinctrl-names = "default";
>   
>   			clocks = <&gcc GCC_MDIO1_AHB_CLK>;
>   			clock-names = "gcc_mdio_ahb_clk";
> @@ -427,6 +429,22 @@ uart1_pins: uart1-state {
>   				drive-strength = <8>;
>   				bias-pull-down;
>   			};
> +
> +			mdio_pins: mdio-state {
> +				mdc-pins {
> +					pins = "gpio36";
> +					function = "mdc";
> +					drive-strength = <8>;
> +					bias-pull-up;
> +				};
> +
> +				mdio-pins {
> +					pins = "gpio37";
> +					function = "mdio";
> +					drive-strength = <8>;
> +					bias-pull-up;
> +				};
> +			};
>   		};
>   
>   		gcc: clock-controller@1800000 {
>
> ---
> base-commit: 3d08ff75a47a3e7e2ab45a3bcab6723b4d906422
> change-id: 20260811-qcom_ipq5018_mdio_pinctrl-f9e609e97c3d
>
> Best regards,
> --
> Luo Jie <jie.luo@oss.qualcomm.com>
>
>