* [PATCH v2 0/9] Add ITE IT6263 LVDS to HDMI converter support
@ 2024-10-12 7:35 Liu Ying
2024-10-12 7:35 ` [PATCH v2 1/9] arm64: dts: imx8mp-skov-revb-mi1010ait-1cp1: Add panel-timing node to panel node Liu Ying
` (8 more replies)
0 siblings, 9 replies; 49+ messages in thread
From: Liu Ying @ 2024-10-12 7:35 UTC (permalink / raw)
To: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel
Cc: andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
dmitry.baryshkov, arnd, nfraprado, o.rempel, y.moog, marex,
isaac.scott, biju.das.jz
Hi,
This patch series aims to add ITE IT6263 LVDS to HDMI converter on
i.MX8MP EVK. Combined with LVDS receiver and HDMI 1.4a transmitter,
the IT6263 supports LVDS input and HDMI 1.4 output by conversion
function. IT6263 product link can be found at [1].
Patch 1&2 are preparation patches to allow display modes of two
existing panels to pass the added mode validation logic in patch 4.
Patch 3 allows i.MX8MP LVDS Display Bridge(LDB) bridge driver to find
the next non-panel bridge, that is the IT6263 in this case.
Patch 4 adds mode validation logic to i.MX8MP LDB bridge driver against
"ldb" clock so that it can filter out unsupported display modes read
from EDID.
Patch 5 adds DT binding for IT6263.
Patch 6 adds IT6263 bridge driver. Only video output is supported.
Patch 7 adds DT overlays to support NXP adapter cards[2][3] with IT6263
populated.
Patch 8 enables the IT6263 bridge driver in defconfig.
Patch 9 updates MAINTAINERS to add maintainer for IT6263 driver.
[1] https://www.ite.com.tw/en/product/cate1/IT6263
[2] https://www.nxp.com/part/IMX-LVDS-HDMI
[3] https://www.nxp.com/part/IMX-DLVDS-HDMI
v2:
* Add more comments in fsl-ldb.c and commit message about pixel clock
rate validation for patch 4. (Maxime)
* Document number of LVDS link data lanes in patch 5. (Biju)
* Simplify ports property by dropping "oneOf" in patch 5. (Rob)
* Add AVI inforframe support in patch 6. (Maxime)
* Add DRM_MODE_CONNECTOR_HDMIA in patch 6. (Biju)
* Rename it6263_reset() to it6263_hw_reset() in patch 6. (Biju)
* Check number of LVDS link data lanes in patch 6. (Biju)
* Add ite,lvds-link-num-data-lanes properties in patch 7.
* Update MAINTAINERS. (Maxime)
Liu Ying (9):
arm64: dts: imx8mp-skov-revb-mi1010ait-1cp1: Add panel-timing node to
panel node
arm64: dts: imx8mp-phyboard-pollux-rdk: Add panel-timing node to
panel-lvds node
drm/bridge: fsl-ldb: Get the next non-panel bridge
drm/bridge: fsl-ldb: Use clk_round_rate() to validate "ldb" clock rate
dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
drm/bridge: Add ITE IT6263 LVDS to HDMI converter
arm64: dts: imx8mp-evk: Add NXP LVDS to HDMI adapter cards
arm64: defconfig: Enable ITE IT6263 driver
MAINTAINERS: Add maintainer for ITE IT6263 driver
.../bindings/display/bridge/ite,it6263.yaml | 276 ++++++
MAINTAINERS | 8 +
arch/arm64/boot/dts/freescale/Makefile | 8 +
.../imx8mp-evk-imx-lvds-hdmi-common.dtsi | 29 +
...8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso | 44 +
...imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi | 43 +
.../imx8mp-evk-lvds0-imx-lvds-hdmi.dtso | 28 +
...8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso | 44 +
...imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi | 43 +
.../imx8mp-evk-lvds1-imx-lvds-hdmi.dtso | 28 +
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 6 +
.../freescale/imx8mp-phyboard-pollux-rdk.dts | 15 +
.../imx8mp-skov-revb-mi1010ait-1cp1.dts | 15 +
arch/arm64/configs/defconfig | 1 +
drivers/gpu/drm/bridge/Kconfig | 8 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/fsl-ldb.c | 55 +-
drivers/gpu/drm/bridge/ite-it6263.c | 919 ++++++++++++++++++
18 files changed, 1551 insertions(+), 20 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-imx-lvds-hdmi-common.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi.dtso
create mode 100644 drivers/gpu/drm/bridge/ite-it6263.c
--
2.34.1
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 1/9] arm64: dts: imx8mp-skov-revb-mi1010ait-1cp1: Add panel-timing node to panel node
2024-10-12 7:35 [PATCH v2 0/9] Add ITE IT6263 LVDS to HDMI converter support Liu Ying
@ 2024-10-12 7:35 ` Liu Ying
2024-10-12 20:33 ` Marek Vasut
2024-10-12 7:35 ` [PATCH v2 2/9] arm64: dts: imx8mp-phyboard-pollux-rdk: Add panel-timing node to panel-lvds node Liu Ying
` (7 subsequent siblings)
8 siblings, 1 reply; 49+ messages in thread
From: Liu Ying @ 2024-10-12 7:35 UTC (permalink / raw)
To: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel
Cc: andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
dmitry.baryshkov, arnd, nfraprado, o.rempel, y.moog, marex,
isaac.scott, biju.das.jz
Add a panel-timing node to panel node to override any fixed display
modes written in a panel driver. This way, 68.9MHz clock frequency
specified in panel-timing node may accommodate 7-fold 482.3MHz
"media_ldb" clock which is derived from 964.6MHz "video_pll1" clock.
The above clock frequencies align to the clock rates assigned in the
lvds_bridge node and media_blk_ctrl node in this DT file.
This should be able to suppress this LDB driver warning:
[ 17.206644] fsl-ldb 32ec0000.blk-ctrl:bridge@5c: Configured LDB clock (70000000 Hz) does not match requested LVDS clock: 490000000 Hz
This also makes the display mode used by the panel pass mode validation
against pixel clock rate and "media_ldb" clock rate in a certain display
driver.
Fixes: 6d382d51d979 ("arm64: dts: freescale: Add SKOV IMX8MP CPU revB board")
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v2:
* No change.
.../freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts
index 3c2efdc59bfa..4e9f76de7462 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts
@@ -13,6 +13,21 @@ panel {
backlight = <&backlight>;
power-supply = <®_tft_vcom>;
+ panel-timing {
+ clock-frequency = <68900000>;
+ hactive = <1280>;
+ vactive = <800>;
+ hfront-porch = <30>;
+ hback-porch = <30>;
+ hsync-len = <10>;
+ vfront-porch = <5>;
+ vback-porch = <5>;
+ vsync-len = <5>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ };
+
port {
in_lvds0: endpoint {
remote-endpoint = <&ldb_lvds_ch0>;
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 2/9] arm64: dts: imx8mp-phyboard-pollux-rdk: Add panel-timing node to panel-lvds node
2024-10-12 7:35 [PATCH v2 0/9] Add ITE IT6263 LVDS to HDMI converter support Liu Ying
2024-10-12 7:35 ` [PATCH v2 1/9] arm64: dts: imx8mp-skov-revb-mi1010ait-1cp1: Add panel-timing node to panel node Liu Ying
@ 2024-10-12 7:35 ` Liu Ying
2024-10-12 20:34 ` Marek Vasut
2024-10-12 7:35 ` [PATCH v2 3/9] drm/bridge: fsl-ldb: Get the next non-panel bridge Liu Ying
` (6 subsequent siblings)
8 siblings, 1 reply; 49+ messages in thread
From: Liu Ying @ 2024-10-12 7:35 UTC (permalink / raw)
To: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel
Cc: andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
dmitry.baryshkov, arnd, nfraprado, o.rempel, y.moog, marex,
isaac.scott, biju.das.jz
Add a panel-timing node to panel-lvds node to override any fixed
display modes written in a panel driver. This way, 74.25MHz clock
frequency specified in panel-timing node may accommodate 7-fold
519.75MHz "media_ldb" clock which is derived from 1.0395GHz
"video_pll1" clock.
This should suppress this LDB driver warning:
[ 17.923709] fsl-ldb 32ec0000.blk-ctrl:bridge@5c: Configured LDB clock (72400000 Hz) does not match requested LVDS clock: 506800000 Hz
This also makes the display mode used by the panel pass mode validation
against pixel clock rate and "media_ldb" clock rate in a certain display
driver.
Fixes: 326d86e197fc ("arm64: dts: imx8mp-phyboard-pollux-rdk: add etml panel support")
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v2:
* No change.
.../dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
index 50debe821c42..20cb5363cccb 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
@@ -37,6 +37,21 @@ panel1_lvds: panel-lvds {
backlight = <&backlight_lvds>;
power-supply = <®_vcc_3v3_sw>;
+ panel-timing {
+ clock-frequency = <74250000>;
+ hactive = <1280>;
+ vactive = <800>;
+ hfront-porch = <72>;
+ hback-porch = <86>;
+ hsync-len = <2>;
+ vfront-porch = <15>;
+ vback-porch = <21>;
+ vsync-len = <2>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ };
+
port {
panel1_in: endpoint {
remote-endpoint = <&ldb_lvds_ch1>;
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 3/9] drm/bridge: fsl-ldb: Get the next non-panel bridge
2024-10-12 7:35 [PATCH v2 0/9] Add ITE IT6263 LVDS to HDMI converter support Liu Ying
2024-10-12 7:35 ` [PATCH v2 1/9] arm64: dts: imx8mp-skov-revb-mi1010ait-1cp1: Add panel-timing node to panel node Liu Ying
2024-10-12 7:35 ` [PATCH v2 2/9] arm64: dts: imx8mp-phyboard-pollux-rdk: Add panel-timing node to panel-lvds node Liu Ying
@ 2024-10-12 7:35 ` Liu Ying
2024-10-12 8:48 ` Dmitry Baryshkov
2024-10-12 7:35 ` [PATCH v2 4/9] drm/bridge: fsl-ldb: Use clk_round_rate() to validate "ldb" clock rate Liu Ying
` (5 subsequent siblings)
8 siblings, 1 reply; 49+ messages in thread
From: Liu Ying @ 2024-10-12 7:35 UTC (permalink / raw)
To: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel
Cc: andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
dmitry.baryshkov, arnd, nfraprado, o.rempel, y.moog, marex,
isaac.scott, biju.das.jz
The next bridge in bridge chain could be a panel bridge or a non-panel
bridge. Use devm_drm_of_get_bridge() to replace the combination
function calls of of_drm_find_panel() and devm_drm_panel_bridge_add()
to get either a panel bridge or a non-panel bridge, instead of getting
a panel bridge only.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v2:
* No change.
drivers/gpu/drm/bridge/fsl-ldb.c | 31 +++++++++++--------------------
1 file changed, 11 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c
index 0e4bac7dd04f..b559f3e0bef6 100644
--- a/drivers/gpu/drm/bridge/fsl-ldb.c
+++ b/drivers/gpu/drm/bridge/fsl-ldb.c
@@ -15,7 +15,6 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_bridge.h>
#include <drm/drm_of.h>
-#include <drm/drm_panel.h>
#define LDB_CTRL_CH0_ENABLE BIT(0)
#define LDB_CTRL_CH0_DI_SELECT BIT(1)
@@ -86,7 +85,7 @@ static const struct fsl_ldb_devdata fsl_ldb_devdata[] = {
struct fsl_ldb {
struct device *dev;
struct drm_bridge bridge;
- struct drm_bridge *panel_bridge;
+ struct drm_bridge *next_bridge;
struct clk *clk;
struct regmap *regmap;
const struct fsl_ldb_devdata *devdata;
@@ -117,7 +116,7 @@ static int fsl_ldb_attach(struct drm_bridge *bridge,
{
struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
- return drm_bridge_attach(bridge->encoder, fsl_ldb->panel_bridge,
+ return drm_bridge_attach(bridge->encoder, fsl_ldb->next_bridge,
bridge, flags);
}
@@ -292,9 +291,7 @@ static const struct drm_bridge_funcs funcs = {
static int fsl_ldb_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
- struct device_node *panel_node;
struct device_node *remote1, *remote2;
- struct drm_panel *panel;
struct fsl_ldb *fsl_ldb;
int dual_link;
@@ -318,33 +315,27 @@ static int fsl_ldb_probe(struct platform_device *pdev)
if (IS_ERR(fsl_ldb->regmap))
return PTR_ERR(fsl_ldb->regmap);
- /* Locate the remote ports and the panel node */
+ /* Locate the remote ports. */
remote1 = of_graph_get_remote_node(dev->of_node, 1, 0);
remote2 = of_graph_get_remote_node(dev->of_node, 2, 0);
fsl_ldb->ch0_enabled = (remote1 != NULL);
fsl_ldb->ch1_enabled = (remote2 != NULL);
- panel_node = of_node_get(remote1 ? remote1 : remote2);
of_node_put(remote1);
of_node_put(remote2);
- if (!fsl_ldb->ch0_enabled && !fsl_ldb->ch1_enabled) {
- of_node_put(panel_node);
- return dev_err_probe(dev, -ENXIO, "No panel node found");
- }
+ if (!fsl_ldb->ch0_enabled && !fsl_ldb->ch1_enabled)
+ return dev_err_probe(dev, -ENXIO, "No next bridge node found");
dev_dbg(dev, "Using %s\n",
fsl_ldb_is_dual(fsl_ldb) ? "dual-link mode" :
fsl_ldb->ch0_enabled ? "channel 0" : "channel 1");
- panel = of_drm_find_panel(panel_node);
- of_node_put(panel_node);
- if (IS_ERR(panel))
- return PTR_ERR(panel);
-
- fsl_ldb->panel_bridge = devm_drm_panel_bridge_add(dev, panel);
- if (IS_ERR(fsl_ldb->panel_bridge))
- return PTR_ERR(fsl_ldb->panel_bridge);
-
+ fsl_ldb->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node,
+ fsl_ldb->ch0_enabled ? 1 : 2,
+ 0);
+ if (IS_ERR(fsl_ldb->next_bridge))
+ return dev_err_probe(dev, PTR_ERR(fsl_ldb->next_bridge),
+ "failed to get next bridge\n");
if (fsl_ldb_is_dual(fsl_ldb)) {
struct device_node *port1, *port2;
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 4/9] drm/bridge: fsl-ldb: Use clk_round_rate() to validate "ldb" clock rate
2024-10-12 7:35 [PATCH v2 0/9] Add ITE IT6263 LVDS to HDMI converter support Liu Ying
` (2 preceding siblings ...)
2024-10-12 7:35 ` [PATCH v2 3/9] drm/bridge: fsl-ldb: Get the next non-panel bridge Liu Ying
@ 2024-10-12 7:35 ` Liu Ying
2024-10-12 7:35 ` [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter Liu Ying
` (4 subsequent siblings)
8 siblings, 0 replies; 49+ messages in thread
From: Liu Ying @ 2024-10-12 7:35 UTC (permalink / raw)
To: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel
Cc: andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
dmitry.baryshkov, arnd, nfraprado, o.rempel, y.moog, marex,
isaac.scott, biju.das.jz
Multiple display modes could be read from a display device's EDID.
Use clk_round_rate() to validate the "ldb" clock rate for each mode
in drm_bridge_funcs::mode_valid() to filter unsupported modes out.
Also, since this driver doesn't directly reference pixel clock, use
clk_round_rate() to validate the pixel clock rate against the "ldb"
clock if the "ldb" clock and the pixel clock are sibling in clock
tree. This is not done in display controller driver because
drm_crtc_helper_funcs::mode_valid() may not decide to do the
validation or not if multiple encoders are connected to the CRTC,
e.g., i.MX93 LCDIF may connect with MIPI DSI controller, LDB and
parallel display output simultaneously.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v2:
* Add more comments in fsl-ldb.c and commit message about pixel clock
rate validation. (Maxime)
drivers/gpu/drm/bridge/fsl-ldb.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c
index b559f3e0bef6..77afc169f0d3 100644
--- a/drivers/gpu/drm/bridge/fsl-ldb.c
+++ b/drivers/gpu/drm/bridge/fsl-ldb.c
@@ -11,6 +11,7 @@
#include <linux/of_graph.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include <linux/units.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_bridge.h>
@@ -64,6 +65,7 @@ struct fsl_ldb_devdata {
u32 lvds_ctrl;
bool lvds_en_bit;
bool single_ctrl_reg;
+ bool ldb_clk_pixel_clk_sibling;
};
static const struct fsl_ldb_devdata fsl_ldb_devdata[] = {
@@ -74,11 +76,13 @@ static const struct fsl_ldb_devdata fsl_ldb_devdata[] = {
[IMX8MP_LDB] = {
.ldb_ctrl = 0x5c,
.lvds_ctrl = 0x128,
+ .ldb_clk_pixel_clk_sibling = true,
},
[IMX93_LDB] = {
.ldb_ctrl = 0x20,
.lvds_ctrl = 0x24,
.lvds_en_bit = true,
+ .ldb_clk_pixel_clk_sibling = true,
},
};
@@ -269,11 +273,31 @@ fsl_ldb_mode_valid(struct drm_bridge *bridge,
const struct drm_display_info *info,
const struct drm_display_mode *mode)
{
+ unsigned long link_freq, pclk_rate, rounded_pclk_rate;
struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
if (mode->clock > (fsl_ldb_is_dual(fsl_ldb) ? 160000 : 80000))
return MODE_CLOCK_HIGH;
+ /* Validate "ldb" clock rate. */
+ link_freq = fsl_ldb_link_frequency(fsl_ldb, mode->clock);
+ if (link_freq != clk_round_rate(fsl_ldb->clk, link_freq))
+ return MODE_NOCLOCK;
+
+ /*
+ * Since this driver doesn't directly reference pixel clock and
+ * display controller driver cannot validate pixel clock due to
+ * multiple types of encoders connected, use "ldb" clock to
+ * validate pixel clock rate, if the two clocks are sibling.
+ */
+ if (fsl_ldb->devdata->ldb_clk_pixel_clk_sibling) {
+ pclk_rate = mode->clock * HZ_PER_KHZ;
+
+ rounded_pclk_rate = clk_round_rate(fsl_ldb->clk, pclk_rate);
+ if (rounded_pclk_rate != pclk_rate)
+ return MODE_NOCLOCK;
+ }
+
return MODE_OK;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-12 7:35 [PATCH v2 0/9] Add ITE IT6263 LVDS to HDMI converter support Liu Ying
` (3 preceding siblings ...)
2024-10-12 7:35 ` [PATCH v2 4/9] drm/bridge: fsl-ldb: Use clk_round_rate() to validate "ldb" clock rate Liu Ying
@ 2024-10-12 7:35 ` Liu Ying
2024-10-12 8:30 ` Dmitry Baryshkov
2024-10-12 7:35 ` [PATCH v2 6/9] drm/bridge: " Liu Ying
` (3 subsequent siblings)
8 siblings, 1 reply; 49+ messages in thread
From: Liu Ying @ 2024-10-12 7:35 UTC (permalink / raw)
To: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel
Cc: andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
dmitry.baryshkov, arnd, nfraprado, o.rempel, y.moog, marex,
isaac.scott, biju.das.jz
Document ITE IT6263 LVDS to HDMI converter.
Product link:
https://www.ite.com.tw/en/product/cate1/IT6263
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v2:
* Document number of LVDS link data lanes. (Biju)
* Simplify ports property by dropping "oneOf". (Rob)
.../bindings/display/bridge/ite,it6263.yaml | 276 ++++++++++++++++++
1 file changed, 276 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
new file mode 100644
index 000000000000..bc2bbec07623
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
@@ -0,0 +1,276 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/ite,it6263.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ITE IT6263 LVDS to HDMI converter
+
+maintainers:
+ - Liu Ying <victor.liu@nxp.com>
+
+description: |
+ The IT6263 is a high-performance single-chip De-SSC(De-Spread Spectrum) LVDS
+ to HDMI converter. Combined with LVDS receiver and HDMI 1.4a transmitter,
+ the IT6263 supports LVDS input and HDMI 1.4 output by conversion function.
+ The built-in LVDS receiver can support single-link and dual-link LVDS inputs,
+ and the built-in HDMI transmitter is fully compliant with HDMI 1.4a/3D, HDCP
+ 1.2 and backward compatible with DVI 1.0 specification.
+
+ The IT6263 also encodes and transmits up to 8 channels of I2S digital audio,
+ with sampling rate up to 192KHz and sample size up to 24 bits. In addition,
+ an S/PDIF input port takes in compressed audio of up to 192KHz frame rate.
+
+ The newly supported High-Bit Rate(HBR) audio by HDMI specifications v1.3 is
+ provided by the IT6263 in two interfaces: the four I2S input ports or the
+ S/PDIF input port. With both interfaces the highest possible HBR frame rate
+ is supported at up to 768KHz.
+
+properties:
+ compatible:
+ const: ite,it6263
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+ description: audio master clock
+
+ clock-names:
+ const: mclk
+
+ reset-gpios:
+ maxItems: 1
+
+ ivdd-supply:
+ description: 1.8V digital logic power
+
+ ovdd-supply:
+ description: 3.3V I/O pin power
+
+ txavcc18-supply:
+ description: 1.8V HDMI analog frontend power
+
+ txavcc33-supply:
+ description: 3.3V HDMI analog frontend power
+
+ pvcc1-supply:
+ description: 1.8V HDMI frontend core PLL power
+
+ pvcc2-supply:
+ description: 1.8V HDMI frontend filter PLL power
+
+ avcc-supply:
+ description: 3.3V LVDS frontend power
+
+ anvdd-supply:
+ description: 1.8V LVDS frontend analog power
+
+ apvdd-supply:
+ description: 1.8V LVDS frontend PLL power
+
+ "#sound-dai-cells":
+ const: 0
+
+ ite,lvds-link-num-data-lanes:
+ $ref: /schemas/types.yaml#/definitions/uint8
+ enum: [3, 4, 5]
+ description: number of data lanes per LVDS link
+
+ ite,i2s-audio-fifo-sources:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 4
+ items:
+ enum: [0, 1, 2, 3]
+ description:
+ Each array element indicates the pin number of an I2S serial data input
+ line which is connected to an audio FIFO, from audio FIFO0 to FIFO3.
+
+ ite,rl-channel-swap-audio-sources:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 4
+ uniqueItems: true
+ items:
+ enum: [0, 1, 2, 3]
+ description:
+ Each array element indicates an audio source whose right channel and left
+ channel are swapped by this converter. For I2S, the element is the pin
+ number of an I2S serial data input line. For S/PDIF, the element is always
+ 0.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ The first LVDS input link.
+ In dual-link LVDS mode, this link works together with the second LVDS
+ input link, and one link receives odd pixels while the other receives
+ even pixels. Specify the pixels with one of the dual-lvds-odd-pixels
+ and dual-lvds-even-pixels properties when and only when dual-link LVDS
+ mode is used.
+
+ properties:
+ dual-lvds-odd-pixels:
+ type: boolean
+ description: the first sink port for odd pixels
+
+ dual-lvds-even-pixels:
+ type: boolean
+ description: the first sink port for even pixels
+
+ port@1:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: the second LVDS input link
+
+ properties:
+ dual-lvds-even-pixels:
+ type: boolean
+ description: the second sink port for even pixels
+
+ dual-lvds-odd-pixels:
+ type: boolean
+ description: the second sink port for odd pixels
+
+ oneOf:
+ - required: [dual-lvds-even-pixels]
+ - required: [dual-lvds-odd-pixels]
+
+ port@2:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: video port for the HDMI output
+
+ port@3:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: sound input port
+
+ required:
+ - port@0
+ - port@2
+
+required:
+ - compatible
+ - reg
+ - ivdd-supply
+ - ovdd-supply
+ - txavcc18-supply
+ - txavcc33-supply
+ - pvcc1-supply
+ - pvcc2-supply
+ - avcc-supply
+ - anvdd-supply
+ - apvdd-supply
+ - ite,lvds-link-num-data-lanes
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ /* single-link LVDS input */
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi@4c {
+ compatible = "ite,it6263";
+ reg = <0x4c>;
+ reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ ivdd-supply = <®_buck5>;
+ ovdd-supply = <®_vext_3v3>;
+ txavcc18-supply = <®_buck5>;
+ txavcc33-supply = <®_vext_3v3>;
+ pvcc1-supply = <®_buck5>;
+ pvcc2-supply = <®_buck5>;
+ avcc-supply = <®_vext_3v3>;
+ anvdd-supply = <®_buck5>;
+ apvdd-supply = <®_buck5>;
+ ite,lvds-link-num-data-lanes = /bits/ 8 <4>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ it6263_lvds_link1: endpoint {
+ remote-endpoint = <&ldb_lvds_ch0>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ it6263_out: endpoint {
+ remote-endpoint = <&hdmi_in>;
+ };
+ };
+ };
+ };
+ };
+
+ - |
+ /* dual-link LVDS input */
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi@4c {
+ compatible = "ite,it6263";
+ reg = <0x4c>;
+ reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ ivdd-supply = <®_buck5>;
+ ovdd-supply = <®_vext_3v3>;
+ txavcc18-supply = <®_buck5>;
+ txavcc33-supply = <®_vext_3v3>;
+ pvcc1-supply = <®_buck5>;
+ pvcc2-supply = <®_buck5>;
+ avcc-supply = <®_vext_3v3>;
+ anvdd-supply = <®_buck5>;
+ apvdd-supply = <®_buck5>;
+ ite,lvds-link-num-data-lanes = /bits/ 8 <4>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dual-lvds-odd-pixels;
+
+ it6263_lvds_link1_dual: endpoint {
+ remote-endpoint = <&ldb_lvds_ch0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dual-lvds-even-pixels;
+
+ it6263_lvds_link2_dual: endpoint {
+ remote-endpoint = <&ldb_lvds_ch1>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ it6263_out_dual: endpoint {
+ remote-endpoint = <&hdmi_in>;
+ };
+ };
+ };
+ };
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-12 7:35 [PATCH v2 0/9] Add ITE IT6263 LVDS to HDMI converter support Liu Ying
` (4 preceding siblings ...)
2024-10-12 7:35 ` [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter Liu Ying
@ 2024-10-12 7:35 ` Liu Ying
2024-10-12 8:45 ` Dmitry Baryshkov
` (2 more replies)
2024-10-12 7:35 ` [PATCH v2 7/9] arm64: dts: imx8mp-evk: Add NXP LVDS to HDMI adapter cards Liu Ying
` (2 subsequent siblings)
8 siblings, 3 replies; 49+ messages in thread
From: Liu Ying @ 2024-10-12 7:35 UTC (permalink / raw)
To: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel
Cc: andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
dmitry.baryshkov, arnd, nfraprado, o.rempel, y.moog, marex,
isaac.scott, biju.das.jz
Add basic HDMI video output support. Currently, only RGB888 output
pixel format is supported. At the LVDS input side, the driver
supports single LVDS link and dual LVDS links with "jeida-24" LVDS
mapping.
Product link:
https://www.ite.com.tw/en/product/cate1/IT6263
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v2:
* Add AVI inforframe support. (Maxime)
* Add DRM_MODE_CONNECTOR_HDMIA. (Biju)
* Rename it6263_reset() to it6263_hw_reset(). (Biju)
* Check number of LVDS link data lanes. (Biju)
drivers/gpu/drm/bridge/Kconfig | 8 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/ite-it6263.c | 919 ++++++++++++++++++++++++++++
3 files changed, 928 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/ite-it6263.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 3eb955333c80..93f99682a090 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -90,6 +90,14 @@ config DRM_FSL_LDB
help
Support for i.MX8MP DPI-to-LVDS on-SoC encoder.
+config DRM_ITE_IT6263
+ tristate "ITE IT6263 LVDS/HDMI bridge"
+ depends on OF
+ select DRM_KMS_HELPER
+ select REGMAP_I2C
+ help
+ ITE IT6263 LVDS to HDMI bridge chip driver.
+
config DRM_ITE_IT6505
tristate "ITE IT6505 DisplayPort bridge"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 7df87b582dca..f3776dd473fd 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
obj-$(CONFIG_DRM_CROS_EC_ANX7688) += cros-ec-anx7688.o
obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
obj-$(CONFIG_DRM_FSL_LDB) += fsl-ldb.o
+obj-$(CONFIG_DRM_ITE_IT6263) += ite-it6263.o
obj-$(CONFIG_DRM_ITE_IT6505) += ite-it6505.o
obj-$(CONFIG_DRM_LONTIUM_LT8912B) += lontium-lt8912b.o
obj-$(CONFIG_DRM_LONTIUM_LT9211) += lontium-lt9211.o
diff --git a/drivers/gpu/drm/bridge/ite-it6263.c b/drivers/gpu/drm/bridge/ite-it6263.c
new file mode 100644
index 000000000000..9b3318792f15
--- /dev/null
+++ b/drivers/gpu/drm/bridge/ite-it6263.c
@@ -0,0 +1,919 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/hdmi.h>
+#include <linux/i2c.h>
+#include <linux/media-bus-format.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_atomic_state_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_connector.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_edid.h>
+#include <drm/drm_of.h>
+#include <drm/drm_probe_helper.h>
+
+/* -----------------------------------------------------------------------------
+ * LVDS registers
+ */
+
+/* LVDS software reset registers */
+#define LVDS_REG_05 0x05
+#define REG_SOFT_P_RST BIT(1)
+
+/* LVDS system configuration registers */
+/* 0x0b */
+#define LVDS_REG_0B 0x0b
+#define REG_SSC_PCLK_RF BIT(0)
+#define REG_LVDS_IN_SWAP BIT(1)
+
+/* LVDS test pattern gen control registers */
+/* 0x2c */
+#define LVDS_REG_2C 0x2c
+#define REG_COL_DEP GENMASK(1, 0)
+#define BIT8 FIELD_PREP(REG_COL_DEP, 2)
+#define OUT_MAP BIT(4)
+#define JEIDA 0
+#define REG_DESSC_ENB BIT(6)
+#define DMODE BIT(7)
+#define DISO BIT(7)
+#define SISO 0
+
+#define LVDS_REG_3C 0x3c
+#define LVDS_REG_3F 0x3f
+#define LVDS_REG_47 0x47
+#define LVDS_REG_48 0x48
+#define LVDS_REG_4F 0x4f
+#define LVDS_REG_52 0x52
+
+/* -----------------------------------------------------------------------------
+ * HDMI registers are separated into three banks:
+ * 1) HDMI register common bank: 0x00 ~ 0x2f
+ */
+
+/* HDMI genernal registers */
+#define HDMI_REG_SW_RST 0x04
+#define SOFTREF_RST BIT(5)
+#define SOFTA_RST BIT(4)
+#define SOFTV_RST BIT(3)
+#define AUD_RST BIT(2)
+#define HDCP_RST BIT(0)
+#define HDMI_RST_ALL (SOFTREF_RST | SOFTA_RST | SOFTV_RST | \
+ AUD_RST | HDCP_RST)
+
+#define HDMI_REG_SYS_STATUS 0x0e
+#define HPDETECT BIT(6)
+#define TXVIDSTABLE BIT(4)
+
+#define HDMI_REG_BANK_CTRL 0x0f
+#define REG_BANK_SEL BIT(0)
+
+/* HDMI System DDC control registers */
+#define HDMI_REG_DDC_MASTER_CTRL 0x10
+#define MASTER_SEL_HOST BIT(0)
+
+#define HDMI_REG_DDC_HEADER 0x11
+
+#define HDMI_REG_DDC_REQOFF 0x12
+#define HDMI_REG_DDC_REQCOUNT 0x13
+#define HDMI_REG_DDC_EDIDSEG 0x14
+
+#define HDMI_REG_DDC_CMD 0x15
+#define DDC_CMD_EDID_READ 0x3
+#define DDC_CMD_FIFO_CLR 0x9
+
+#define HDMI_REG_DDC_STATUS 0x16
+#define DDC_DONE BIT(7)
+#define DDC_NOACK BIT(5)
+#define DDC_WAITBUS BIT(4)
+#define DDC_ARBILOSE BIT(3)
+#define DDC_ERROR (DDC_NOACK | DDC_WAITBUS | DDC_ARBILOSE)
+
+#define HDMI_DDC_FIFO_BYTES 32
+#define HDMI_REG_DDC_READFIFO 0x17
+#define HDMI_REG_LVDS_PORT 0x1d /* LVDS input control I2C addr */
+#define HDMI_REG_LVDS_PORT_EN 0x1e
+#define LVDS_INPUT_CTRL_I2C_ADDR 0x33
+
+/* -----------------------------------------------------------------------------
+ * 2) HDMI register bank0: 0x30 ~ 0xff
+ */
+
+/* HDMI AFE registers */
+#define HDMI_REG_AFE_DRV_CTRL 0x61
+#define AFE_DRV_PWD BIT(5)
+#define AFE_DRV_RST BIT(4)
+
+#define HDMI_REG_AFE_XP_CTRL 0x62
+#define AFE_XP_GAINBIT BIT(7)
+#define AFE_XP_ER0 BIT(4)
+#define AFE_XP_RESETB BIT(3)
+
+#define HDMI_REG_AFE_ISW_CTRL 0x63
+
+#define HDMI_REG_AFE_IP_CTRL 0x64
+#define AFE_IP_GAINBIT BIT(7)
+#define AFE_IP_ER0 BIT(3)
+#define AFE_IP_RESETB BIT(2)
+
+/* HDMI input data format registers */
+#define HDMI_REG_INPUT_MODE 0x70
+#define IN_RGB 0x00
+
+/* HDMI general control registers */
+#define HDMI_REG_HDMI_MODE 0xc0
+#define TX_HDMI_MODE BIT(0)
+
+#define HDMI_REG_GCP 0xc1
+#define AVMUTE BIT(0)
+#define HDMI_COLOR_DEPTH GENMASK(6, 4)
+#define HDMI_COLOR_DEPTH_24 FIELD_PREP(HDMI_COLOR_DEPTH, 4)
+
+#define HDMI_REG_PKT_GENERAL_CTRL 0xc6
+#define ENABLE_PKT BIT(0)
+#define REPEAT_PKT BIT(1)
+
+/* -----------------------------------------------------------------------------
+ * 3) HDMI register bank1: 0x130 ~ 0x1ff (HDMI packet registers)
+ */
+
+/* AVI packet registers */
+#define HDMI_REG_AVI_DB1 0x158
+#define HDMI_REG_AVI_DB2 0x159
+#define HDMI_REG_AVI_DB3 0x15a
+#define HDMI_REG_AVI_DB4 0x15b
+#define HDMI_REG_AVI_DB5 0x15c
+#define HDMI_REG_AVI_CSUM 0x15d
+#define HDMI_REG_AVI_DB6 0x15e
+#define HDMI_REG_AVI_DB7 0x15f
+#define HDMI_REG_AVI_DB8 0x160
+#define HDMI_REG_AVI_DB9 0x161
+#define HDMI_REG_AVI_DB10 0x162
+#define HDMI_REG_AVI_DB11 0x163
+#define HDMI_REG_AVI_DB12 0x164
+#define HDMI_REG_AVI_DB13 0x165
+
+#define HDMI_AVI_DB_CHUNK1_SIZE (HDMI_REG_AVI_DB5 - HDMI_REG_AVI_DB1 + 1)
+#define HDMI_AVI_DB_CHUNK2_SIZE (HDMI_REG_AVI_DB13 - HDMI_REG_AVI_DB6 + 1)
+
+#define MAX_PIXEL_CLOCK_KHZ 150000
+#define HIGH_PIXEL_CLOCK_KHZ 80000
+
+struct it6263 {
+ struct device *dev;
+ struct i2c_client *hdmi_i2c;
+ struct i2c_client *lvds_i2c;
+ struct regmap *hdmi_regmap;
+ struct regmap *lvds_regmap;
+ struct drm_bridge bridge;
+ struct drm_bridge *next_bridge;
+ struct drm_connector connector;
+ struct gpio_desc *reset_gpio;
+ u8 lvds_link_num_dlanes;
+ bool lvds_dual_link;
+ bool lvds_link12_swap;
+};
+
+static inline struct it6263 *bridge_to_it6263(struct drm_bridge *bridge)
+{
+ return container_of(bridge, struct it6263, bridge);
+}
+
+static inline struct it6263 *connector_to_it6263(struct drm_connector *conn)
+{
+ return container_of(conn, struct it6263, connector);
+}
+
+static bool it6263_hdmi_writeable_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case HDMI_REG_SW_RST:
+ case HDMI_REG_BANK_CTRL:
+ case HDMI_REG_DDC_MASTER_CTRL:
+ case HDMI_REG_DDC_HEADER:
+ case HDMI_REG_DDC_REQOFF:
+ case HDMI_REG_DDC_REQCOUNT:
+ case HDMI_REG_DDC_EDIDSEG:
+ case HDMI_REG_DDC_CMD:
+ case HDMI_REG_LVDS_PORT:
+ case HDMI_REG_LVDS_PORT_EN:
+ case HDMI_REG_AFE_DRV_CTRL:
+ case HDMI_REG_AFE_XP_CTRL:
+ case HDMI_REG_AFE_ISW_CTRL:
+ case HDMI_REG_AFE_IP_CTRL:
+ case HDMI_REG_INPUT_MODE:
+ case HDMI_REG_HDMI_MODE:
+ case HDMI_REG_GCP:
+ case HDMI_REG_PKT_GENERAL_CTRL:
+ case HDMI_REG_AVI_DB1:
+ case HDMI_REG_AVI_DB2:
+ case HDMI_REG_AVI_DB3:
+ case HDMI_REG_AVI_DB4:
+ case HDMI_REG_AVI_DB5:
+ case HDMI_REG_AVI_CSUM:
+ case HDMI_REG_AVI_DB6:
+ case HDMI_REG_AVI_DB7:
+ case HDMI_REG_AVI_DB8:
+ case HDMI_REG_AVI_DB9:
+ case HDMI_REG_AVI_DB10:
+ case HDMI_REG_AVI_DB11:
+ case HDMI_REG_AVI_DB12:
+ case HDMI_REG_AVI_DB13:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool it6263_hdmi_readable_reg(struct device *dev, unsigned int reg)
+{
+ if (it6263_hdmi_writeable_reg(dev, reg))
+ return true;
+
+ switch (reg) {
+ case HDMI_REG_SYS_STATUS:
+ case HDMI_REG_DDC_STATUS:
+ case HDMI_REG_DDC_READFIFO:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool it6263_hdmi_volatile_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case HDMI_REG_SW_RST:
+ case HDMI_REG_SYS_STATUS:
+ case HDMI_REG_DDC_STATUS:
+ case HDMI_REG_DDC_READFIFO:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static const struct regmap_range_cfg it6263_hdmi_range_cfg = {
+ .range_min = 0x00,
+ .range_max = HDMI_REG_AVI_DB13,
+ .selector_reg = HDMI_REG_BANK_CTRL,
+ .selector_mask = REG_BANK_SEL,
+ .selector_shift = 0,
+ .window_start = 0x00,
+ .window_len = 0x100,
+};
+
+static const struct regmap_config it6263_hdmi_regmap_config = {
+ .name = "it6263-hdmi",
+ .reg_bits = 8,
+ .val_bits = 8,
+ .writeable_reg = it6263_hdmi_writeable_reg,
+ .readable_reg = it6263_hdmi_readable_reg,
+ .volatile_reg = it6263_hdmi_volatile_reg,
+ .max_register = HDMI_REG_AVI_DB13,
+ .ranges = &it6263_hdmi_range_cfg,
+ .num_ranges = 1,
+ .cache_type = REGCACHE_MAPLE,
+};
+
+static bool it6263_lvds_writeable_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case LVDS_REG_05:
+ case LVDS_REG_0B:
+ case LVDS_REG_2C:
+ case LVDS_REG_3C:
+ case LVDS_REG_3F:
+ case LVDS_REG_47:
+ case LVDS_REG_48:
+ case LVDS_REG_4F:
+ case LVDS_REG_52:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool it6263_lvds_readable_reg(struct device *dev, unsigned int reg)
+{
+ return it6263_lvds_writeable_reg(dev, reg);
+}
+
+static bool it6263_lvds_volatile_reg(struct device *dev, unsigned int reg)
+{
+ return reg == LVDS_REG_05;
+}
+
+static const struct regmap_config it6263_lvds_regmap_config = {
+ .name = "it6263-lvds",
+ .reg_bits = 8,
+ .val_bits = 8,
+ .writeable_reg = it6263_lvds_writeable_reg,
+ .readable_reg = it6263_lvds_readable_reg,
+ .volatile_reg = it6263_lvds_volatile_reg,
+ .max_register = LVDS_REG_52,
+ .cache_type = REGCACHE_MAPLE,
+};
+
+static const char * const it6263_supplies[] = {
+ "ivdd", "ovdd", "txavcc18", "txavcc33", "pvcc1", "pvcc2",
+ "avcc", "anvdd", "apvdd"
+};
+
+static int it6263_parse_dt(struct it6263 *it)
+{
+ struct device *dev = it->dev;
+ struct device_node *port0, *port1;
+ int ret;
+
+ ret = of_property_read_u8(dev->of_node, "ite,lvds-link-num-data-lanes",
+ &it->lvds_link_num_dlanes);
+ if (ret) {
+ dev_err(dev, "failed to get LVDS link number of data lanes: %d\n",
+ ret);
+ return ret;
+ }
+
+ it->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0);
+ if (IS_ERR(it->next_bridge))
+ return dev_err_probe(dev, PTR_ERR(it->next_bridge),
+ "failed to get next bridge\n");
+
+ port0 = of_graph_get_port_by_id(dev->of_node, 0);
+ port1 = of_graph_get_port_by_id(dev->of_node, 1);
+ if (port0 && port1) {
+ if (of_property_read_bool(port0, "dual-lvds-even-pixels") &&
+ of_property_read_bool(port1, "dual-lvds-odd-pixels")) {
+ it->lvds_dual_link = true;
+ it->lvds_link12_swap = true;
+ } else if (of_property_read_bool(port0, "dual-lvds-odd-pixels") &&
+ of_property_read_bool(port1, "dual-lvds-even-pixels")) {
+ it->lvds_dual_link = true;
+ }
+
+ if (!it->lvds_dual_link) {
+ dev_err(dev,
+ "failed to get LVDS dual link pixel order\n");
+ ret = -EINVAL;
+ }
+ } else if (port1) {
+ ret = -EINVAL;
+ dev_err(dev, "single input LVDS port1 is not supported\n");
+ } else if (!port0) {
+ ret = -EINVAL;
+ dev_err(dev, "no input LVDS port\n");
+ }
+
+ of_node_put(port0);
+ of_node_put(port1);
+
+ return ret;
+}
+
+static inline void it6263_hw_reset(struct it6263 *it)
+{
+ if (!it->reset_gpio)
+ return;
+
+ gpiod_set_value_cansleep(it->reset_gpio, 0);
+ fsleep(1000);
+ gpiod_set_value_cansleep(it->reset_gpio, 1);
+ /* The chip maker says the low pulse should be at least 40ms. */
+ fsleep(40000);
+ gpiod_set_value_cansleep(it->reset_gpio, 0);
+ /* addtional time to wait the high voltage to be stable */
+ fsleep(5000);
+}
+
+static inline int it6263_lvds_set_i2c_addr(struct it6263 *it)
+{
+ int ret;
+
+ ret = regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT,
+ LVDS_INPUT_CTRL_I2C_ADDR << 1);
+ if (ret)
+ return ret;
+
+ return regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT_EN, BIT(0));
+}
+
+static inline void it6263_lvds_reset(struct it6263 *it)
+{
+ /* AFE PLL reset */
+ regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), 0x0);
+ fsleep(1000);
+ regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), BIT(0));
+
+ /* software pixel clock domain reset */
+ regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST,
+ REG_SOFT_P_RST);
+ fsleep(1000);
+ regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST, 0x0);
+ fsleep(10000);
+}
+
+static inline void it6263_lvds_set_interface(struct it6263 *it)
+{
+ /* color depth */
+ regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_COL_DEP, BIT8);
+ /* output mapping */
+ regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, OUT_MAP, JEIDA);
+
+ if (it->lvds_dual_link) {
+ regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, DISO);
+ regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), BIT(1));
+ } else {
+ regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, SISO);
+ regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), 0);
+ }
+}
+
+static inline void it6263_lvds_set_afe(struct it6263 *it)
+{
+ regmap_write(it->lvds_regmap, LVDS_REG_3C, 0xaa);
+ regmap_write(it->lvds_regmap, LVDS_REG_3F, 0x02);
+ regmap_write(it->lvds_regmap, LVDS_REG_47, 0xaa);
+ regmap_write(it->lvds_regmap, LVDS_REG_48, 0x02);
+ regmap_write(it->lvds_regmap, LVDS_REG_4F, 0x11);
+
+ regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_SSC_PCLK_RF,
+ REG_SSC_PCLK_RF);
+ regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, 0x07, 0);
+ regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_DESSC_ENB,
+ REG_DESSC_ENB);
+}
+
+static inline void it6263_lvds_sys_cfg(struct it6263 *it)
+{
+ regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_LVDS_IN_SWAP,
+ it->lvds_link12_swap ? REG_LVDS_IN_SWAP : 0);
+}
+
+static inline void it6263_lvds_config(struct it6263 *it)
+{
+ it6263_lvds_reset(it);
+ it6263_lvds_set_interface(it);
+ it6263_lvds_set_afe(it);
+ it6263_lvds_sys_cfg(it);
+}
+
+static inline void it6263_hdmi_config(struct it6263 *it)
+{
+ regmap_write(it->hdmi_regmap, HDMI_REG_SW_RST, HDMI_RST_ALL);
+ regmap_write(it->hdmi_regmap, HDMI_REG_INPUT_MODE, IN_RGB);
+ regmap_write_bits(it->hdmi_regmap, HDMI_REG_GCP, HDMI_COLOR_DEPTH,
+ HDMI_COLOR_DEPTH_24);
+}
+
+static enum drm_connector_status it6263_detect(struct it6263 *it)
+{
+ unsigned int val;
+
+ regmap_read(it->hdmi_regmap, HDMI_REG_SYS_STATUS, &val);
+ if (val & HPDETECT)
+ return connector_status_connected;
+ else
+ return connector_status_disconnected;
+}
+
+static enum drm_connector_status
+it6263_connector_detect(struct drm_connector *connector, bool force)
+{
+ struct it6263 *it = connector_to_it6263(connector);
+
+ return it6263_detect(it);
+}
+
+static const struct drm_connector_funcs it6263_connector_funcs = {
+ .detect = it6263_connector_detect,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .destroy = drm_connector_cleanup,
+ .reset = drm_atomic_helper_connector_reset,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+static int it6263_read_edid(void *data, u8 *buf, unsigned int block, size_t len)
+{
+ struct it6263 *it = data;
+ struct regmap *regmap = it->hdmi_regmap;
+ unsigned int start = (block % 2) * EDID_LENGTH;
+ unsigned int segment = block >> 1;
+ unsigned int count, val;
+ int ret;
+
+ regmap_write(regmap, HDMI_REG_DDC_MASTER_CTRL, MASTER_SEL_HOST);
+ regmap_write(regmap, HDMI_REG_DDC_HEADER, DDC_ADDR << 1);
+ regmap_write(regmap, HDMI_REG_DDC_EDIDSEG, segment);
+
+ while (len) {
+ /* clear DDC FIFO */
+ regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_FIFO_CLR);
+
+ ret = regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS,
+ val, val & DDC_DONE,
+ 2000, 10000);
+ if (ret) {
+ dev_err(it->dev, "failed to clear DDC FIFO:%d\n", ret);
+ return ret;
+ }
+
+ count = len > HDMI_DDC_FIFO_BYTES ? HDMI_DDC_FIFO_BYTES : len;
+
+ /* fire the read command */
+ regmap_write(regmap, HDMI_REG_DDC_REQOFF, start);
+ regmap_write(regmap, HDMI_REG_DDC_REQCOUNT, count);
+ regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_EDID_READ);
+
+ start += count;
+ len -= count;
+
+ ret = regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS, val,
+ val & (DDC_DONE | DDC_ERROR),
+ 20000, 250000);
+ if (ret && !(val & DDC_ERROR)) {
+ dev_err(it->dev, "failed to read EDID:%d\n", ret);
+ return ret;
+ }
+
+ if (val & DDC_ERROR) {
+ dev_err(it->dev, "DDC error\n");
+ return -EIO;
+ }
+
+ /* cache to buffer */
+ for (; count > 0; count--) {
+ regmap_read(regmap, HDMI_REG_DDC_READFIFO, &val);
+ *(buf++) = val;
+ }
+ }
+
+ return 0;
+}
+
+static int it6263_connector_get_modes(struct drm_connector *connector)
+{
+ struct it6263 *it = connector_to_it6263(connector);
+ const struct drm_edid *drm_edid;
+ int count;
+
+ drm_edid = drm_edid_read_custom(connector, it6263_read_edid, it);
+
+ drm_edid_connector_update(connector, drm_edid);
+ count = drm_edid_connector_add_modes(connector);
+
+ drm_edid_free(drm_edid);
+
+ return count;
+}
+
+static const struct drm_connector_helper_funcs it6263_connector_helper_funcs = {
+ .get_modes = it6263_connector_get_modes,
+};
+
+static int it6263_bridge_atomic_check(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct drm_display_mode *mode = &crtc_state->adjusted_mode;
+
+ return mode->clock > MAX_PIXEL_CLOCK_KHZ ? -EINVAL : 0;
+}
+
+static void
+it6263_bridge_atomic_disable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
+{
+ struct it6263 *it = bridge_to_it6263(bridge);
+
+ regmap_write_bits(it->hdmi_regmap, HDMI_REG_GCP, AVMUTE, AVMUTE);
+ regmap_write(it->hdmi_regmap, HDMI_REG_PKT_GENERAL_CTRL, 0);
+ regmap_write(it->hdmi_regmap, HDMI_REG_AFE_DRV_CTRL,
+ AFE_DRV_RST | AFE_DRV_PWD);
+}
+
+static void
+it6263_hdmi_avi_infoframe_configure(struct it6263 *it,
+ struct drm_connector *connector,
+ const struct drm_display_mode *mode)
+{
+ struct hdmi_avi_infoframe frame;
+ u8 buf[HDMI_INFOFRAME_SIZE(AVI)];
+ int ret;
+
+ ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
+ if (ret) {
+ dev_err(it->dev, "failed to setup AVI infoframe: %d\n", ret);
+ return;
+ }
+
+ ret = hdmi_avi_infoframe_pack(&frame, buf, sizeof(buf));
+ if (ret < 0) {
+ dev_err(it->dev, "failed to pack infoframe: %d\n", ret);
+ return;
+ }
+
+ /* write the first AVI infoframe data byte chunk(DB1-DB5) */
+ ret = regmap_bulk_write(it->hdmi_regmap, HDMI_REG_AVI_DB1,
+ &buf[HDMI_INFOFRAME_HEADER_SIZE],
+ HDMI_AVI_DB_CHUNK1_SIZE);
+ if (ret) {
+ dev_err(it->dev, "failed to write the 1st AVI infoframe data byte chunk: %d\n",
+ ret);
+ return;
+ }
+
+ /* write the second AVI infoframe data byte chunk(DB6-DB13) */
+ ret = regmap_bulk_write(it->hdmi_regmap, HDMI_REG_AVI_DB6,
+ &buf[HDMI_INFOFRAME_HEADER_SIZE +
+ HDMI_AVI_DB_CHUNK1_SIZE],
+ HDMI_AVI_DB_CHUNK2_SIZE);
+ if (ret) {
+ dev_err(it->dev, "failed to write the 2nd AVI infoframe data byte chunk: %d\n",
+ ret);
+ return;
+ }
+
+ ret = regmap_write(it->hdmi_regmap, HDMI_REG_AVI_CSUM, buf[3]);
+ if (ret)
+ dev_err(it->dev, "failed to set AVI infoframe checksum: %d\n",
+ ret);
+}
+
+static void
+it6263_bridge_atomic_enable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
+{
+ struct drm_atomic_state *state = old_bridge_state->base.state;
+ struct it6263 *it = bridge_to_it6263(bridge);
+ const struct drm_crtc_state *crtc_state;
+ struct regmap *regmap = it->hdmi_regmap;
+ const struct drm_display_mode *mode;
+ struct drm_connector *connector;
+ bool is_stable = false;
+ struct drm_crtc *crtc;
+ unsigned int val;
+ bool pclk_high;
+ int i, ret;
+
+ connector = drm_atomic_get_new_connector_for_encoder(state,
+ bridge->encoder);
+ crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
+ crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+ mode = &crtc_state->adjusted_mode;
+
+ regmap_write(regmap, HDMI_REG_HDMI_MODE, TX_HDMI_MODE);
+
+ it6263_hdmi_avi_infoframe_configure(it, connector, mode);
+
+ /* HDMI AFE setup */
+ pclk_high = mode->clock > HIGH_PIXEL_CLOCK_KHZ ? true : false;
+ regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, AFE_DRV_RST);
+ if (pclk_high)
+ regmap_write(regmap, HDMI_REG_AFE_XP_CTRL,
+ AFE_XP_GAINBIT | AFE_XP_RESETB);
+ else
+ regmap_write(regmap, HDMI_REG_AFE_XP_CTRL,
+ AFE_XP_ER0 | AFE_XP_RESETB);
+ regmap_write(regmap, HDMI_REG_AFE_ISW_CTRL, 0x10);
+ if (pclk_high)
+ regmap_write(regmap, HDMI_REG_AFE_IP_CTRL,
+ AFE_IP_GAINBIT | AFE_IP_RESETB);
+ else
+ regmap_write(regmap, HDMI_REG_AFE_IP_CTRL,
+ AFE_IP_ER0 | AFE_IP_RESETB);
+
+ /* HDMI software video reset */
+ regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, SOFTV_RST);
+ fsleep(1000);
+ regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, 0);
+
+ /* reconfigure LVDS and retry several times in case video is instable */
+ for (i = 0; i < 3; i++) {
+ ret = regmap_read_poll_timeout(regmap, HDMI_REG_SYS_STATUS, val,
+ val & TXVIDSTABLE,
+ 20000, 500000);
+ if (!ret) {
+ is_stable = true;
+ break;
+ }
+
+ it6263_lvds_config(it);
+ }
+
+ if (!is_stable)
+ dev_warn(it->dev, "failed to wait for video stable\n");
+
+ /* HDMI AFE reset release and power up */
+ regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, 0);
+
+ regmap_write_bits(regmap, HDMI_REG_GCP, AVMUTE, 0);
+
+ regmap_write(regmap, HDMI_REG_PKT_GENERAL_CTRL, ENABLE_PKT | REPEAT_PKT);
+}
+
+static enum drm_mode_status
+it6263_bridge_mode_valid(struct drm_bridge *bridge,
+ const struct drm_display_info *info,
+ const struct drm_display_mode *mode)
+{
+ return mode->clock > MAX_PIXEL_CLOCK_KHZ ? MODE_CLOCK_HIGH : MODE_OK;
+}
+
+static int it6263_bridge_attach(struct drm_bridge *bridge,
+ enum drm_bridge_attach_flags flags)
+{
+ struct it6263 *it = bridge_to_it6263(bridge);
+ int ret;
+
+ ret = drm_bridge_attach(bridge->encoder, it->next_bridge, bridge,
+ flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+ if (ret < 0)
+ return ret;
+
+ if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
+ return 0;
+
+ it->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
+ DRM_CONNECTOR_POLL_DISCONNECT;
+
+ ret = drm_connector_init(bridge->dev, &it->connector,
+ &it6263_connector_funcs,
+ DRM_MODE_CONNECTOR_HDMIA);
+ if (ret)
+ return ret;
+
+ drm_connector_helper_add(&it->connector,
+ &it6263_connector_helper_funcs);
+ drm_connector_attach_encoder(&it->connector, bridge->encoder);
+
+ return 0;
+}
+
+static enum drm_connector_status it6263_bridge_detect(struct drm_bridge *bridge)
+{
+ struct it6263 *it = bridge_to_it6263(bridge);
+
+ return it6263_detect(it);
+}
+
+static const struct drm_edid *
+it6263_bridge_edid_read(struct drm_bridge *bridge,
+ struct drm_connector *connector)
+{
+ struct it6263 *it = bridge_to_it6263(bridge);
+
+ return drm_edid_read_custom(connector, it6263_read_edid, it);
+}
+
+static u32 *
+it6263_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ u32 output_fmt,
+ unsigned int *num_input_fmts)
+{
+ struct it6263 *it = bridge_to_it6263(bridge);
+ u32 *input_fmts;
+
+ *num_input_fmts = 0;
+
+ if (it->lvds_link_num_dlanes == 3)
+ return NULL;
+
+ input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
+ if (!input_fmts)
+ return NULL;
+
+ input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA;
+ *num_input_fmts = 1;
+
+ return input_fmts;
+}
+
+static const struct drm_bridge_funcs it6263_bridge_funcs = {
+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+ .atomic_reset = drm_atomic_helper_bridge_reset,
+ .attach = it6263_bridge_attach,
+ .mode_valid = it6263_bridge_mode_valid,
+ .atomic_disable = it6263_bridge_atomic_disable,
+ .atomic_enable = it6263_bridge_atomic_enable,
+ .atomic_check = it6263_bridge_atomic_check,
+ .detect = it6263_bridge_detect,
+ .edid_read = it6263_bridge_edid_read,
+ .atomic_get_input_bus_fmts = it6263_bridge_atomic_get_input_bus_fmts,
+};
+
+static int it6263_probe(struct i2c_client *client)
+{
+ struct device *dev = &client->dev;
+ struct it6263 *it;
+ int ret;
+
+ it = devm_kzalloc(dev, sizeof(*it), GFP_KERNEL);
+ if (!it)
+ return -ENOMEM;
+
+ it->dev = dev;
+ it->hdmi_i2c = client;
+
+ it->hdmi_regmap = devm_regmap_init_i2c(client,
+ &it6263_hdmi_regmap_config);
+ if (IS_ERR(it->hdmi_regmap))
+ return dev_err_probe(dev, PTR_ERR(it->hdmi_regmap),
+ "failed to init I2C regmap for HDMI\n");
+
+ it->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
+ if (IS_ERR(it->reset_gpio))
+ return dev_err_probe(dev, PTR_ERR(it->reset_gpio),
+ "failed to get reset gpio\n");
+
+ ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(it6263_supplies),
+ it6263_supplies);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to get power supplies\n");
+
+ ret = it6263_parse_dt(it);
+ if (ret)
+ return ret;
+
+ it6263_hw_reset(it);
+
+ ret = it6263_lvds_set_i2c_addr(it);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to set I2C addr\n");
+
+ it->lvds_i2c = devm_i2c_new_dummy_device(dev, client->adapter,
+ LVDS_INPUT_CTRL_I2C_ADDR);
+ if (IS_ERR(it->lvds_i2c))
+ dev_err_probe(it->dev, PTR_ERR(it->lvds_i2c),
+ "failed to allocate I2C device for LVDS\n");
+
+ it->lvds_regmap = devm_regmap_init_i2c(it->lvds_i2c,
+ &it6263_lvds_regmap_config);
+ if (IS_ERR(it->lvds_regmap))
+ return dev_err_probe(dev, PTR_ERR(it->lvds_regmap),
+ "failed to init I2C regmap for LVDS\n");
+
+ it6263_lvds_config(it);
+ it6263_hdmi_config(it);
+
+ i2c_set_clientdata(client, it);
+
+ it->bridge.funcs = &it6263_bridge_funcs;
+ it->bridge.of_node = dev->of_node;
+ it->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT;
+ it->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
+ drm_bridge_add(&it->bridge);
+
+ return 0;
+}
+
+static void it6263_remove(struct i2c_client *client)
+{
+ struct it6263 *it = i2c_get_clientdata(client);
+
+ drm_bridge_remove(&it->bridge);
+}
+
+static const struct of_device_id it6263_of_match[] = {
+ { .compatible = "ite,it6263", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, it6263_of_match);
+
+static const struct i2c_device_id it6263_i2c_ids[] = {
+ { "it6263", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, it6263_i2c_ids);
+
+static struct i2c_driver it6263_driver = {
+ .probe = it6263_probe,
+ .remove = it6263_remove,
+ .driver = {
+ .name = "it6263",
+ .of_match_table = it6263_of_match,
+ },
+ .id_table = it6263_i2c_ids,
+};
+module_i2c_driver(it6263_driver);
+
+MODULE_DESCRIPTION("ITE Tech. Inc. IT6263 LVDS/HDMI bridge");
+MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 7/9] arm64: dts: imx8mp-evk: Add NXP LVDS to HDMI adapter cards
2024-10-12 7:35 [PATCH v2 0/9] Add ITE IT6263 LVDS to HDMI converter support Liu Ying
` (5 preceding siblings ...)
2024-10-12 7:35 ` [PATCH v2 6/9] drm/bridge: " Liu Ying
@ 2024-10-12 7:35 ` Liu Ying
2024-10-12 7:35 ` [PATCH v2 8/9] arm64: defconfig: Enable ITE IT6263 driver Liu Ying
2024-10-12 7:35 ` [PATCH v2 9/9] MAINTAINERS: Add maintainer for " Liu Ying
8 siblings, 0 replies; 49+ messages in thread
From: Liu Ying @ 2024-10-12 7:35 UTC (permalink / raw)
To: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel
Cc: andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
dmitry.baryshkov, arnd, nfraprado, o.rempel, y.moog, marex,
isaac.scott, biju.das.jz
One ITE IT6263 LVDS to HDMI converter is populated on NXP IMX-LVDS-HDMI
and IMX-DLVDS-HDMI adapter cards.
Card IMX-LVDS-HDMI supports single LVDS link(IT6263 link1).
Card IMX-DLVDS-HDMI supports dual LVDS links(IT6263 link1 and link2).
Only one card can be enabled with one i.MX8MP EVK.
Add dedicated overlays to support the below four connections:
1) imx8mp-evk-lvds0-imx-lvds-hdmi.dtso:
i.MX8MP EVK LVDS0 connector <=> LVDS adapter card J6(IT6263 link1)
2) imx8mp-evk-lvds1-imx-lvds-hdmi.dtso:
i.MX8MP EVK LVDS1 connector <=> LVDS adapter card J6(IT6263 link1)
3) imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso:
i.MX8MP EVK LVDS0 connector <=> DLVDS adapter card channel0(IT6263 link1)
i.MX8MP EVK LVDS1 connector <=> DLVDS adapter card channel1(IT6263 link2)
4) imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso:
i.MX8MP EVK LVDS1 connector <=> DLVDS adapter card channel0(IT6263 link1)
i.MX8MP EVK LVDS0 connector <=> DLVDS adapter card channel1(IT6263 link2)
Part links:
https://www.nxp.com/part/IMX-LVDS-HDMI
https://www.nxp.com/part/IMX-DLVDS-HDMI
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v2:
* Add ite,lvds-link-num-data-lanes properties.
arch/arm64/boot/dts/freescale/Makefile | 8 ++++
.../imx8mp-evk-imx-lvds-hdmi-common.dtsi | 29 ++++++++++++
...8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso | 44 +++++++++++++++++++
...imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi | 43 ++++++++++++++++++
.../imx8mp-evk-lvds0-imx-lvds-hdmi.dtso | 28 ++++++++++++
...8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso | 44 +++++++++++++++++++
...imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi | 43 ++++++++++++++++++
.../imx8mp-evk-lvds1-imx-lvds-hdmi.dtso | 28 ++++++++++++
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 6 +++
9 files changed, 273 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-imx-lvds-hdmi-common.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi.dtso
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 9d3df8b218a2..cc4333f49c2d 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -196,7 +196,15 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-mallow.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-yavia.dtb
+imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtbo
+imx8mp-evk-lvds0-imx-lvds-hdmi-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds0-imx-lvds-hdmi.dtbo
+imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtbo
+imx8mp-evk-lvds1-imx-lvds-hdmi-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds1-imx-lvds-hdmi.dtbo
imx8mp-evk-mx8-dlvds-lcd1-dtbs += imx8mp-evk.dtb imx8mp-evk-mx8-dlvds-lcd1.dtbo
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds0-imx-lvds-hdmi.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds1-imx-lvds-hdmi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-mx8-dlvds-lcd1.dtb
imx8mp-tqma8mpql-mba8mpxl-lvds-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds.dtbo
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-imx-lvds-hdmi-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-evk-imx-lvds-hdmi-common.dtsi
new file mode 100644
index 000000000000..44b30e9b3fde
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-imx-lvds-hdmi-common.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ lvds-hdmi-connector {
+ compatible = "hdmi-connector";
+ label = "J2";
+ type = "a";
+
+ port {
+ lvds2hdmi_connector_in: endpoint {
+ remote-endpoint = <&it6263_out>;
+ };
+ };
+ };
+};
+
+&lcdif2 {
+ status = "okay";
+};
+
+&lvds_bridge {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso
new file mode 100644
index 000000000000..4008d2fd36d6
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include "imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi"
+
+&it6263 {
+ ports {
+ port@0 {
+ reg = <0>;
+ dual-lvds-odd-pixels;
+
+ it6263_lvds_link1: endpoint {
+ remote-endpoint = <&ldb_lvds_ch0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dual-lvds-even-pixels;
+
+ it6263_lvds_link2: endpoint {
+ remote-endpoint = <&ldb_lvds_ch1>;
+ };
+ };
+ };
+};
+
+&lvds_bridge {
+ ports {
+ port@1 {
+ ldb_lvds_ch0: endpoint {
+ remote-endpoint = <&it6263_lvds_link1>;
+ };
+ };
+
+ port@2 {
+ ldb_lvds_ch1: endpoint {
+ remote-endpoint = <&it6263_lvds_link2>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi
new file mode 100644
index 000000000000..757ce878c7cb
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "imx8mp-evk-imx-lvds-hdmi-common.dtsi"
+
+&i2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ it6263: hdmi@4c {
+ compatible = "ite,it6263";
+ reg = <0x4c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lvds_en>;
+ reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ ivdd-supply = <®_buck5>;
+ ovdd-supply = <®_vext_3v3>;
+ txavcc18-supply = <®_buck5>;
+ txavcc33-supply = <®_vext_3v3>;
+ pvcc1-supply = <®_buck5>;
+ pvcc2-supply = <®_buck5>;
+ avcc-supply = <®_vext_3v3>;
+ anvdd-supply = <®_buck5>;
+ apvdd-supply = <®_buck5>;
+ ite,lvds-link-num-data-lanes = /bits/ 8 <4>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ reg = <2>;
+
+ it6263_out: endpoint {
+ remote-endpoint = <&lvds2hdmi_connector_in>;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi.dtso b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi.dtso
new file mode 100644
index 000000000000..9e11f261ad13
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi.dtso
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include "imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi"
+
+&it6263 {
+ ports {
+ port@0 {
+ reg = <0>;
+
+ it6263_lvds_link1: endpoint {
+ remote-endpoint = <&ldb_lvds_ch0>;
+ };
+ };
+ };
+};
+
+&lvds_bridge {
+ ports {
+ port@1 {
+ ldb_lvds_ch0: endpoint {
+ remote-endpoint = <&it6263_lvds_link1>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso
new file mode 100644
index 000000000000..af2e73e36a1b
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include "imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi"
+
+&it6263 {
+ ports {
+ port@0 {
+ reg = <0>;
+ dual-lvds-even-pixels;
+
+ it6263_lvds_link1: endpoint {
+ remote-endpoint = <&ldb_lvds_ch1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dual-lvds-odd-pixels;
+
+ it6263_lvds_link2: endpoint {
+ remote-endpoint = <&ldb_lvds_ch0>;
+ };
+ };
+ };
+};
+
+&lvds_bridge {
+ ports {
+ port@1 {
+ ldb_lvds_ch0: endpoint {
+ remote-endpoint = <&it6263_lvds_link2>;
+ };
+ };
+
+ port@2 {
+ ldb_lvds_ch1: endpoint {
+ remote-endpoint = <&it6263_lvds_link1>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi
new file mode 100644
index 000000000000..7381dbd0b7f6
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "imx8mp-evk-imx-lvds-hdmi-common.dtsi"
+
+&i2c3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ it6263: hdmi@4c {
+ compatible = "ite,it6263";
+ reg = <0x4c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lvds_en>;
+ reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ ivdd-supply = <®_buck5>;
+ ovdd-supply = <®_vext_3v3>;
+ txavcc18-supply = <®_buck5>;
+ txavcc33-supply = <®_vext_3v3>;
+ pvcc1-supply = <®_buck5>;
+ pvcc2-supply = <®_buck5>;
+ avcc-supply = <®_vext_3v3>;
+ anvdd-supply = <®_buck5>;
+ apvdd-supply = <®_buck5>;
+ ite,lvds-link-num-data-lanes = /bits/ 8 <4>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ reg = <2>;
+
+ it6263_out: endpoint {
+ remote-endpoint = <&lvds2hdmi_connector_in>;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi.dtso b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi.dtso
new file mode 100644
index 000000000000..527a893a71b2
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi.dtso
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include "imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi"
+
+&it6263 {
+ ports {
+ port@0 {
+ reg = <0>;
+
+ it6263_lvds_link1: endpoint {
+ remote-endpoint = <&ldb_lvds_ch1>;
+ };
+ };
+ };
+};
+
+&lvds_bridge {
+ ports {
+ port@2 {
+ ldb_lvds_ch1: endpoint {
+ remote-endpoint = <&it6263_lvds_link1>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index d26930f1a9e9..68e12a752edd 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -938,6 +938,12 @@ MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2
>;
};
+ pinctrl_lvds_en: lvdsengrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c0
+ >;
+ };
+
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60 /* open drain, pull up */
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 8/9] arm64: defconfig: Enable ITE IT6263 driver
2024-10-12 7:35 [PATCH v2 0/9] Add ITE IT6263 LVDS to HDMI converter support Liu Ying
` (6 preceding siblings ...)
2024-10-12 7:35 ` [PATCH v2 7/9] arm64: dts: imx8mp-evk: Add NXP LVDS to HDMI adapter cards Liu Ying
@ 2024-10-12 7:35 ` Liu Ying
2024-10-12 7:35 ` [PATCH v2 9/9] MAINTAINERS: Add maintainer for " Liu Ying
8 siblings, 0 replies; 49+ messages in thread
From: Liu Ying @ 2024-10-12 7:35 UTC (permalink / raw)
To: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel
Cc: andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
dmitry.baryshkov, arnd, nfraprado, o.rempel, y.moog, marex,
isaac.scott, biju.das.jz
ITE IT6263 LVDS to HDMI converter is populated on NXP IMX-LVDS-HDMI
and IMX-DLVDS-HDMI adapter cards. The adapter cards can connect to
i.MX8MP EVK base board to support video output through HDMI connectors.
Build the ITE IT6263 driver as a module.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v2:
* No change.
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 5fdbfea7a5b2..d8a232e285d4 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -899,6 +899,7 @@ CONFIG_DRM_PANEL_SITRONIX_ST7703=m
CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m
CONFIG_DRM_FSL_LDB=m
+CONFIG_DRM_ITE_IT6263=m
CONFIG_DRM_LONTIUM_LT8912B=m
CONFIG_DRM_LONTIUM_LT9611=m
CONFIG_DRM_LONTIUM_LT9611UXC=m
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 9/9] MAINTAINERS: Add maintainer for ITE IT6263 driver
2024-10-12 7:35 [PATCH v2 0/9] Add ITE IT6263 LVDS to HDMI converter support Liu Ying
` (7 preceding siblings ...)
2024-10-12 7:35 ` [PATCH v2 8/9] arm64: defconfig: Enable ITE IT6263 driver Liu Ying
@ 2024-10-12 7:35 ` Liu Ying
8 siblings, 0 replies; 49+ messages in thread
From: Liu Ying @ 2024-10-12 7:35 UTC (permalink / raw)
To: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel
Cc: andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
dmitry.baryshkov, arnd, nfraprado, o.rempel, y.moog, marex,
isaac.scott, biju.das.jz
Add myself as the maintainer of ITE IT6263 LVDS TO HDMI BRIDGE DRIVER.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v2:
* New patch. (Maxime)
MAINTAINERS | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index a097afd76ded..3ce9ab8327e9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12142,6 +12142,14 @@ W: https://linuxtv.org
Q: http://patchwork.linuxtv.org/project/linux-media/list/
F: drivers/media/tuners/it913x*
+ITE IT6263 LVDS TO HDMI BRIDGE DRIVER
+M: Liu Ying <victor.liu@nxp.com>
+L: dri-devel@lists.freedesktop.org
+S: Maintained
+T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
+F: Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
+F: drivers/gpu/drm/bridge/ite-it6263.c
+
ITE IT66121 HDMI BRIDGE DRIVER
M: Phong LE <ple@baylibre.com>
M: Neil Armstrong <neil.armstrong@linaro.org>
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-12 7:35 ` [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter Liu Ying
@ 2024-10-12 8:30 ` Dmitry Baryshkov
2024-10-12 9:14 ` Liu Ying
0 siblings, 1 reply; 49+ messages in thread
From: Dmitry Baryshkov @ 2024-10-12 8:30 UTC (permalink / raw)
To: Liu Ying
Cc: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel,
andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
arnd, nfraprado, o.rempel, y.moog, marex, isaac.scott,
biju.das.jz
On Sat, Oct 12, 2024 at 03:35:39PM +0800, Liu Ying wrote:
> Document ITE IT6263 LVDS to HDMI converter.
>
> Product link:
> https://www.ite.com.tw/en/product/cate1/IT6263
>
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> ---
> v2:
> * Document number of LVDS link data lanes. (Biju)
> * Simplify ports property by dropping "oneOf". (Rob)
>
> .../bindings/display/bridge/ite,it6263.yaml | 276 ++++++++++++++++++
> 1 file changed, 276 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
> new file mode 100644
> index 000000000000..bc2bbec07623
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
> @@ -0,0 +1,276 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/ite,it6263.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ITE IT6263 LVDS to HDMI converter
> +
> +maintainers:
> + - Liu Ying <victor.liu@nxp.com>
> +
> +description: |
> + The IT6263 is a high-performance single-chip De-SSC(De-Spread Spectrum) LVDS
> + to HDMI converter. Combined with LVDS receiver and HDMI 1.4a transmitter,
> + the IT6263 supports LVDS input and HDMI 1.4 output by conversion function.
> + The built-in LVDS receiver can support single-link and dual-link LVDS inputs,
> + and the built-in HDMI transmitter is fully compliant with HDMI 1.4a/3D, HDCP
> + 1.2 and backward compatible with DVI 1.0 specification.
> +
> + The IT6263 also encodes and transmits up to 8 channels of I2S digital audio,
> + with sampling rate up to 192KHz and sample size up to 24 bits. In addition,
> + an S/PDIF input port takes in compressed audio of up to 192KHz frame rate.
> +
> + The newly supported High-Bit Rate(HBR) audio by HDMI specifications v1.3 is
> + provided by the IT6263 in two interfaces: the four I2S input ports or the
> + S/PDIF input port. With both interfaces the highest possible HBR frame rate
> + is supported at up to 768KHz.
> +
> +properties:
No LVDS data-mapping support?
> + compatible:
> + const: ite,it6263
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> + description: audio master clock
> +
> + clock-names:
> + const: mclk
> +
> + reset-gpios:
> + maxItems: 1
> +
> + ivdd-supply:
> + description: 1.8V digital logic power
> +
> + ovdd-supply:
> + description: 3.3V I/O pin power
> +
> + txavcc18-supply:
> + description: 1.8V HDMI analog frontend power
> +
> + txavcc33-supply:
> + description: 3.3V HDMI analog frontend power
> +
> + pvcc1-supply:
> + description: 1.8V HDMI frontend core PLL power
> +
> + pvcc2-supply:
> + description: 1.8V HDMI frontend filter PLL power
> +
> + avcc-supply:
> + description: 3.3V LVDS frontend power
> +
> + anvdd-supply:
> + description: 1.8V LVDS frontend analog power
> +
> + apvdd-supply:
> + description: 1.8V LVDS frontend PLL power
> +
> + "#sound-dai-cells":
> + const: 0
> +
> + ite,lvds-link-num-data-lanes:
> + $ref: /schemas/types.yaml#/definitions/uint8
> + enum: [3, 4, 5]
> + description: number of data lanes per LVDS link
Please use data-lanes property inside the OF graph.
> +
> + ite,i2s-audio-fifo-sources:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + minItems: 1
> + maxItems: 4
> + items:
> + enum: [0, 1, 2, 3]
> + description:
> + Each array element indicates the pin number of an I2S serial data input
> + line which is connected to an audio FIFO, from audio FIFO0 to FIFO3.
What does that mean from the board point of view? Routed audio links for
the multichannel audio?
> +
> + ite,rl-channel-swap-audio-sources:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + minItems: 1
> + maxItems: 4
> + uniqueItems: true
> + items:
> + enum: [0, 1, 2, 3]
> + description:
> + Each array element indicates an audio source whose right channel and left
> + channel are swapped by this converter. For I2S, the element is the pin
> + number of an I2S serial data input line. For S/PDIF, the element is always
> + 0.
Why?
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + The first LVDS input link.
> + In dual-link LVDS mode, this link works together with the second LVDS
> + input link, and one link receives odd pixels while the other receives
> + even pixels. Specify the pixels with one of the dual-lvds-odd-pixels
> + and dual-lvds-even-pixels properties when and only when dual-link LVDS
> + mode is used.
> +
> + properties:
> + dual-lvds-odd-pixels:
> + type: boolean
> + description: the first sink port for odd pixels
> +
> + dual-lvds-even-pixels:
> + type: boolean
> + description: the first sink port for even pixels
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description: the second LVDS input link
> +
> + properties:
> + dual-lvds-even-pixels:
> + type: boolean
> + description: the second sink port for even pixels
> +
> + dual-lvds-odd-pixels:
> + type: boolean
> + description: the second sink port for odd pixels
> +
> + oneOf:
> + - required: [dual-lvds-even-pixels]
> + - required: [dual-lvds-odd-pixels]
This still allows one to specify that both ports provide odd pixels. Is
that expected? Also why do you need two properties which specify the
same option.
My suggestion would be to add a single root-level property which
specifies which port provides even pixel data.
> +
> + port@2:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: video port for the HDMI output
> +
> + port@3:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: sound input port
> +
> + required:
> + - port@0
> + - port@2
> +
> +required:
> + - compatible
> + - reg
> + - ivdd-supply
> + - ovdd-supply
> + - txavcc18-supply
> + - txavcc33-supply
> + - pvcc1-supply
> + - pvcc2-supply
> + - avcc-supply
> + - anvdd-supply
> + - apvdd-supply
> + - ite,lvds-link-num-data-lanes
> + - ports
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + /* single-link LVDS input */
> + #include <dt-bindings/gpio/gpio.h>
> +
> + i2c {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + hdmi@4c {
> + compatible = "ite,it6263";
> + reg = <0x4c>;
> + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
> + ivdd-supply = <®_buck5>;
> + ovdd-supply = <®_vext_3v3>;
> + txavcc18-supply = <®_buck5>;
> + txavcc33-supply = <®_vext_3v3>;
> + pvcc1-supply = <®_buck5>;
> + pvcc2-supply = <®_buck5>;
> + avcc-supply = <®_vext_3v3>;
> + anvdd-supply = <®_buck5>;
> + apvdd-supply = <®_buck5>;
> + ite,lvds-link-num-data-lanes = /bits/ 8 <4>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + it6263_lvds_link1: endpoint {
> + remote-endpoint = <&ldb_lvds_ch0>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> +
> + it6263_out: endpoint {
> + remote-endpoint = <&hdmi_in>;
> + };
> + };
> + };
> + };
> + };
> +
> + - |
> + /* dual-link LVDS input */
> + #include <dt-bindings/gpio/gpio.h>
> +
> + i2c {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + hdmi@4c {
> + compatible = "ite,it6263";
> + reg = <0x4c>;
> + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
> + ivdd-supply = <®_buck5>;
> + ovdd-supply = <®_vext_3v3>;
> + txavcc18-supply = <®_buck5>;
> + txavcc33-supply = <®_vext_3v3>;
> + pvcc1-supply = <®_buck5>;
> + pvcc2-supply = <®_buck5>;
> + avcc-supply = <®_vext_3v3>;
> + anvdd-supply = <®_buck5>;
> + apvdd-supply = <®_buck5>;
> + ite,lvds-link-num-data-lanes = /bits/ 8 <4>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dual-lvds-odd-pixels;
> +
> + it6263_lvds_link1_dual: endpoint {
> + remote-endpoint = <&ldb_lvds_ch0>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dual-lvds-even-pixels;
> +
> + it6263_lvds_link2_dual: endpoint {
> + remote-endpoint = <&ldb_lvds_ch1>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> +
> + it6263_out_dual: endpoint {
> + remote-endpoint = <&hdmi_in>;
> + };
> + };
> + };
> + };
> + };
> --
> 2.34.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-12 7:35 ` [PATCH v2 6/9] drm/bridge: " Liu Ying
@ 2024-10-12 8:45 ` Dmitry Baryshkov
2024-10-12 10:01 ` Liu Ying
2024-10-13 10:27 ` Biju Das
2024-10-14 7:10 ` Dmitry Baryshkov
2024-10-15 4:54 ` kernel test robot
2 siblings, 2 replies; 49+ messages in thread
From: Dmitry Baryshkov @ 2024-10-12 8:45 UTC (permalink / raw)
To: Liu Ying
Cc: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel,
andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
arnd, nfraprado, o.rempel, y.moog, marex, isaac.scott,
biju.das.jz
On Sat, Oct 12, 2024 at 03:35:40PM +0800, Liu Ying wrote:
> Add basic HDMI video output support. Currently, only RGB888 output
> pixel format is supported. At the LVDS input side, the driver
> supports single LVDS link and dual LVDS links with "jeida-24" LVDS
> mapping.
>
> Product link:
> https://www.ite.com.tw/en/product/cate1/IT6263
>
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> ---
> v2:
> * Add AVI inforframe support. (Maxime)
Maxime asked to wire up the HDMI Connector framework. I have pushed the
patch that converts lt9611.c driver. Please implement similar changes in
your driver.
> * Add DRM_MODE_CONNECTOR_HDMIA. (Biju)
> * Rename it6263_reset() to it6263_hw_reset(). (Biju)
> * Check number of LVDS link data lanes. (Biju)
>
> drivers/gpu/drm/bridge/Kconfig | 8 +
> drivers/gpu/drm/bridge/Makefile | 1 +
> drivers/gpu/drm/bridge/ite-it6263.c | 919 ++++++++++++++++++++++++++++
> 3 files changed, 928 insertions(+)
> create mode 100644 drivers/gpu/drm/bridge/ite-it6263.c
>
> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> index 3eb955333c80..93f99682a090 100644
> --- a/drivers/gpu/drm/bridge/Kconfig
> +++ b/drivers/gpu/drm/bridge/Kconfig
> @@ -90,6 +90,14 @@ config DRM_FSL_LDB
> help
> Support for i.MX8MP DPI-to-LVDS on-SoC encoder.
>
> +config DRM_ITE_IT6263
> + tristate "ITE IT6263 LVDS/HDMI bridge"
> + depends on OF
> + select DRM_KMS_HELPER
> + select REGMAP_I2C
> + help
> + ITE IT6263 LVDS to HDMI bridge chip driver.
> +
> config DRM_ITE_IT6505
> tristate "ITE IT6505 DisplayPort bridge"
> depends on OF
> diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
> index 7df87b582dca..f3776dd473fd 100644
> --- a/drivers/gpu/drm/bridge/Makefile
> +++ b/drivers/gpu/drm/bridge/Makefile
> @@ -6,6 +6,7 @@ obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
> obj-$(CONFIG_DRM_CROS_EC_ANX7688) += cros-ec-anx7688.o
> obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
> obj-$(CONFIG_DRM_FSL_LDB) += fsl-ldb.o
> +obj-$(CONFIG_DRM_ITE_IT6263) += ite-it6263.o
> obj-$(CONFIG_DRM_ITE_IT6505) += ite-it6505.o
> obj-$(CONFIG_DRM_LONTIUM_LT8912B) += lontium-lt8912b.o
> obj-$(CONFIG_DRM_LONTIUM_LT9211) += lontium-lt9211.o
> diff --git a/drivers/gpu/drm/bridge/ite-it6263.c b/drivers/gpu/drm/bridge/ite-it6263.c
> new file mode 100644
> index 000000000000..9b3318792f15
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/ite-it6263.c
> @@ -0,0 +1,919 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/bits.h>
> +#include <linux/delay.h>
> +#include <linux/gpio/consumer.h>
> +#include <linux/hdmi.h>
> +#include <linux/i2c.h>
> +#include <linux/media-bus-format.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
> +
> +#include <drm/drm_atomic.h>
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_atomic_state_helper.h>
> +#include <drm/drm_bridge.h>
> +#include <drm/drm_connector.h>
> +#include <drm/drm_crtc.h>
> +#include <drm/drm_edid.h>
> +#include <drm/drm_of.h>
> +#include <drm/drm_probe_helper.h>
> +
> +/* -----------------------------------------------------------------------------
> + * LVDS registers
> + */
> +
> +/* LVDS software reset registers */
> +#define LVDS_REG_05 0x05
> +#define REG_SOFT_P_RST BIT(1)
> +
> +/* LVDS system configuration registers */
> +/* 0x0b */
> +#define LVDS_REG_0B 0x0b
> +#define REG_SSC_PCLK_RF BIT(0)
> +#define REG_LVDS_IN_SWAP BIT(1)
> +
> +/* LVDS test pattern gen control registers */
> +/* 0x2c */
> +#define LVDS_REG_2C 0x2c
> +#define REG_COL_DEP GENMASK(1, 0)
> +#define BIT8 FIELD_PREP(REG_COL_DEP, 2)
> +#define OUT_MAP BIT(4)
> +#define JEIDA 0
> +#define REG_DESSC_ENB BIT(6)
> +#define DMODE BIT(7)
> +#define DISO BIT(7)
> +#define SISO 0
> +
> +#define LVDS_REG_3C 0x3c
> +#define LVDS_REG_3F 0x3f
> +#define LVDS_REG_47 0x47
> +#define LVDS_REG_48 0x48
> +#define LVDS_REG_4F 0x4f
> +#define LVDS_REG_52 0x52
> +
> +/* -----------------------------------------------------------------------------
> + * HDMI registers are separated into three banks:
> + * 1) HDMI register common bank: 0x00 ~ 0x2f
> + */
> +
> +/* HDMI genernal registers */
> +#define HDMI_REG_SW_RST 0x04
> +#define SOFTREF_RST BIT(5)
> +#define SOFTA_RST BIT(4)
> +#define SOFTV_RST BIT(3)
> +#define AUD_RST BIT(2)
> +#define HDCP_RST BIT(0)
> +#define HDMI_RST_ALL (SOFTREF_RST | SOFTA_RST | SOFTV_RST | \
> + AUD_RST | HDCP_RST)
> +
> +#define HDMI_REG_SYS_STATUS 0x0e
> +#define HPDETECT BIT(6)
> +#define TXVIDSTABLE BIT(4)
> +
> +#define HDMI_REG_BANK_CTRL 0x0f
> +#define REG_BANK_SEL BIT(0)
> +
> +/* HDMI System DDC control registers */
> +#define HDMI_REG_DDC_MASTER_CTRL 0x10
> +#define MASTER_SEL_HOST BIT(0)
> +
> +#define HDMI_REG_DDC_HEADER 0x11
> +
> +#define HDMI_REG_DDC_REQOFF 0x12
> +#define HDMI_REG_DDC_REQCOUNT 0x13
> +#define HDMI_REG_DDC_EDIDSEG 0x14
> +
> +#define HDMI_REG_DDC_CMD 0x15
> +#define DDC_CMD_EDID_READ 0x3
> +#define DDC_CMD_FIFO_CLR 0x9
> +
> +#define HDMI_REG_DDC_STATUS 0x16
> +#define DDC_DONE BIT(7)
> +#define DDC_NOACK BIT(5)
> +#define DDC_WAITBUS BIT(4)
> +#define DDC_ARBILOSE BIT(3)
> +#define DDC_ERROR (DDC_NOACK | DDC_WAITBUS | DDC_ARBILOSE)
> +
> +#define HDMI_DDC_FIFO_BYTES 32
> +#define HDMI_REG_DDC_READFIFO 0x17
> +#define HDMI_REG_LVDS_PORT 0x1d /* LVDS input control I2C addr */
> +#define HDMI_REG_LVDS_PORT_EN 0x1e
> +#define LVDS_INPUT_CTRL_I2C_ADDR 0x33
> +
> +/* -----------------------------------------------------------------------------
> + * 2) HDMI register bank0: 0x30 ~ 0xff
> + */
> +
> +/* HDMI AFE registers */
> +#define HDMI_REG_AFE_DRV_CTRL 0x61
> +#define AFE_DRV_PWD BIT(5)
> +#define AFE_DRV_RST BIT(4)
> +
> +#define HDMI_REG_AFE_XP_CTRL 0x62
> +#define AFE_XP_GAINBIT BIT(7)
> +#define AFE_XP_ER0 BIT(4)
> +#define AFE_XP_RESETB BIT(3)
> +
> +#define HDMI_REG_AFE_ISW_CTRL 0x63
> +
> +#define HDMI_REG_AFE_IP_CTRL 0x64
> +#define AFE_IP_GAINBIT BIT(7)
> +#define AFE_IP_ER0 BIT(3)
> +#define AFE_IP_RESETB BIT(2)
> +
> +/* HDMI input data format registers */
> +#define HDMI_REG_INPUT_MODE 0x70
> +#define IN_RGB 0x00
> +
> +/* HDMI general control registers */
> +#define HDMI_REG_HDMI_MODE 0xc0
> +#define TX_HDMI_MODE BIT(0)
> +
> +#define HDMI_REG_GCP 0xc1
> +#define AVMUTE BIT(0)
> +#define HDMI_COLOR_DEPTH GENMASK(6, 4)
> +#define HDMI_COLOR_DEPTH_24 FIELD_PREP(HDMI_COLOR_DEPTH, 4)
> +
> +#define HDMI_REG_PKT_GENERAL_CTRL 0xc6
> +#define ENABLE_PKT BIT(0)
> +#define REPEAT_PKT BIT(1)
> +
> +/* -----------------------------------------------------------------------------
> + * 3) HDMI register bank1: 0x130 ~ 0x1ff (HDMI packet registers)
> + */
> +
> +/* AVI packet registers */
> +#define HDMI_REG_AVI_DB1 0x158
> +#define HDMI_REG_AVI_DB2 0x159
> +#define HDMI_REG_AVI_DB3 0x15a
> +#define HDMI_REG_AVI_DB4 0x15b
> +#define HDMI_REG_AVI_DB5 0x15c
> +#define HDMI_REG_AVI_CSUM 0x15d
> +#define HDMI_REG_AVI_DB6 0x15e
> +#define HDMI_REG_AVI_DB7 0x15f
> +#define HDMI_REG_AVI_DB8 0x160
> +#define HDMI_REG_AVI_DB9 0x161
> +#define HDMI_REG_AVI_DB10 0x162
> +#define HDMI_REG_AVI_DB11 0x163
> +#define HDMI_REG_AVI_DB12 0x164
> +#define HDMI_REG_AVI_DB13 0x165
> +
> +#define HDMI_AVI_DB_CHUNK1_SIZE (HDMI_REG_AVI_DB5 - HDMI_REG_AVI_DB1 + 1)
> +#define HDMI_AVI_DB_CHUNK2_SIZE (HDMI_REG_AVI_DB13 - HDMI_REG_AVI_DB6 + 1)
> +
> +#define MAX_PIXEL_CLOCK_KHZ 150000
> +#define HIGH_PIXEL_CLOCK_KHZ 80000
> +
> +struct it6263 {
> + struct device *dev;
> + struct i2c_client *hdmi_i2c;
> + struct i2c_client *lvds_i2c;
> + struct regmap *hdmi_regmap;
> + struct regmap *lvds_regmap;
> + struct drm_bridge bridge;
> + struct drm_bridge *next_bridge;
> + struct drm_connector connector;
> + struct gpio_desc *reset_gpio;
> + u8 lvds_link_num_dlanes;
> + bool lvds_dual_link;
> + bool lvds_link12_swap;
> +};
> +
> +static inline struct it6263 *bridge_to_it6263(struct drm_bridge *bridge)
> +{
> + return container_of(bridge, struct it6263, bridge);
> +}
> +
> +static inline struct it6263 *connector_to_it6263(struct drm_connector *conn)
> +{
> + return container_of(conn, struct it6263, connector);
> +}
> +
> +static bool it6263_hdmi_writeable_reg(struct device *dev, unsigned int reg)
> +{
> + switch (reg) {
> + case HDMI_REG_SW_RST:
> + case HDMI_REG_BANK_CTRL:
> + case HDMI_REG_DDC_MASTER_CTRL:
> + case HDMI_REG_DDC_HEADER:
> + case HDMI_REG_DDC_REQOFF:
> + case HDMI_REG_DDC_REQCOUNT:
> + case HDMI_REG_DDC_EDIDSEG:
> + case HDMI_REG_DDC_CMD:
> + case HDMI_REG_LVDS_PORT:
> + case HDMI_REG_LVDS_PORT_EN:
> + case HDMI_REG_AFE_DRV_CTRL:
> + case HDMI_REG_AFE_XP_CTRL:
> + case HDMI_REG_AFE_ISW_CTRL:
> + case HDMI_REG_AFE_IP_CTRL:
> + case HDMI_REG_INPUT_MODE:
> + case HDMI_REG_HDMI_MODE:
> + case HDMI_REG_GCP:
> + case HDMI_REG_PKT_GENERAL_CTRL:
> + case HDMI_REG_AVI_DB1:
> + case HDMI_REG_AVI_DB2:
> + case HDMI_REG_AVI_DB3:
> + case HDMI_REG_AVI_DB4:
> + case HDMI_REG_AVI_DB5:
> + case HDMI_REG_AVI_CSUM:
> + case HDMI_REG_AVI_DB6:
> + case HDMI_REG_AVI_DB7:
> + case HDMI_REG_AVI_DB8:
> + case HDMI_REG_AVI_DB9:
> + case HDMI_REG_AVI_DB10:
> + case HDMI_REG_AVI_DB11:
> + case HDMI_REG_AVI_DB12:
> + case HDMI_REG_AVI_DB13:
> + return true;
> + default:
> + return false;
> + }
> +}
> +
> +static bool it6263_hdmi_readable_reg(struct device *dev, unsigned int reg)
> +{
> + if (it6263_hdmi_writeable_reg(dev, reg))
> + return true;
> +
> + switch (reg) {
> + case HDMI_REG_SYS_STATUS:
> + case HDMI_REG_DDC_STATUS:
> + case HDMI_REG_DDC_READFIFO:
> + return true;
> + default:
> + return false;
> + }
> +}
> +
> +static bool it6263_hdmi_volatile_reg(struct device *dev, unsigned int reg)
> +{
> + switch (reg) {
> + case HDMI_REG_SW_RST:
> + case HDMI_REG_SYS_STATUS:
> + case HDMI_REG_DDC_STATUS:
> + case HDMI_REG_DDC_READFIFO:
> + return true;
> + default:
> + return false;
> + }
> +}
> +
> +static const struct regmap_range_cfg it6263_hdmi_range_cfg = {
> + .range_min = 0x00,
> + .range_max = HDMI_REG_AVI_DB13,
> + .selector_reg = HDMI_REG_BANK_CTRL,
> + .selector_mask = REG_BANK_SEL,
> + .selector_shift = 0,
> + .window_start = 0x00,
> + .window_len = 0x100,
> +};
> +
> +static const struct regmap_config it6263_hdmi_regmap_config = {
> + .name = "it6263-hdmi",
> + .reg_bits = 8,
> + .val_bits = 8,
> + .writeable_reg = it6263_hdmi_writeable_reg,
> + .readable_reg = it6263_hdmi_readable_reg,
> + .volatile_reg = it6263_hdmi_volatile_reg,
> + .max_register = HDMI_REG_AVI_DB13,
> + .ranges = &it6263_hdmi_range_cfg,
> + .num_ranges = 1,
> + .cache_type = REGCACHE_MAPLE,
> +};
> +
> +static bool it6263_lvds_writeable_reg(struct device *dev, unsigned int reg)
> +{
> + switch (reg) {
> + case LVDS_REG_05:
> + case LVDS_REG_0B:
> + case LVDS_REG_2C:
> + case LVDS_REG_3C:
> + case LVDS_REG_3F:
> + case LVDS_REG_47:
> + case LVDS_REG_48:
> + case LVDS_REG_4F:
> + case LVDS_REG_52:
> + return true;
> + default:
> + return false;
> + }
> +}
> +
> +static bool it6263_lvds_readable_reg(struct device *dev, unsigned int reg)
> +{
> + return it6263_lvds_writeable_reg(dev, reg);
> +}
> +
> +static bool it6263_lvds_volatile_reg(struct device *dev, unsigned int reg)
> +{
> + return reg == LVDS_REG_05;
> +}
> +
> +static const struct regmap_config it6263_lvds_regmap_config = {
> + .name = "it6263-lvds",
> + .reg_bits = 8,
> + .val_bits = 8,
> + .writeable_reg = it6263_lvds_writeable_reg,
> + .readable_reg = it6263_lvds_readable_reg,
> + .volatile_reg = it6263_lvds_volatile_reg,
> + .max_register = LVDS_REG_52,
> + .cache_type = REGCACHE_MAPLE,
> +};
> +
> +static const char * const it6263_supplies[] = {
> + "ivdd", "ovdd", "txavcc18", "txavcc33", "pvcc1", "pvcc2",
> + "avcc", "anvdd", "apvdd"
> +};
> +
> +static int it6263_parse_dt(struct it6263 *it)
> +{
> + struct device *dev = it->dev;
> + struct device_node *port0, *port1;
> + int ret;
> +
> + ret = of_property_read_u8(dev->of_node, "ite,lvds-link-num-data-lanes",
> + &it->lvds_link_num_dlanes);
> + if (ret) {
> + dev_err(dev, "failed to get LVDS link number of data lanes: %d\n",
> + ret);
> + return ret;
> + }
> +
> + it->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0);
> + if (IS_ERR(it->next_bridge))
> + return dev_err_probe(dev, PTR_ERR(it->next_bridge),
> + "failed to get next bridge\n");
> +
> + port0 = of_graph_get_port_by_id(dev->of_node, 0);
> + port1 = of_graph_get_port_by_id(dev->of_node, 1);
> + if (port0 && port1) {
> + if (of_property_read_bool(port0, "dual-lvds-even-pixels") &&
> + of_property_read_bool(port1, "dual-lvds-odd-pixels")) {
> + it->lvds_dual_link = true;
> + it->lvds_link12_swap = true;
This is a nice name for the propery in the Dual Link LVDS case:
ite,lvds-link-swap
> + } else if (of_property_read_bool(port0, "dual-lvds-odd-pixels") &&
> + of_property_read_bool(port1, "dual-lvds-even-pixels")) {
> + it->lvds_dual_link = true;
> + }
> +
> + if (!it->lvds_dual_link) {
> + dev_err(dev,
> + "failed to get LVDS dual link pixel order\n");
> + ret = -EINVAL;
> + }
> + } else if (port1) {
> + ret = -EINVAL;
> + dev_err(dev, "single input LVDS port1 is not supported\n");
> + } else if (!port0) {
> + ret = -EINVAL;
> + dev_err(dev, "no input LVDS port\n");
> + }
> +
> + of_node_put(port0);
> + of_node_put(port1);
> +
> + return ret;
> +}
> +
> +static inline void it6263_hw_reset(struct it6263 *it)
> +{
> + if (!it->reset_gpio)
> + return;
> +
> + gpiod_set_value_cansleep(it->reset_gpio, 0);
> + fsleep(1000);
> + gpiod_set_value_cansleep(it->reset_gpio, 1);
> + /* The chip maker says the low pulse should be at least 40ms. */
> + fsleep(40000);
> + gpiod_set_value_cansleep(it->reset_gpio, 0);
> + /* addtional time to wait the high voltage to be stable */
> + fsleep(5000);
> +}
> +
> +static inline int it6263_lvds_set_i2c_addr(struct it6263 *it)
> +{
> + int ret;
> +
> + ret = regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT,
> + LVDS_INPUT_CTRL_I2C_ADDR << 1);
> + if (ret)
> + return ret;
> +
> + return regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT_EN, BIT(0));
> +}
> +
> +static inline void it6263_lvds_reset(struct it6263 *it)
> +{
> + /* AFE PLL reset */
> + regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), 0x0);
> + fsleep(1000);
> + regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), BIT(0));
> +
> + /* software pixel clock domain reset */
> + regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST,
> + REG_SOFT_P_RST);
> + fsleep(1000);
> + regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST, 0x0);
> + fsleep(10000);
> +}
> +
> +static inline void it6263_lvds_set_interface(struct it6263 *it)
> +{
> + /* color depth */
> + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_COL_DEP, BIT8);
> + /* output mapping */
> + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, OUT_MAP, JEIDA);
> +
> + if (it->lvds_dual_link) {
> + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, DISO);
> + regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), BIT(1));
> + } else {
> + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, SISO);
> + regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), 0);
> + }
> +}
> +
> +static inline void it6263_lvds_set_afe(struct it6263 *it)
> +{
> + regmap_write(it->lvds_regmap, LVDS_REG_3C, 0xaa);
> + regmap_write(it->lvds_regmap, LVDS_REG_3F, 0x02);
> + regmap_write(it->lvds_regmap, LVDS_REG_47, 0xaa);
> + regmap_write(it->lvds_regmap, LVDS_REG_48, 0x02);
> + regmap_write(it->lvds_regmap, LVDS_REG_4F, 0x11);
> +
> + regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_SSC_PCLK_RF,
> + REG_SSC_PCLK_RF);
> + regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, 0x07, 0);
> + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_DESSC_ENB,
> + REG_DESSC_ENB);
> +}
> +
> +static inline void it6263_lvds_sys_cfg(struct it6263 *it)
> +{
> + regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_LVDS_IN_SWAP,
> + it->lvds_link12_swap ? REG_LVDS_IN_SWAP : 0);
> +}
> +
> +static inline void it6263_lvds_config(struct it6263 *it)
> +{
> + it6263_lvds_reset(it);
> + it6263_lvds_set_interface(it);
> + it6263_lvds_set_afe(it);
> + it6263_lvds_sys_cfg(it);
> +}
> +
> +static inline void it6263_hdmi_config(struct it6263 *it)
> +{
> + regmap_write(it->hdmi_regmap, HDMI_REG_SW_RST, HDMI_RST_ALL);
> + regmap_write(it->hdmi_regmap, HDMI_REG_INPUT_MODE, IN_RGB);
> + regmap_write_bits(it->hdmi_regmap, HDMI_REG_GCP, HDMI_COLOR_DEPTH,
> + HDMI_COLOR_DEPTH_24);
> +}
> +
> +static enum drm_connector_status it6263_detect(struct it6263 *it)
> +{
> + unsigned int val;
> +
> + regmap_read(it->hdmi_regmap, HDMI_REG_SYS_STATUS, &val);
> + if (val & HPDETECT)
> + return connector_status_connected;
> + else
> + return connector_status_disconnected;
> +}
> +
> +static enum drm_connector_status
> +it6263_connector_detect(struct drm_connector *connector, bool force)
> +{
> + struct it6263 *it = connector_to_it6263(connector);
> +
> + return it6263_detect(it);
> +}
> +
> +static const struct drm_connector_funcs it6263_connector_funcs = {
> + .detect = it6263_connector_detect,
> + .fill_modes = drm_helper_probe_single_connector_modes,
> + .destroy = drm_connector_cleanup,
> + .reset = drm_atomic_helper_connector_reset,
> + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> +};
> +
> +static int it6263_read_edid(void *data, u8 *buf, unsigned int block, size_t len)
> +{
> + struct it6263 *it = data;
> + struct regmap *regmap = it->hdmi_regmap;
> + unsigned int start = (block % 2) * EDID_LENGTH;
> + unsigned int segment = block >> 1;
> + unsigned int count, val;
> + int ret;
> +
> + regmap_write(regmap, HDMI_REG_DDC_MASTER_CTRL, MASTER_SEL_HOST);
> + regmap_write(regmap, HDMI_REG_DDC_HEADER, DDC_ADDR << 1);
> + regmap_write(regmap, HDMI_REG_DDC_EDIDSEG, segment);
> +
> + while (len) {
> + /* clear DDC FIFO */
> + regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_FIFO_CLR);
> +
> + ret = regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS,
> + val, val & DDC_DONE,
> + 2000, 10000);
> + if (ret) {
> + dev_err(it->dev, "failed to clear DDC FIFO:%d\n", ret);
> + return ret;
> + }
> +
> + count = len > HDMI_DDC_FIFO_BYTES ? HDMI_DDC_FIFO_BYTES : len;
> +
> + /* fire the read command */
> + regmap_write(regmap, HDMI_REG_DDC_REQOFF, start);
> + regmap_write(regmap, HDMI_REG_DDC_REQCOUNT, count);
> + regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_EDID_READ);
> +
> + start += count;
> + len -= count;
> +
> + ret = regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS, val,
> + val & (DDC_DONE | DDC_ERROR),
> + 20000, 250000);
> + if (ret && !(val & DDC_ERROR)) {
> + dev_err(it->dev, "failed to read EDID:%d\n", ret);
> + return ret;
> + }
> +
> + if (val & DDC_ERROR) {
> + dev_err(it->dev, "DDC error\n");
> + return -EIO;
> + }
> +
> + /* cache to buffer */
> + for (; count > 0; count--) {
> + regmap_read(regmap, HDMI_REG_DDC_READFIFO, &val);
> + *(buf++) = val;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static int it6263_connector_get_modes(struct drm_connector *connector)
> +{
> + struct it6263 *it = connector_to_it6263(connector);
> + const struct drm_edid *drm_edid;
> + int count;
> +
> + drm_edid = drm_edid_read_custom(connector, it6263_read_edid, it);
> +
> + drm_edid_connector_update(connector, drm_edid);
> + count = drm_edid_connector_add_modes(connector);
> +
> + drm_edid_free(drm_edid);
> +
> + return count;
> +}
> +
> +static const struct drm_connector_helper_funcs it6263_connector_helper_funcs = {
> + .get_modes = it6263_connector_get_modes,
> +};
> +
> +static int it6263_bridge_atomic_check(struct drm_bridge *bridge,
> + struct drm_bridge_state *bridge_state,
> + struct drm_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state)
> +{
> + struct drm_display_mode *mode = &crtc_state->adjusted_mode;
Use drm_atomic_helper_connector_hdmi_check().
Implement .hdmi_tmds_char_rate_valid(). Also, I think, single and dual
link LVDS have different max clock rates. Please correct me if I'm
wrong.
> +
> + return mode->clock > MAX_PIXEL_CLOCK_KHZ ? -EINVAL : 0;
> +}
> +
> +static void
> +it6263_bridge_atomic_disable(struct drm_bridge *bridge,
> + struct drm_bridge_state *old_bridge_state)
> +{
> + struct it6263 *it = bridge_to_it6263(bridge);
> +
> + regmap_write_bits(it->hdmi_regmap, HDMI_REG_GCP, AVMUTE, AVMUTE);
> + regmap_write(it->hdmi_regmap, HDMI_REG_PKT_GENERAL_CTRL, 0);
> + regmap_write(it->hdmi_regmap, HDMI_REG_AFE_DRV_CTRL,
> + AFE_DRV_RST | AFE_DRV_PWD);
> +}
> +
> +static void
> +it6263_hdmi_avi_infoframe_configure(struct it6263 *it,
> + struct drm_connector *connector,
> + const struct drm_display_mode *mode)
-> .hdmi_write_infoframe() , .hdmi_clear_infoframe().
> +{
> + struct hdmi_avi_infoframe frame;
> + u8 buf[HDMI_INFOFRAME_SIZE(AVI)];
> + int ret;
> +
> + ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
> + if (ret) {
> + dev_err(it->dev, "failed to setup AVI infoframe: %d\n", ret);
> + return;
> + }
> +
> + ret = hdmi_avi_infoframe_pack(&frame, buf, sizeof(buf));
> + if (ret < 0) {
> + dev_err(it->dev, "failed to pack infoframe: %d\n", ret);
> + return;
> + }
> +
> + /* write the first AVI infoframe data byte chunk(DB1-DB5) */
> + ret = regmap_bulk_write(it->hdmi_regmap, HDMI_REG_AVI_DB1,
> + &buf[HDMI_INFOFRAME_HEADER_SIZE],
> + HDMI_AVI_DB_CHUNK1_SIZE);
> + if (ret) {
> + dev_err(it->dev, "failed to write the 1st AVI infoframe data byte chunk: %d\n",
> + ret);
> + return;
> + }
> +
> + /* write the second AVI infoframe data byte chunk(DB6-DB13) */
> + ret = regmap_bulk_write(it->hdmi_regmap, HDMI_REG_AVI_DB6,
> + &buf[HDMI_INFOFRAME_HEADER_SIZE +
> + HDMI_AVI_DB_CHUNK1_SIZE],
> + HDMI_AVI_DB_CHUNK2_SIZE);
> + if (ret) {
> + dev_err(it->dev, "failed to write the 2nd AVI infoframe data byte chunk: %d\n",
> + ret);
> + return;
> + }
> +
> + ret = regmap_write(it->hdmi_regmap, HDMI_REG_AVI_CSUM, buf[3]);
> + if (ret)
> + dev_err(it->dev, "failed to set AVI infoframe checksum: %d\n",
> + ret);
> +}
> +
> +static void
> +it6263_bridge_atomic_enable(struct drm_bridge *bridge,
> + struct drm_bridge_state *old_bridge_state)
> +{
> + struct drm_atomic_state *state = old_bridge_state->base.state;
> + struct it6263 *it = bridge_to_it6263(bridge);
> + const struct drm_crtc_state *crtc_state;
> + struct regmap *regmap = it->hdmi_regmap;
> + const struct drm_display_mode *mode;
> + struct drm_connector *connector;
> + bool is_stable = false;
> + struct drm_crtc *crtc;
> + unsigned int val;
> + bool pclk_high;
> + int i, ret;
> +
> + connector = drm_atomic_get_new_connector_for_encoder(state,
> + bridge->encoder);
> + crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
> + crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
> + mode = &crtc_state->adjusted_mode;
> +
> + regmap_write(regmap, HDMI_REG_HDMI_MODE, TX_HDMI_MODE);
> +
> + it6263_hdmi_avi_infoframe_configure(it, connector, mode);
drm_atomic_helper_connector_hdmi_update_infoframes
> +
> + /* HDMI AFE setup */
> + pclk_high = mode->clock > HIGH_PIXEL_CLOCK_KHZ ? true : false;
> + regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, AFE_DRV_RST);
> + if (pclk_high)
> + regmap_write(regmap, HDMI_REG_AFE_XP_CTRL,
> + AFE_XP_GAINBIT | AFE_XP_RESETB);
> + else
> + regmap_write(regmap, HDMI_REG_AFE_XP_CTRL,
> + AFE_XP_ER0 | AFE_XP_RESETB);
> + regmap_write(regmap, HDMI_REG_AFE_ISW_CTRL, 0x10);
> + if (pclk_high)
> + regmap_write(regmap, HDMI_REG_AFE_IP_CTRL,
> + AFE_IP_GAINBIT | AFE_IP_RESETB);
> + else
> + regmap_write(regmap, HDMI_REG_AFE_IP_CTRL,
> + AFE_IP_ER0 | AFE_IP_RESETB);
> +
> + /* HDMI software video reset */
> + regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, SOFTV_RST);
> + fsleep(1000);
> + regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, 0);
> +
> + /* reconfigure LVDS and retry several times in case video is instable */
> + for (i = 0; i < 3; i++) {
> + ret = regmap_read_poll_timeout(regmap, HDMI_REG_SYS_STATUS, val,
> + val & TXVIDSTABLE,
> + 20000, 500000);
> + if (!ret) {
> + is_stable = true;
> + break;
> + }
> +
> + it6263_lvds_config(it);
> + }
> +
> + if (!is_stable)
> + dev_warn(it->dev, "failed to wait for video stable\n");
> +
> + /* HDMI AFE reset release and power up */
> + regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, 0);
> +
> + regmap_write_bits(regmap, HDMI_REG_GCP, AVMUTE, 0);
> +
> + regmap_write(regmap, HDMI_REG_PKT_GENERAL_CTRL, ENABLE_PKT | REPEAT_PKT);
> +}
> +
> +static enum drm_mode_status
> +it6263_bridge_mode_valid(struct drm_bridge *bridge,
> + const struct drm_display_info *info,
> + const struct drm_display_mode *mode)
> +{
> + return mode->clock > MAX_PIXEL_CLOCK_KHZ ? MODE_CLOCK_HIGH : MODE_OK;
rate = drm_hdmi_compute_mode_clock(mode, 8, HDMI_COLORSPACE_RGB);
return bridge->funcs->hdmi_tmds_char_rate_valid(bridge, mode, rate);
> +}
> +
> +static int it6263_bridge_attach(struct drm_bridge *bridge,
> + enum drm_bridge_attach_flags flags)
> +{
> + struct it6263 *it = bridge_to_it6263(bridge);
> + int ret;
> +
> + ret = drm_bridge_attach(bridge->encoder, it->next_bridge, bridge,
> + flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
> + if (ret < 0)
> + return ret;
> +
> + if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
> + return 0;
> +
> + it->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
> + DRM_CONNECTOR_POLL_DISCONNECT;
> +
Please strongly consider dropping this and using drm_bridge_connector in
the host driver.
> + ret = drm_connector_init(bridge->dev, &it->connector,
> + &it6263_connector_funcs,
> + DRM_MODE_CONNECTOR_HDMIA);
> + if (ret)
> + return ret;
> +
> + drm_connector_helper_add(&it->connector,
> + &it6263_connector_helper_funcs);
> + drm_connector_attach_encoder(&it->connector, bridge->encoder);
> +
> + return 0;
> +}
> +
> +static enum drm_connector_status it6263_bridge_detect(struct drm_bridge *bridge)
> +{
> + struct it6263 *it = bridge_to_it6263(bridge);
> +
> + return it6263_detect(it);
> +}
> +
> +static const struct drm_edid *
> +it6263_bridge_edid_read(struct drm_bridge *bridge,
> + struct drm_connector *connector)
> +{
> + struct it6263 *it = bridge_to_it6263(bridge);
> +
> + return drm_edid_read_custom(connector, it6263_read_edid, it);
> +}
> +
> +static u32 *
> +it6263_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
> + struct drm_bridge_state *bridge_state,
> + struct drm_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state,
> + u32 output_fmt,
> + unsigned int *num_input_fmts)
> +{
> + struct it6263 *it = bridge_to_it6263(bridge);
> + u32 *input_fmts;
> +
> + *num_input_fmts = 0;
> +
> + if (it->lvds_link_num_dlanes == 3)
> + return NULL;
> +
> + input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
> + if (!input_fmts)
> + return NULL;
> +
> + input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA;
> + *num_input_fmts = 1;
> +
> + return input_fmts;
> +}
> +
> +static const struct drm_bridge_funcs it6263_bridge_funcs = {
> + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
> + .atomic_reset = drm_atomic_helper_bridge_reset,
> + .attach = it6263_bridge_attach,
> + .mode_valid = it6263_bridge_mode_valid,
> + .atomic_disable = it6263_bridge_atomic_disable,
> + .atomic_enable = it6263_bridge_atomic_enable,
> + .atomic_check = it6263_bridge_atomic_check,
> + .detect = it6263_bridge_detect,
> + .edid_read = it6263_bridge_edid_read,
> + .atomic_get_input_bus_fmts = it6263_bridge_atomic_get_input_bus_fmts,
> +};
> +
> +static int it6263_probe(struct i2c_client *client)
> +{
> + struct device *dev = &client->dev;
> + struct it6263 *it;
> + int ret;
> +
> + it = devm_kzalloc(dev, sizeof(*it), GFP_KERNEL);
> + if (!it)
> + return -ENOMEM;
> +
> + it->dev = dev;
> + it->hdmi_i2c = client;
> +
> + it->hdmi_regmap = devm_regmap_init_i2c(client,
> + &it6263_hdmi_regmap_config);
> + if (IS_ERR(it->hdmi_regmap))
> + return dev_err_probe(dev, PTR_ERR(it->hdmi_regmap),
> + "failed to init I2C regmap for HDMI\n");
> +
> + it->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
> + if (IS_ERR(it->reset_gpio))
> + return dev_err_probe(dev, PTR_ERR(it->reset_gpio),
> + "failed to get reset gpio\n");
> +
> + ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(it6263_supplies),
> + it6263_supplies);
> + if (ret)
> + return dev_err_probe(dev, ret, "failed to get power supplies\n");
> +
> + ret = it6263_parse_dt(it);
> + if (ret)
> + return ret;
> +
> + it6263_hw_reset(it);
> +
> + ret = it6263_lvds_set_i2c_addr(it);
> + if (ret)
> + return dev_err_probe(dev, ret, "failed to set I2C addr\n");
> +
> + it->lvds_i2c = devm_i2c_new_dummy_device(dev, client->adapter,
> + LVDS_INPUT_CTRL_I2C_ADDR);
> + if (IS_ERR(it->lvds_i2c))
> + dev_err_probe(it->dev, PTR_ERR(it->lvds_i2c),
> + "failed to allocate I2C device for LVDS\n");
> +
> + it->lvds_regmap = devm_regmap_init_i2c(it->lvds_i2c,
> + &it6263_lvds_regmap_config);
> + if (IS_ERR(it->lvds_regmap))
> + return dev_err_probe(dev, PTR_ERR(it->lvds_regmap),
> + "failed to init I2C regmap for LVDS\n");
> +
> + it6263_lvds_config(it);
> + it6263_hdmi_config(it);
> +
> + i2c_set_clientdata(client, it);
> +
> + it->bridge.funcs = &it6263_bridge_funcs;
> + it->bridge.of_node = dev->of_node;
> + it->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT;
| DRM_BRIDGE_OP_HDMI
BTW: No HPD IRQ support?
> + it->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
> + drm_bridge_add(&it->bridge);
devm_drm_bridge_add()
> +
> + return 0;
> +}
> +
> +static void it6263_remove(struct i2c_client *client)
> +{
> + struct it6263 *it = i2c_get_clientdata(client);
> +
> + drm_bridge_remove(&it->bridge);
Remove, it becomes unused with the devm_ function.
> +}
> +
> +static const struct of_device_id it6263_of_match[] = {
> + { .compatible = "ite,it6263", },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, it6263_of_match);
> +
> +static const struct i2c_device_id it6263_i2c_ids[] = {
> + { "it6263", 0 },
> + { }
> +};
> +MODULE_DEVICE_TABLE(i2c, it6263_i2c_ids);
> +
> +static struct i2c_driver it6263_driver = {
> + .probe = it6263_probe,
> + .remove = it6263_remove,
> + .driver = {
> + .name = "it6263",
> + .of_match_table = it6263_of_match,
> + },
> + .id_table = it6263_i2c_ids,
> +};
> +module_i2c_driver(it6263_driver);
> +
> +MODULE_DESCRIPTION("ITE Tech. Inc. IT6263 LVDS/HDMI bridge");
> +MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>");
> +MODULE_LICENSE("GPL");
> --
> 2.34.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 3/9] drm/bridge: fsl-ldb: Get the next non-panel bridge
2024-10-12 7:35 ` [PATCH v2 3/9] drm/bridge: fsl-ldb: Get the next non-panel bridge Liu Ying
@ 2024-10-12 8:48 ` Dmitry Baryshkov
0 siblings, 0 replies; 49+ messages in thread
From: Dmitry Baryshkov @ 2024-10-12 8:48 UTC (permalink / raw)
To: Liu Ying
Cc: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel,
andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
arnd, nfraprado, o.rempel, y.moog, marex, isaac.scott,
biju.das.jz
On Sat, Oct 12, 2024 at 03:35:37PM +0800, Liu Ying wrote:
> The next bridge in bridge chain could be a panel bridge or a non-panel
> bridge. Use devm_drm_of_get_bridge() to replace the combination
> function calls of of_drm_find_panel() and devm_drm_panel_bridge_add()
> to get either a panel bridge or a non-panel bridge, instead of getting
> a panel bridge only.
>
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> ---
> v2:
> * No change.
>
> drivers/gpu/drm/bridge/fsl-ldb.c | 31 +++++++++++--------------------
> 1 file changed, 11 insertions(+), 20 deletions(-)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-12 8:30 ` Dmitry Baryshkov
@ 2024-10-12 9:14 ` Liu Ying
2024-10-13 23:45 ` Dmitry Baryshkov
0 siblings, 1 reply; 49+ messages in thread
From: Liu Ying @ 2024-10-12 9:14 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel,
andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
arnd, nfraprado, o.rempel, y.moog, marex, isaac.scott,
biju.das.jz
On 10/12/2024, Dmitry Baryshkov wrote:
> On Sat, Oct 12, 2024 at 03:35:39PM +0800, Liu Ying wrote:
>> Document ITE IT6263 LVDS to HDMI converter.
>>
>> Product link:
>> https://www.ite.com.tw/en/product/cate1/IT6263
>>
>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
>> ---
>> v2:
>> * Document number of LVDS link data lanes. (Biju)
>> * Simplify ports property by dropping "oneOf". (Rob)
>>
>> .../bindings/display/bridge/ite,it6263.yaml | 276 ++++++++++++++++++
>> 1 file changed, 276 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
>> new file mode 100644
>> index 000000000000..bc2bbec07623
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
>> @@ -0,0 +1,276 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/display/bridge/ite,it6263.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: ITE IT6263 LVDS to HDMI converter
>> +
>> +maintainers:
>> + - Liu Ying <victor.liu@nxp.com>
>> +
>> +description: |
>> + The IT6263 is a high-performance single-chip De-SSC(De-Spread Spectrum) LVDS
>> + to HDMI converter. Combined with LVDS receiver and HDMI 1.4a transmitter,
>> + the IT6263 supports LVDS input and HDMI 1.4 output by conversion function.
>> + The built-in LVDS receiver can support single-link and dual-link LVDS inputs,
>> + and the built-in HDMI transmitter is fully compliant with HDMI 1.4a/3D, HDCP
>> + 1.2 and backward compatible with DVI 1.0 specification.
>> +
>> + The IT6263 also encodes and transmits up to 8 channels of I2S digital audio,
>> + with sampling rate up to 192KHz and sample size up to 24 bits. In addition,
>> + an S/PDIF input port takes in compressed audio of up to 192KHz frame rate.
>> +
>> + The newly supported High-Bit Rate(HBR) audio by HDMI specifications v1.3 is
>> + provided by the IT6263 in two interfaces: the four I2S input ports or the
>> + S/PDIF input port. With both interfaces the highest possible HBR frame rate
>> + is supported at up to 768KHz.
>> +
>> +properties:
>
> No LVDS data-mapping support?
It is enough to document number of LVDS link data lanes
because OS should be able to determine the data-mapping
by looking at the number and the data-mapping capability
of the other side of the LVDS link.
>
>> + compatible:
>> + const: ite,it6263
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + maxItems: 1
>> + description: audio master clock
>> +
>> + clock-names:
>> + const: mclk
>> +
>> + reset-gpios:
>> + maxItems: 1
>> +
>> + ivdd-supply:
>> + description: 1.8V digital logic power
>> +
>> + ovdd-supply:
>> + description: 3.3V I/O pin power
>> +
>> + txavcc18-supply:
>> + description: 1.8V HDMI analog frontend power
>> +
>> + txavcc33-supply:
>> + description: 3.3V HDMI analog frontend power
>> +
>> + pvcc1-supply:
>> + description: 1.8V HDMI frontend core PLL power
>> +
>> + pvcc2-supply:
>> + description: 1.8V HDMI frontend filter PLL power
>> +
>> + avcc-supply:
>> + description: 3.3V LVDS frontend power
>> +
>> + anvdd-supply:
>> + description: 1.8V LVDS frontend analog power
>> +
>> + apvdd-supply:
>> + description: 1.8V LVDS frontend PLL power
>> +
>> + "#sound-dai-cells":
>> + const: 0
>> +
>> + ite,lvds-link-num-data-lanes:
>> + $ref: /schemas/types.yaml#/definitions/uint8
>> + enum: [3, 4, 5]
>> + description: number of data lanes per LVDS link
>
> Please use data-lanes property inside the OF graph.
In both port@0 and port@1?
>
>> +
>> + ite,i2s-audio-fifo-sources:
>> + $ref: /schemas/types.yaml#/definitions/uint32-array
>> + minItems: 1
>> + maxItems: 4
>> + items:
>> + enum: [0, 1, 2, 3]
>> + description:
>> + Each array element indicates the pin number of an I2S serial data input
>> + line which is connected to an audio FIFO, from audio FIFO0 to FIFO3.
>
> What does that mean from the board point of view? Routed audio links for
> the multichannel audio?
Yes, also for single channel audio.
>
>> +
>> + ite,rl-channel-swap-audio-sources:
>> + $ref: /schemas/types.yaml#/definitions/uint32-array
>> + minItems: 1
>> + maxItems: 4
>> + uniqueItems: true
>> + items:
>> + enum: [0, 1, 2, 3]
>> + description:
>> + Each array element indicates an audio source whose right channel and left
>> + channel are swapped by this converter. For I2S, the element is the pin
>> + number of an I2S serial data input line. For S/PDIF, the element is always
>> + 0.
>
> Why?
Because this converter has the capability to swap right channel
and left channel and S/PDIF always uses audio source0.
>
>> +
>> + ports:
>> + $ref: /schemas/graph.yaml#/properties/ports
>> +
>> + properties:
>> + port@0:
>> + $ref: /schemas/graph.yaml#/$defs/port-base
>> + unevaluatedProperties: false
>> + description:
>> + The first LVDS input link.
>> + In dual-link LVDS mode, this link works together with the second LVDS
>> + input link, and one link receives odd pixels while the other receives
>> + even pixels. Specify the pixels with one of the dual-lvds-odd-pixels
>> + and dual-lvds-even-pixels properties when and only when dual-link LVDS
>> + mode is used.
>> +
>> + properties:
>> + dual-lvds-odd-pixels:
>> + type: boolean
>> + description: the first sink port for odd pixels
>> +
>> + dual-lvds-even-pixels:
>> + type: boolean
>> + description: the first sink port for even pixels
>> +
>> + port@1:
>> + $ref: /schemas/graph.yaml#/$defs/port-base
>> + unevaluatedProperties: false
>> + description: the second LVDS input link
>> +
>> + properties:
>> + dual-lvds-even-pixels:
>> + type: boolean
>> + description: the second sink port for even pixels
>> +
>> + dual-lvds-odd-pixels:
>> + type: boolean
>> + description: the second sink port for odd pixels
>> +
>> + oneOf:
>> + - required: [dual-lvds-even-pixels]
>> + - required: [dual-lvds-odd-pixels]
>
> This still allows one to specify that both ports provide odd pixels. Is
> that expected? Also why do you need two properties which specify the
> same option.
No, that is not expected. Description for port@0 already mentions
one link receives odd pixels while the other receives even pixels.
Two options are supported for dual-link LVDS, not the same option:
1) LVDS link1(port@0) gets odd pixels
and
LVDS link2(port@1) gets even pixels.
2) LVDS link1(port@0) gets even pixels
and
LVDS link2(port@1) gets odd pixels.
That's the reason why each port needs two properties to define
odd/even pixels.
>
> My suggestion would be to add a single root-level property which
> specifies which port provides even pixel data.
That won't work. The LVDS source side expects the ports of
the sink side specify dual-lvds-{odd,even}-pixels properties.
>
>> +
>> + port@2:
>> + $ref: /schemas/graph.yaml#/properties/port
>> + description: video port for the HDMI output
>> +
>> + port@3:
>> + $ref: /schemas/graph.yaml#/properties/port
>> + description: sound input port
>> +
>> + required:
>> + - port@0
>> + - port@2
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - ivdd-supply
>> + - ovdd-supply
>> + - txavcc18-supply
>> + - txavcc33-supply
>> + - pvcc1-supply
>> + - pvcc2-supply
>> + - avcc-supply
>> + - anvdd-supply
>> + - apvdd-supply
>> + - ite,lvds-link-num-data-lanes
>> + - ports
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + /* single-link LVDS input */
>> + #include <dt-bindings/gpio/gpio.h>
>> +
>> + i2c {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + hdmi@4c {
>> + compatible = "ite,it6263";
>> + reg = <0x4c>;
>> + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
>> + ivdd-supply = <®_buck5>;
>> + ovdd-supply = <®_vext_3v3>;
>> + txavcc18-supply = <®_buck5>;
>> + txavcc33-supply = <®_vext_3v3>;
>> + pvcc1-supply = <®_buck5>;
>> + pvcc2-supply = <®_buck5>;
>> + avcc-supply = <®_vext_3v3>;
>> + anvdd-supply = <®_buck5>;
>> + apvdd-supply = <®_buck5>;
>> + ite,lvds-link-num-data-lanes = /bits/ 8 <4>;
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> +
>> + it6263_lvds_link1: endpoint {
>> + remote-endpoint = <&ldb_lvds_ch0>;
>> + };
>> + };
>> +
>> + port@2 {
>> + reg = <2>;
>> +
>> + it6263_out: endpoint {
>> + remote-endpoint = <&hdmi_in>;
>> + };
>> + };
>> + };
>> + };
>> + };
>> +
>> + - |
>> + /* dual-link LVDS input */
>> + #include <dt-bindings/gpio/gpio.h>
>> +
>> + i2c {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + hdmi@4c {
>> + compatible = "ite,it6263";
>> + reg = <0x4c>;
>> + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
>> + ivdd-supply = <®_buck5>;
>> + ovdd-supply = <®_vext_3v3>;
>> + txavcc18-supply = <®_buck5>;
>> + txavcc33-supply = <®_vext_3v3>;
>> + pvcc1-supply = <®_buck5>;
>> + pvcc2-supply = <®_buck5>;
>> + avcc-supply = <®_vext_3v3>;
>> + anvdd-supply = <®_buck5>;
>> + apvdd-supply = <®_buck5>;
>> + ite,lvds-link-num-data-lanes = /bits/ 8 <4>;
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + dual-lvds-odd-pixels;
>> +
>> + it6263_lvds_link1_dual: endpoint {
>> + remote-endpoint = <&ldb_lvds_ch0>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + dual-lvds-even-pixels;
>> +
>> + it6263_lvds_link2_dual: endpoint {
>> + remote-endpoint = <&ldb_lvds_ch1>;
>> + };
>> + };
>> +
>> + port@2 {
>> + reg = <2>;
>> +
>> + it6263_out_dual: endpoint {
>> + remote-endpoint = <&hdmi_in>;
>> + };
>> + };
>> + };
>> + };
>> + };
>> --
>> 2.34.1
>>
>
--
Regards,
Liu Ying
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-12 8:45 ` Dmitry Baryshkov
@ 2024-10-12 10:01 ` Liu Ying
2024-10-13 10:48 ` Biju Das
2024-10-13 23:58 ` Dmitry Baryshkov
2024-10-13 10:27 ` Biju Das
1 sibling, 2 replies; 49+ messages in thread
From: Liu Ying @ 2024-10-12 10:01 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel,
andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
arnd, nfraprado, o.rempel, y.moog, marex, isaac.scott,
biju.das.jz
On 10/12/2024, Dmitry Baryshkov wrote:
> On Sat, Oct 12, 2024 at 03:35:40PM +0800, Liu Ying wrote:
>> Add basic HDMI video output support. Currently, only RGB888 output
>> pixel format is supported. At the LVDS input side, the driver
>> supports single LVDS link and dual LVDS links with "jeida-24" LVDS
>> mapping.
>>
>> Product link:
>> https://www.ite.com.tw/en/product/cate1/IT6263
>>
>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
>> ---
>> v2:
>> * Add AVI inforframe support. (Maxime)
>
> Maxime asked to wire up the HDMI Connector framework. I have pushed the
> patch that converts lt9611.c driver. Please implement similar changes in
> your driver.
Hmm, didn't fully get the meaning of "the new HDMI bridge infrastructure"
maxime asked. Ok, will take a look at lt9611.c.
>
>> * Add DRM_MODE_CONNECTOR_HDMIA. (Biju)
>> * Rename it6263_reset() to it6263_hw_reset(). (Biju)
>> * Check number of LVDS link data lanes. (Biju)
>>
>> drivers/gpu/drm/bridge/Kconfig | 8 +
>> drivers/gpu/drm/bridge/Makefile | 1 +
>> drivers/gpu/drm/bridge/ite-it6263.c | 919 ++++++++++++++++++++++++++++
>> 3 files changed, 928 insertions(+)
>> create mode 100644 drivers/gpu/drm/bridge/ite-it6263.c
>>
>> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
>> index 3eb955333c80..93f99682a090 100644
>> --- a/drivers/gpu/drm/bridge/Kconfig
>> +++ b/drivers/gpu/drm/bridge/Kconfig
>> @@ -90,6 +90,14 @@ config DRM_FSL_LDB
>> help
>> Support for i.MX8MP DPI-to-LVDS on-SoC encoder.
>>
>> +config DRM_ITE_IT6263
>> + tristate "ITE IT6263 LVDS/HDMI bridge"
>> + depends on OF
>> + select DRM_KMS_HELPER
>> + select REGMAP_I2C
>> + help
>> + ITE IT6263 LVDS to HDMI bridge chip driver.
>> +
>> config DRM_ITE_IT6505
>> tristate "ITE IT6505 DisplayPort bridge"
>> depends on OF
>> diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
>> index 7df87b582dca..f3776dd473fd 100644
>> --- a/drivers/gpu/drm/bridge/Makefile
>> +++ b/drivers/gpu/drm/bridge/Makefile
>> @@ -6,6 +6,7 @@ obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
>> obj-$(CONFIG_DRM_CROS_EC_ANX7688) += cros-ec-anx7688.o
>> obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
>> obj-$(CONFIG_DRM_FSL_LDB) += fsl-ldb.o
>> +obj-$(CONFIG_DRM_ITE_IT6263) += ite-it6263.o
>> obj-$(CONFIG_DRM_ITE_IT6505) += ite-it6505.o
>> obj-$(CONFIG_DRM_LONTIUM_LT8912B) += lontium-lt8912b.o
>> obj-$(CONFIG_DRM_LONTIUM_LT9211) += lontium-lt9211.o
>> diff --git a/drivers/gpu/drm/bridge/ite-it6263.c b/drivers/gpu/drm/bridge/ite-it6263.c
>> new file mode 100644
>> index 000000000000..9b3318792f15
>> --- /dev/null
>> +++ b/drivers/gpu/drm/bridge/ite-it6263.c
>> @@ -0,0 +1,919 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright 2024 NXP
>> + */
>> +
>> +#include <linux/bitfield.h>
>> +#include <linux/bits.h>
>> +#include <linux/delay.h>
>> +#include <linux/gpio/consumer.h>
>> +#include <linux/hdmi.h>
>> +#include <linux/i2c.h>
>> +#include <linux/media-bus-format.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/regmap.h>
>> +#include <linux/regulator/consumer.h>
>> +
>> +#include <drm/drm_atomic.h>
>> +#include <drm/drm_atomic_helper.h>
>> +#include <drm/drm_atomic_state_helper.h>
>> +#include <drm/drm_bridge.h>
>> +#include <drm/drm_connector.h>
>> +#include <drm/drm_crtc.h>
>> +#include <drm/drm_edid.h>
>> +#include <drm/drm_of.h>
>> +#include <drm/drm_probe_helper.h>
>> +
>> +/* -----------------------------------------------------------------------------
>> + * LVDS registers
>> + */
>> +
>> +/* LVDS software reset registers */
>> +#define LVDS_REG_05 0x05
>> +#define REG_SOFT_P_RST BIT(1)
>> +
>> +/* LVDS system configuration registers */
>> +/* 0x0b */
>> +#define LVDS_REG_0B 0x0b
>> +#define REG_SSC_PCLK_RF BIT(0)
>> +#define REG_LVDS_IN_SWAP BIT(1)
>> +
>> +/* LVDS test pattern gen control registers */
>> +/* 0x2c */
>> +#define LVDS_REG_2C 0x2c
>> +#define REG_COL_DEP GENMASK(1, 0)
>> +#define BIT8 FIELD_PREP(REG_COL_DEP, 2)
>> +#define OUT_MAP BIT(4)
>> +#define JEIDA 0
>> +#define REG_DESSC_ENB BIT(6)
>> +#define DMODE BIT(7)
>> +#define DISO BIT(7)
>> +#define SISO 0
>> +
>> +#define LVDS_REG_3C 0x3c
>> +#define LVDS_REG_3F 0x3f
>> +#define LVDS_REG_47 0x47
>> +#define LVDS_REG_48 0x48
>> +#define LVDS_REG_4F 0x4f
>> +#define LVDS_REG_52 0x52
>> +
>> +/* -----------------------------------------------------------------------------
>> + * HDMI registers are separated into three banks:
>> + * 1) HDMI register common bank: 0x00 ~ 0x2f
>> + */
>> +
>> +/* HDMI genernal registers */
>> +#define HDMI_REG_SW_RST 0x04
>> +#define SOFTREF_RST BIT(5)
>> +#define SOFTA_RST BIT(4)
>> +#define SOFTV_RST BIT(3)
>> +#define AUD_RST BIT(2)
>> +#define HDCP_RST BIT(0)
>> +#define HDMI_RST_ALL (SOFTREF_RST | SOFTA_RST | SOFTV_RST | \
>> + AUD_RST | HDCP_RST)
>> +
>> +#define HDMI_REG_SYS_STATUS 0x0e
>> +#define HPDETECT BIT(6)
>> +#define TXVIDSTABLE BIT(4)
>> +
>> +#define HDMI_REG_BANK_CTRL 0x0f
>> +#define REG_BANK_SEL BIT(0)
>> +
>> +/* HDMI System DDC control registers */
>> +#define HDMI_REG_DDC_MASTER_CTRL 0x10
>> +#define MASTER_SEL_HOST BIT(0)
>> +
>> +#define HDMI_REG_DDC_HEADER 0x11
>> +
>> +#define HDMI_REG_DDC_REQOFF 0x12
>> +#define HDMI_REG_DDC_REQCOUNT 0x13
>> +#define HDMI_REG_DDC_EDIDSEG 0x14
>> +
>> +#define HDMI_REG_DDC_CMD 0x15
>> +#define DDC_CMD_EDID_READ 0x3
>> +#define DDC_CMD_FIFO_CLR 0x9
>> +
>> +#define HDMI_REG_DDC_STATUS 0x16
>> +#define DDC_DONE BIT(7)
>> +#define DDC_NOACK BIT(5)
>> +#define DDC_WAITBUS BIT(4)
>> +#define DDC_ARBILOSE BIT(3)
>> +#define DDC_ERROR (DDC_NOACK | DDC_WAITBUS | DDC_ARBILOSE)
>> +
>> +#define HDMI_DDC_FIFO_BYTES 32
>> +#define HDMI_REG_DDC_READFIFO 0x17
>> +#define HDMI_REG_LVDS_PORT 0x1d /* LVDS input control I2C addr */
>> +#define HDMI_REG_LVDS_PORT_EN 0x1e
>> +#define LVDS_INPUT_CTRL_I2C_ADDR 0x33
>> +
>> +/* -----------------------------------------------------------------------------
>> + * 2) HDMI register bank0: 0x30 ~ 0xff
>> + */
>> +
>> +/* HDMI AFE registers */
>> +#define HDMI_REG_AFE_DRV_CTRL 0x61
>> +#define AFE_DRV_PWD BIT(5)
>> +#define AFE_DRV_RST BIT(4)
>> +
>> +#define HDMI_REG_AFE_XP_CTRL 0x62
>> +#define AFE_XP_GAINBIT BIT(7)
>> +#define AFE_XP_ER0 BIT(4)
>> +#define AFE_XP_RESETB BIT(3)
>> +
>> +#define HDMI_REG_AFE_ISW_CTRL 0x63
>> +
>> +#define HDMI_REG_AFE_IP_CTRL 0x64
>> +#define AFE_IP_GAINBIT BIT(7)
>> +#define AFE_IP_ER0 BIT(3)
>> +#define AFE_IP_RESETB BIT(2)
>> +
>> +/* HDMI input data format registers */
>> +#define HDMI_REG_INPUT_MODE 0x70
>> +#define IN_RGB 0x00
>> +
>> +/* HDMI general control registers */
>> +#define HDMI_REG_HDMI_MODE 0xc0
>> +#define TX_HDMI_MODE BIT(0)
>> +
>> +#define HDMI_REG_GCP 0xc1
>> +#define AVMUTE BIT(0)
>> +#define HDMI_COLOR_DEPTH GENMASK(6, 4)
>> +#define HDMI_COLOR_DEPTH_24 FIELD_PREP(HDMI_COLOR_DEPTH, 4)
>> +
>> +#define HDMI_REG_PKT_GENERAL_CTRL 0xc6
>> +#define ENABLE_PKT BIT(0)
>> +#define REPEAT_PKT BIT(1)
>> +
>> +/* -----------------------------------------------------------------------------
>> + * 3) HDMI register bank1: 0x130 ~ 0x1ff (HDMI packet registers)
>> + */
>> +
>> +/* AVI packet registers */
>> +#define HDMI_REG_AVI_DB1 0x158
>> +#define HDMI_REG_AVI_DB2 0x159
>> +#define HDMI_REG_AVI_DB3 0x15a
>> +#define HDMI_REG_AVI_DB4 0x15b
>> +#define HDMI_REG_AVI_DB5 0x15c
>> +#define HDMI_REG_AVI_CSUM 0x15d
>> +#define HDMI_REG_AVI_DB6 0x15e
>> +#define HDMI_REG_AVI_DB7 0x15f
>> +#define HDMI_REG_AVI_DB8 0x160
>> +#define HDMI_REG_AVI_DB9 0x161
>> +#define HDMI_REG_AVI_DB10 0x162
>> +#define HDMI_REG_AVI_DB11 0x163
>> +#define HDMI_REG_AVI_DB12 0x164
>> +#define HDMI_REG_AVI_DB13 0x165
>> +
>> +#define HDMI_AVI_DB_CHUNK1_SIZE (HDMI_REG_AVI_DB5 - HDMI_REG_AVI_DB1 + 1)
>> +#define HDMI_AVI_DB_CHUNK2_SIZE (HDMI_REG_AVI_DB13 - HDMI_REG_AVI_DB6 + 1)
>> +
>> +#define MAX_PIXEL_CLOCK_KHZ 150000
>> +#define HIGH_PIXEL_CLOCK_KHZ 80000
>> +
>> +struct it6263 {
>> + struct device *dev;
>> + struct i2c_client *hdmi_i2c;
>> + struct i2c_client *lvds_i2c;
>> + struct regmap *hdmi_regmap;
>> + struct regmap *lvds_regmap;
>> + struct drm_bridge bridge;
>> + struct drm_bridge *next_bridge;
>> + struct drm_connector connector;
>> + struct gpio_desc *reset_gpio;
>> + u8 lvds_link_num_dlanes;
>> + bool lvds_dual_link;
>> + bool lvds_link12_swap;
>> +};
>> +
>> +static inline struct it6263 *bridge_to_it6263(struct drm_bridge *bridge)
>> +{
>> + return container_of(bridge, struct it6263, bridge);
>> +}
>> +
>> +static inline struct it6263 *connector_to_it6263(struct drm_connector *conn)
>> +{
>> + return container_of(conn, struct it6263, connector);
>> +}
>> +
>> +static bool it6263_hdmi_writeable_reg(struct device *dev, unsigned int reg)
>> +{
>> + switch (reg) {
>> + case HDMI_REG_SW_RST:
>> + case HDMI_REG_BANK_CTRL:
>> + case HDMI_REG_DDC_MASTER_CTRL:
>> + case HDMI_REG_DDC_HEADER:
>> + case HDMI_REG_DDC_REQOFF:
>> + case HDMI_REG_DDC_REQCOUNT:
>> + case HDMI_REG_DDC_EDIDSEG:
>> + case HDMI_REG_DDC_CMD:
>> + case HDMI_REG_LVDS_PORT:
>> + case HDMI_REG_LVDS_PORT_EN:
>> + case HDMI_REG_AFE_DRV_CTRL:
>> + case HDMI_REG_AFE_XP_CTRL:
>> + case HDMI_REG_AFE_ISW_CTRL:
>> + case HDMI_REG_AFE_IP_CTRL:
>> + case HDMI_REG_INPUT_MODE:
>> + case HDMI_REG_HDMI_MODE:
>> + case HDMI_REG_GCP:
>> + case HDMI_REG_PKT_GENERAL_CTRL:
>> + case HDMI_REG_AVI_DB1:
>> + case HDMI_REG_AVI_DB2:
>> + case HDMI_REG_AVI_DB3:
>> + case HDMI_REG_AVI_DB4:
>> + case HDMI_REG_AVI_DB5:
>> + case HDMI_REG_AVI_CSUM:
>> + case HDMI_REG_AVI_DB6:
>> + case HDMI_REG_AVI_DB7:
>> + case HDMI_REG_AVI_DB8:
>> + case HDMI_REG_AVI_DB9:
>> + case HDMI_REG_AVI_DB10:
>> + case HDMI_REG_AVI_DB11:
>> + case HDMI_REG_AVI_DB12:
>> + case HDMI_REG_AVI_DB13:
>> + return true;
>> + default:
>> + return false;
>> + }
>> +}
>> +
>> +static bool it6263_hdmi_readable_reg(struct device *dev, unsigned int reg)
>> +{
>> + if (it6263_hdmi_writeable_reg(dev, reg))
>> + return true;
>> +
>> + switch (reg) {
>> + case HDMI_REG_SYS_STATUS:
>> + case HDMI_REG_DDC_STATUS:
>> + case HDMI_REG_DDC_READFIFO:
>> + return true;
>> + default:
>> + return false;
>> + }
>> +}
>> +
>> +static bool it6263_hdmi_volatile_reg(struct device *dev, unsigned int reg)
>> +{
>> + switch (reg) {
>> + case HDMI_REG_SW_RST:
>> + case HDMI_REG_SYS_STATUS:
>> + case HDMI_REG_DDC_STATUS:
>> + case HDMI_REG_DDC_READFIFO:
>> + return true;
>> + default:
>> + return false;
>> + }
>> +}
>> +
>> +static const struct regmap_range_cfg it6263_hdmi_range_cfg = {
>> + .range_min = 0x00,
>> + .range_max = HDMI_REG_AVI_DB13,
>> + .selector_reg = HDMI_REG_BANK_CTRL,
>> + .selector_mask = REG_BANK_SEL,
>> + .selector_shift = 0,
>> + .window_start = 0x00,
>> + .window_len = 0x100,
>> +};
>> +
>> +static const struct regmap_config it6263_hdmi_regmap_config = {
>> + .name = "it6263-hdmi",
>> + .reg_bits = 8,
>> + .val_bits = 8,
>> + .writeable_reg = it6263_hdmi_writeable_reg,
>> + .readable_reg = it6263_hdmi_readable_reg,
>> + .volatile_reg = it6263_hdmi_volatile_reg,
>> + .max_register = HDMI_REG_AVI_DB13,
>> + .ranges = &it6263_hdmi_range_cfg,
>> + .num_ranges = 1,
>> + .cache_type = REGCACHE_MAPLE,
>> +};
>> +
>> +static bool it6263_lvds_writeable_reg(struct device *dev, unsigned int reg)
>> +{
>> + switch (reg) {
>> + case LVDS_REG_05:
>> + case LVDS_REG_0B:
>> + case LVDS_REG_2C:
>> + case LVDS_REG_3C:
>> + case LVDS_REG_3F:
>> + case LVDS_REG_47:
>> + case LVDS_REG_48:
>> + case LVDS_REG_4F:
>> + case LVDS_REG_52:
>> + return true;
>> + default:
>> + return false;
>> + }
>> +}
>> +
>> +static bool it6263_lvds_readable_reg(struct device *dev, unsigned int reg)
>> +{
>> + return it6263_lvds_writeable_reg(dev, reg);
>> +}
>> +
>> +static bool it6263_lvds_volatile_reg(struct device *dev, unsigned int reg)
>> +{
>> + return reg == LVDS_REG_05;
>> +}
>> +
>> +static const struct regmap_config it6263_lvds_regmap_config = {
>> + .name = "it6263-lvds",
>> + .reg_bits = 8,
>> + .val_bits = 8,
>> + .writeable_reg = it6263_lvds_writeable_reg,
>> + .readable_reg = it6263_lvds_readable_reg,
>> + .volatile_reg = it6263_lvds_volatile_reg,
>> + .max_register = LVDS_REG_52,
>> + .cache_type = REGCACHE_MAPLE,
>> +};
>> +
>> +static const char * const it6263_supplies[] = {
>> + "ivdd", "ovdd", "txavcc18", "txavcc33", "pvcc1", "pvcc2",
>> + "avcc", "anvdd", "apvdd"
>> +};
>> +
>> +static int it6263_parse_dt(struct it6263 *it)
>> +{
>> + struct device *dev = it->dev;
>> + struct device_node *port0, *port1;
>> + int ret;
>> +
>> + ret = of_property_read_u8(dev->of_node, "ite,lvds-link-num-data-lanes",
>> + &it->lvds_link_num_dlanes);
>> + if (ret) {
>> + dev_err(dev, "failed to get LVDS link number of data lanes: %d\n",
>> + ret);
>> + return ret;
>> + }
>> +
>> + it->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0);
>> + if (IS_ERR(it->next_bridge))
>> + return dev_err_probe(dev, PTR_ERR(it->next_bridge),
>> + "failed to get next bridge\n");
>> +
>> + port0 = of_graph_get_port_by_id(dev->of_node, 0);
>> + port1 = of_graph_get_port_by_id(dev->of_node, 1);
>> + if (port0 && port1) {
>> + if (of_property_read_bool(port0, "dual-lvds-even-pixels") &&
>> + of_property_read_bool(port1, "dual-lvds-odd-pixels")) {
>> + it->lvds_dual_link = true;
>> + it->lvds_link12_swap = true;
>
> This is a nice name for the propery in the Dual Link LVDS case:
>
> ite,lvds-link-swap
Swapping LVDS link1&2 is implied by the dual-lvds-{even,odd}-pixels
properties that DT writers specify in port@0 and port@1.
The DT writers don't need to use a dedicated property like
ite,lvds-link-swap to explicitly indicate the swap.
>
>
>> + } else if (of_property_read_bool(port0, "dual-lvds-odd-pixels") &&
>> + of_property_read_bool(port1, "dual-lvds-even-pixels")) {
>> + it->lvds_dual_link = true;
>> + }
>> +
>> + if (!it->lvds_dual_link) {
>> + dev_err(dev,
>> + "failed to get LVDS dual link pixel order\n");
>> + ret = -EINVAL;
>> + }
>> + } else if (port1) {
>> + ret = -EINVAL;
>> + dev_err(dev, "single input LVDS port1 is not supported\n");
>> + } else if (!port0) {
>> + ret = -EINVAL;
>> + dev_err(dev, "no input LVDS port\n");
>> + }
>> +
>> + of_node_put(port0);
>> + of_node_put(port1);
>> +
>> + return ret;
>> +}
>> +
>> +static inline void it6263_hw_reset(struct it6263 *it)
>> +{
>> + if (!it->reset_gpio)
>> + return;
>> +
>> + gpiod_set_value_cansleep(it->reset_gpio, 0);
>> + fsleep(1000);
>> + gpiod_set_value_cansleep(it->reset_gpio, 1);
>> + /* The chip maker says the low pulse should be at least 40ms. */
>> + fsleep(40000);
>> + gpiod_set_value_cansleep(it->reset_gpio, 0);
>> + /* addtional time to wait the high voltage to be stable */
>> + fsleep(5000);
>> +}
>> +
>> +static inline int it6263_lvds_set_i2c_addr(struct it6263 *it)
>> +{
>> + int ret;
>> +
>> + ret = regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT,
>> + LVDS_INPUT_CTRL_I2C_ADDR << 1);
>> + if (ret)
>> + return ret;
>> +
>> + return regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT_EN, BIT(0));
>> +}
>> +
>> +static inline void it6263_lvds_reset(struct it6263 *it)
>> +{
>> + /* AFE PLL reset */
>> + regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), 0x0);
>> + fsleep(1000);
>> + regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), BIT(0));
>> +
>> + /* software pixel clock domain reset */
>> + regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST,
>> + REG_SOFT_P_RST);
>> + fsleep(1000);
>> + regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST, 0x0);
>> + fsleep(10000);
>> +}
>> +
>> +static inline void it6263_lvds_set_interface(struct it6263 *it)
>> +{
>> + /* color depth */
>> + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_COL_DEP, BIT8);
>> + /* output mapping */
>> + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, OUT_MAP, JEIDA);
>> +
>> + if (it->lvds_dual_link) {
>> + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, DISO);
>> + regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), BIT(1));
>> + } else {
>> + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, SISO);
>> + regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), 0);
>> + }
>> +}
>> +
>> +static inline void it6263_lvds_set_afe(struct it6263 *it)
>> +{
>> + regmap_write(it->lvds_regmap, LVDS_REG_3C, 0xaa);
>> + regmap_write(it->lvds_regmap, LVDS_REG_3F, 0x02);
>> + regmap_write(it->lvds_regmap, LVDS_REG_47, 0xaa);
>> + regmap_write(it->lvds_regmap, LVDS_REG_48, 0x02);
>> + regmap_write(it->lvds_regmap, LVDS_REG_4F, 0x11);
>> +
>> + regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_SSC_PCLK_RF,
>> + REG_SSC_PCLK_RF);
>> + regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, 0x07, 0);
>> + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_DESSC_ENB,
>> + REG_DESSC_ENB);
>> +}
>> +
>> +static inline void it6263_lvds_sys_cfg(struct it6263 *it)
>> +{
>> + regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_LVDS_IN_SWAP,
>> + it->lvds_link12_swap ? REG_LVDS_IN_SWAP : 0);
>> +}
>> +
>> +static inline void it6263_lvds_config(struct it6263 *it)
>> +{
>> + it6263_lvds_reset(it);
>> + it6263_lvds_set_interface(it);
>> + it6263_lvds_set_afe(it);
>> + it6263_lvds_sys_cfg(it);
>> +}
>> +
>> +static inline void it6263_hdmi_config(struct it6263 *it)
>> +{
>> + regmap_write(it->hdmi_regmap, HDMI_REG_SW_RST, HDMI_RST_ALL);
>> + regmap_write(it->hdmi_regmap, HDMI_REG_INPUT_MODE, IN_RGB);
>> + regmap_write_bits(it->hdmi_regmap, HDMI_REG_GCP, HDMI_COLOR_DEPTH,
>> + HDMI_COLOR_DEPTH_24);
>> +}
>> +
>> +static enum drm_connector_status it6263_detect(struct it6263 *it)
>> +{
>> + unsigned int val;
>> +
>> + regmap_read(it->hdmi_regmap, HDMI_REG_SYS_STATUS, &val);
>> + if (val & HPDETECT)
>> + return connector_status_connected;
>> + else
>> + return connector_status_disconnected;
>> +}
>> +
>> +static enum drm_connector_status
>> +it6263_connector_detect(struct drm_connector *connector, bool force)
>> +{
>> + struct it6263 *it = connector_to_it6263(connector);
>> +
>> + return it6263_detect(it);
>> +}
>> +
>> +static const struct drm_connector_funcs it6263_connector_funcs = {
>> + .detect = it6263_connector_detect,
>> + .fill_modes = drm_helper_probe_single_connector_modes,
>> + .destroy = drm_connector_cleanup,
>> + .reset = drm_atomic_helper_connector_reset,
>> + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
>> + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
>> +};
>> +
>> +static int it6263_read_edid(void *data, u8 *buf, unsigned int block, size_t len)
>> +{
>> + struct it6263 *it = data;
>> + struct regmap *regmap = it->hdmi_regmap;
>> + unsigned int start = (block % 2) * EDID_LENGTH;
>> + unsigned int segment = block >> 1;
>> + unsigned int count, val;
>> + int ret;
>> +
>> + regmap_write(regmap, HDMI_REG_DDC_MASTER_CTRL, MASTER_SEL_HOST);
>> + regmap_write(regmap, HDMI_REG_DDC_HEADER, DDC_ADDR << 1);
>> + regmap_write(regmap, HDMI_REG_DDC_EDIDSEG, segment);
>> +
>> + while (len) {
>> + /* clear DDC FIFO */
>> + regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_FIFO_CLR);
>> +
>> + ret = regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS,
>> + val, val & DDC_DONE,
>> + 2000, 10000);
>> + if (ret) {
>> + dev_err(it->dev, "failed to clear DDC FIFO:%d\n", ret);
>> + return ret;
>> + }
>> +
>> + count = len > HDMI_DDC_FIFO_BYTES ? HDMI_DDC_FIFO_BYTES : len;
>> +
>> + /* fire the read command */
>> + regmap_write(regmap, HDMI_REG_DDC_REQOFF, start);
>> + regmap_write(regmap, HDMI_REG_DDC_REQCOUNT, count);
>> + regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_EDID_READ);
>> +
>> + start += count;
>> + len -= count;
>> +
>> + ret = regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS, val,
>> + val & (DDC_DONE | DDC_ERROR),
>> + 20000, 250000);
>> + if (ret && !(val & DDC_ERROR)) {
>> + dev_err(it->dev, "failed to read EDID:%d\n", ret);
>> + return ret;
>> + }
>> +
>> + if (val & DDC_ERROR) {
>> + dev_err(it->dev, "DDC error\n");
>> + return -EIO;
>> + }
>> +
>> + /* cache to buffer */
>> + for (; count > 0; count--) {
>> + regmap_read(regmap, HDMI_REG_DDC_READFIFO, &val);
>> + *(buf++) = val;
>> + }
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int it6263_connector_get_modes(struct drm_connector *connector)
>> +{
>> + struct it6263 *it = connector_to_it6263(connector);
>> + const struct drm_edid *drm_edid;
>> + int count;
>> +
>> + drm_edid = drm_edid_read_custom(connector, it6263_read_edid, it);
>> +
>> + drm_edid_connector_update(connector, drm_edid);
>> + count = drm_edid_connector_add_modes(connector);
>> +
>> + drm_edid_free(drm_edid);
>> +
>> + return count;
>> +}
>> +
>> +static const struct drm_connector_helper_funcs it6263_connector_helper_funcs = {
>> + .get_modes = it6263_connector_get_modes,
>> +};
>> +
>> +static int it6263_bridge_atomic_check(struct drm_bridge *bridge,
>> + struct drm_bridge_state *bridge_state,
>> + struct drm_crtc_state *crtc_state,
>> + struct drm_connector_state *conn_state)
>> +{
>> + struct drm_display_mode *mode = &crtc_state->adjusted_mode;
>
> Use drm_atomic_helper_connector_hdmi_check().
Will take a look at this.
>
> Implement .hdmi_tmds_char_rate_valid(). Also, I think, single and dual
Will take a look at this.
> link LVDS have different max clock rates. Please correct me if I'm
> wrong.
Yes, I think so too. But, I don't know the exact max clock rates.
IT6263 data sheet only says LVDS RX supports clock rate up to
150MHz.
>
>> +
>> + return mode->clock > MAX_PIXEL_CLOCK_KHZ ? -EINVAL : 0;
>> +}
>> +
>> +static void
>> +it6263_bridge_atomic_disable(struct drm_bridge *bridge,
>> + struct drm_bridge_state *old_bridge_state)
>> +{
>> + struct it6263 *it = bridge_to_it6263(bridge);
>> +
>> + regmap_write_bits(it->hdmi_regmap, HDMI_REG_GCP, AVMUTE, AVMUTE);
>> + regmap_write(it->hdmi_regmap, HDMI_REG_PKT_GENERAL_CTRL, 0);
>> + regmap_write(it->hdmi_regmap, HDMI_REG_AFE_DRV_CTRL,
>> + AFE_DRV_RST | AFE_DRV_PWD);
>> +}
>> +
>> +static void
>> +it6263_hdmi_avi_infoframe_configure(struct it6263 *it,
>> + struct drm_connector *connector,
>> + const struct drm_display_mode *mode)
>
> -> .hdmi_write_infoframe() , .hdmi_clear_infoframe().
Will take a look at them.
>
>> +{
>> + struct hdmi_avi_infoframe frame;
>> + u8 buf[HDMI_INFOFRAME_SIZE(AVI)];
>> + int ret;
>> +
>> + ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
>> + if (ret) {
>> + dev_err(it->dev, "failed to setup AVI infoframe: %d\n", ret);
>> + return;
>> + }
>> +
>> + ret = hdmi_avi_infoframe_pack(&frame, buf, sizeof(buf));
>> + if (ret < 0) {
>> + dev_err(it->dev, "failed to pack infoframe: %d\n", ret);
>> + return;
>> + }
>> +
>> + /* write the first AVI infoframe data byte chunk(DB1-DB5) */
>> + ret = regmap_bulk_write(it->hdmi_regmap, HDMI_REG_AVI_DB1,
>> + &buf[HDMI_INFOFRAME_HEADER_SIZE],
>> + HDMI_AVI_DB_CHUNK1_SIZE);
>> + if (ret) {
>> + dev_err(it->dev, "failed to write the 1st AVI infoframe data byte chunk: %d\n",
>> + ret);
>> + return;
>> + }
>> +
>> + /* write the second AVI infoframe data byte chunk(DB6-DB13) */
>> + ret = regmap_bulk_write(it->hdmi_regmap, HDMI_REG_AVI_DB6,
>> + &buf[HDMI_INFOFRAME_HEADER_SIZE +
>> + HDMI_AVI_DB_CHUNK1_SIZE],
>> + HDMI_AVI_DB_CHUNK2_SIZE);
>> + if (ret) {
>> + dev_err(it->dev, "failed to write the 2nd AVI infoframe data byte chunk: %d\n",
>> + ret);
>> + return;
>> + }
>> +
>> + ret = regmap_write(it->hdmi_regmap, HDMI_REG_AVI_CSUM, buf[3]);
>> + if (ret)
>> + dev_err(it->dev, "failed to set AVI infoframe checksum: %d\n",
>> + ret);
>> +}
>> +
>> +static void
>> +it6263_bridge_atomic_enable(struct drm_bridge *bridge,
>> + struct drm_bridge_state *old_bridge_state)
>> +{
>> + struct drm_atomic_state *state = old_bridge_state->base.state;
>> + struct it6263 *it = bridge_to_it6263(bridge);
>> + const struct drm_crtc_state *crtc_state;
>> + struct regmap *regmap = it->hdmi_regmap;
>> + const struct drm_display_mode *mode;
>> + struct drm_connector *connector;
>> + bool is_stable = false;
>> + struct drm_crtc *crtc;
>> + unsigned int val;
>> + bool pclk_high;
>> + int i, ret;
>> +
>> + connector = drm_atomic_get_new_connector_for_encoder(state,
>> + bridge->encoder);
>> + crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
>> + crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
>> + mode = &crtc_state->adjusted_mode;
>> +
>> + regmap_write(regmap, HDMI_REG_HDMI_MODE, TX_HDMI_MODE);
>> +
>> + it6263_hdmi_avi_infoframe_configure(it, connector, mode);
>
> drm_atomic_helper_connector_hdmi_update_infoframes
Will take a look at this.
>
>> +
>> + /* HDMI AFE setup */
>> + pclk_high = mode->clock > HIGH_PIXEL_CLOCK_KHZ ? true : false;
>> + regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, AFE_DRV_RST);
>> + if (pclk_high)
>> + regmap_write(regmap, HDMI_REG_AFE_XP_CTRL,
>> + AFE_XP_GAINBIT | AFE_XP_RESETB);
>> + else
>> + regmap_write(regmap, HDMI_REG_AFE_XP_CTRL,
>> + AFE_XP_ER0 | AFE_XP_RESETB);
>> + regmap_write(regmap, HDMI_REG_AFE_ISW_CTRL, 0x10);
>> + if (pclk_high)
>> + regmap_write(regmap, HDMI_REG_AFE_IP_CTRL,
>> + AFE_IP_GAINBIT | AFE_IP_RESETB);
>> + else
>> + regmap_write(regmap, HDMI_REG_AFE_IP_CTRL,
>> + AFE_IP_ER0 | AFE_IP_RESETB);
>> +
>> + /* HDMI software video reset */
>> + regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, SOFTV_RST);
>> + fsleep(1000);
>> + regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, 0);
>> +
>> + /* reconfigure LVDS and retry several times in case video is instable */
>> + for (i = 0; i < 3; i++) {
>> + ret = regmap_read_poll_timeout(regmap, HDMI_REG_SYS_STATUS, val,
>> + val & TXVIDSTABLE,
>> + 20000, 500000);
>> + if (!ret) {
>> + is_stable = true;
>> + break;
>> + }
>> +
>> + it6263_lvds_config(it);
>> + }
>> +
>> + if (!is_stable)
>> + dev_warn(it->dev, "failed to wait for video stable\n");
>> +
>> + /* HDMI AFE reset release and power up */
>> + regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, 0);
>> +
>> + regmap_write_bits(regmap, HDMI_REG_GCP, AVMUTE, 0);
>> +
>> + regmap_write(regmap, HDMI_REG_PKT_GENERAL_CTRL, ENABLE_PKT | REPEAT_PKT);
>> +}
>> +
>> +static enum drm_mode_status
>> +it6263_bridge_mode_valid(struct drm_bridge *bridge,
>> + const struct drm_display_info *info,
>> + const struct drm_display_mode *mode)
>> +{
>> + return mode->clock > MAX_PIXEL_CLOCK_KHZ ? MODE_CLOCK_HIGH : MODE_OK;
>
> rate = drm_hdmi_compute_mode_clock(mode, 8, HDMI_COLORSPACE_RGB);
> return bridge->funcs->hdmi_tmds_char_rate_valid(bridge, mode, rate);
Will look into the two lines.
>
>> +}
>> +
>> +static int it6263_bridge_attach(struct drm_bridge *bridge,
>> + enum drm_bridge_attach_flags flags)
>> +{
>> + struct it6263 *it = bridge_to_it6263(bridge);
>> + int ret;
>> +
>> + ret = drm_bridge_attach(bridge->encoder, it->next_bridge, bridge,
>> + flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
>> + if (ret < 0)
>> + return ret;
>> +
>> + if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
>> + return 0;
>> +
>> + it->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
>> + DRM_CONNECTOR_POLL_DISCONNECT;
>> +
>
> Please strongly consider dropping this and using drm_bridge_connector in
> the host driver.
I can't afford to make i.MX8MP imx-lcdif KMS use drm_bridge_connector
currently. Maybe the Renesas RZ/G3E SMARC EVK Biju tested v1 patch
set with is also not using drm_bridge_connector. I hope we can leave
it as-is for now.
>
>> + ret = drm_connector_init(bridge->dev, &it->connector,
>> + &it6263_connector_funcs,
>> + DRM_MODE_CONNECTOR_HDMIA);
>> + if (ret)
>> + return ret;
>> +
>> + drm_connector_helper_add(&it->connector,
>> + &it6263_connector_helper_funcs);
>> + drm_connector_attach_encoder(&it->connector, bridge->encoder);
>> +
>> + return 0;
>> +}
>> +
>> +static enum drm_connector_status it6263_bridge_detect(struct drm_bridge *bridge)
>> +{
>> + struct it6263 *it = bridge_to_it6263(bridge);
>> +
>> + return it6263_detect(it);
>> +}
>> +
>> +static const struct drm_edid *
>> +it6263_bridge_edid_read(struct drm_bridge *bridge,
>> + struct drm_connector *connector)
>> +{
>> + struct it6263 *it = bridge_to_it6263(bridge);
>> +
>> + return drm_edid_read_custom(connector, it6263_read_edid, it);
>> +}
>> +
>> +static u32 *
>> +it6263_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
>> + struct drm_bridge_state *bridge_state,
>> + struct drm_crtc_state *crtc_state,
>> + struct drm_connector_state *conn_state,
>> + u32 output_fmt,
>> + unsigned int *num_input_fmts)
>> +{
>> + struct it6263 *it = bridge_to_it6263(bridge);
>> + u32 *input_fmts;
>> +
>> + *num_input_fmts = 0;
>> +
>> + if (it->lvds_link_num_dlanes == 3)
>> + return NULL;
>> +
>> + input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
>> + if (!input_fmts)
>> + return NULL;
>> +
>> + input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA;
>> + *num_input_fmts = 1;
>> +
>> + return input_fmts;
>> +}
>> +
>> +static const struct drm_bridge_funcs it6263_bridge_funcs = {
>> + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
>> + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
>> + .atomic_reset = drm_atomic_helper_bridge_reset,
>> + .attach = it6263_bridge_attach,
>> + .mode_valid = it6263_bridge_mode_valid,
>> + .atomic_disable = it6263_bridge_atomic_disable,
>> + .atomic_enable = it6263_bridge_atomic_enable,
>> + .atomic_check = it6263_bridge_atomic_check,
>> + .detect = it6263_bridge_detect,
>> + .edid_read = it6263_bridge_edid_read,
>> + .atomic_get_input_bus_fmts = it6263_bridge_atomic_get_input_bus_fmts,
>> +};
>> +
>> +static int it6263_probe(struct i2c_client *client)
>> +{
>> + struct device *dev = &client->dev;
>> + struct it6263 *it;
>> + int ret;
>> +
>> + it = devm_kzalloc(dev, sizeof(*it), GFP_KERNEL);
>> + if (!it)
>> + return -ENOMEM;
>> +
>> + it->dev = dev;
>> + it->hdmi_i2c = client;
>> +
>> + it->hdmi_regmap = devm_regmap_init_i2c(client,
>> + &it6263_hdmi_regmap_config);
>> + if (IS_ERR(it->hdmi_regmap))
>> + return dev_err_probe(dev, PTR_ERR(it->hdmi_regmap),
>> + "failed to init I2C regmap for HDMI\n");
>> +
>> + it->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
>> + if (IS_ERR(it->reset_gpio))
>> + return dev_err_probe(dev, PTR_ERR(it->reset_gpio),
>> + "failed to get reset gpio\n");
>> +
>> + ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(it6263_supplies),
>> + it6263_supplies);
>> + if (ret)
>> + return dev_err_probe(dev, ret, "failed to get power supplies\n");
>> +
>> + ret = it6263_parse_dt(it);
>> + if (ret)
>> + return ret;
>> +
>> + it6263_hw_reset(it);
>> +
>> + ret = it6263_lvds_set_i2c_addr(it);
>> + if (ret)
>> + return dev_err_probe(dev, ret, "failed to set I2C addr\n");
>> +
>> + it->lvds_i2c = devm_i2c_new_dummy_device(dev, client->adapter,
>> + LVDS_INPUT_CTRL_I2C_ADDR);
>> + if (IS_ERR(it->lvds_i2c))
>> + dev_err_probe(it->dev, PTR_ERR(it->lvds_i2c),
>> + "failed to allocate I2C device for LVDS\n");
>> +
>> + it->lvds_regmap = devm_regmap_init_i2c(it->lvds_i2c,
>> + &it6263_lvds_regmap_config);
>> + if (IS_ERR(it->lvds_regmap))
>> + return dev_err_probe(dev, PTR_ERR(it->lvds_regmap),
>> + "failed to init I2C regmap for LVDS\n");
>> +
>> + it6263_lvds_config(it);
>> + it6263_hdmi_config(it);
>> +
>> + i2c_set_clientdata(client, it);
>> +
>> + it->bridge.funcs = &it6263_bridge_funcs;
>> + it->bridge.of_node = dev->of_node;
>> + it->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT;
>
> | DRM_BRIDGE_OP_HDMI
Will take a look at this.
>
> BTW: No HPD IRQ support?
IT6263 chip doesn't support HPD IRQ.
>
>> + it->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
>> + drm_bridge_add(&it->bridge);
>
> devm_drm_bridge_add()
Will try to use this. Thanks.
>
>> +
>> + return 0;
>> +}
>> +
>> +static void it6263_remove(struct i2c_client *client)
>> +{
>> + struct it6263 *it = i2c_get_clientdata(client);
>> +
>> + drm_bridge_remove(&it->bridge);
>
> Remove, it becomes unused with the devm_ function.
>
>> +}
>> +
>> +static const struct of_device_id it6263_of_match[] = {
>> + { .compatible = "ite,it6263", },
>> + { }
>> +};
>> +MODULE_DEVICE_TABLE(of, it6263_of_match);
>> +
>> +static const struct i2c_device_id it6263_i2c_ids[] = {
>> + { "it6263", 0 },
>> + { }
>> +};
>> +MODULE_DEVICE_TABLE(i2c, it6263_i2c_ids);
>> +
>> +static struct i2c_driver it6263_driver = {
>> + .probe = it6263_probe,
>> + .remove = it6263_remove,
>> + .driver = {
>> + .name = "it6263",
>> + .of_match_table = it6263_of_match,
>> + },
>> + .id_table = it6263_i2c_ids,
>> +};
>> +module_i2c_driver(it6263_driver);
>> +
>> +MODULE_DESCRIPTION("ITE Tech. Inc. IT6263 LVDS/HDMI bridge");
>> +MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>");
>> +MODULE_LICENSE("GPL");
>> --
>> 2.34.1
>>
>
--
Regards,
Liu Ying
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 1/9] arm64: dts: imx8mp-skov-revb-mi1010ait-1cp1: Add panel-timing node to panel node
2024-10-12 7:35 ` [PATCH v2 1/9] arm64: dts: imx8mp-skov-revb-mi1010ait-1cp1: Add panel-timing node to panel node Liu Ying
@ 2024-10-12 20:33 ` Marek Vasut
0 siblings, 0 replies; 49+ messages in thread
From: Marek Vasut @ 2024-10-12 20:33 UTC (permalink / raw)
To: Liu Ying, dri-devel, devicetree, linux-kernel, imx,
linux-arm-kernel
Cc: andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
dmitry.baryshkov, arnd, nfraprado, o.rempel, y.moog, isaac.scott,
biju.das.jz
On 10/12/24 9:35 AM, Liu Ying wrote:
> Add a panel-timing node to panel node to override any fixed display
> modes written in a panel driver. This way, 68.9MHz clock frequency
> specified in panel-timing node may accommodate 7-fold 482.3MHz
> "media_ldb" clock which is derived from 964.6MHz "video_pll1" clock.
> The above clock frequencies align to the clock rates assigned in the
> lvds_bridge node and media_blk_ctrl node in this DT file.
>
> This should be able to suppress this LDB driver warning:
> [ 17.206644] fsl-ldb 32ec0000.blk-ctrl:bridge@5c: Configured LDB clock (70000000 Hz) does not match requested LVDS clock: 490000000 Hz
>
> This also makes the display mode used by the panel pass mode validation
> against pixel clock rate and "media_ldb" clock rate in a certain display
> driver.
>
> Fixes: 6d382d51d979 ("arm64: dts: freescale: Add SKOV IMX8MP CPU revB board")
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> ---
> v2:
> * No change.
>
> .../freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts
> index 3c2efdc59bfa..4e9f76de7462 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts
> @@ -13,6 +13,21 @@ panel {
> backlight = <&backlight>;
> power-supply = <®_tft_vcom>;
>
> + panel-timing {
> + clock-frequency = <68900000>;
> + hactive = <1280>;
> + vactive = <800>;
> + hfront-porch = <30>;
> + hback-porch = <30>;
> + hsync-len = <10>;
> + vfront-porch = <5>;
> + vback-porch = <5>;
> + vsync-len = <5>;
> + hsync-active = <0>;
> + vsync-active = <0>;
> + de-active = <1>;
> + };
There is an existing entry for this panel in panel-simple.c , please do
not duplicate timings in the DT:
drivers/gpu/drm/panel/panel-simple.c: .timings =
&multi_inno_mi1010ait_1cp_timing,
drivers/gpu/drm/panel/panel-simple.c: .compatible =
"multi-inno,mi1010ait-1cp",
drivers/gpu/drm/panel/panel-simple.c: .data =
&multi_inno_mi1010ait_1cp,
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 2/9] arm64: dts: imx8mp-phyboard-pollux-rdk: Add panel-timing node to panel-lvds node
2024-10-12 7:35 ` [PATCH v2 2/9] arm64: dts: imx8mp-phyboard-pollux-rdk: Add panel-timing node to panel-lvds node Liu Ying
@ 2024-10-12 20:34 ` Marek Vasut
0 siblings, 0 replies; 49+ messages in thread
From: Marek Vasut @ 2024-10-12 20:34 UTC (permalink / raw)
To: Liu Ying, dri-devel, devicetree, linux-kernel, imx,
linux-arm-kernel
Cc: andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
dmitry.baryshkov, arnd, nfraprado, o.rempel, y.moog, isaac.scott,
biju.das.jz
On 10/12/24 9:35 AM, Liu Ying wrote:
> Add a panel-timing node to panel-lvds node to override any fixed
> display modes written in a panel driver. This way, 74.25MHz clock
> frequency specified in panel-timing node may accommodate 7-fold
> 519.75MHz "media_ldb" clock which is derived from 1.0395GHz
> "video_pll1" clock.
>
> This should suppress this LDB driver warning:
> [ 17.923709] fsl-ldb 32ec0000.blk-ctrl:bridge@5c: Configured LDB clock (72400000 Hz) does not match requested LVDS clock: 506800000 Hz
>
> This also makes the display mode used by the panel pass mode validation
> against pixel clock rate and "media_ldb" clock rate in a certain display
> driver.
>
> Fixes: 326d86e197fc ("arm64: dts: imx8mp-phyboard-pollux-rdk: add etml panel support")
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> ---
> v2:
> * No change.
>
> .../dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
> index 50debe821c42..20cb5363cccb 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
> @@ -37,6 +37,21 @@ panel1_lvds: panel-lvds {
> backlight = <&backlight_lvds>;
> power-supply = <®_vcc_3v3_sw>;
>
> + panel-timing {
> + clock-frequency = <74250000>;
> + hactive = <1280>;
> + vactive = <800>;
> + hfront-porch = <72>;
> + hback-porch = <86>;
> + hsync-len = <2>;
> + vfront-porch = <15>;
> + vback-porch = <21>;
> + vsync-len = <2>;
> + hsync-active = <0>;
> + vsync-active = <0>;
> + de-active = <1>;
> + };
There is an existing entry for this panel in panel-simple.c , please do
not duplicate timings in the DT:
drivers/gpu/drm/panel/panel-simple.c:static const struct panel_desc
edt_etml1010g3dra = {
drivers/gpu/drm/panel/panel-simple.c: .timings =
&edt_etml1010g3dra_timing,
drivers/gpu/drm/panel/panel-simple.c: .compatible =
"edt,etml1010g3dra",
^ permalink raw reply [flat|nested] 49+ messages in thread
* RE: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-12 8:45 ` Dmitry Baryshkov
2024-10-12 10:01 ` Liu Ying
@ 2024-10-13 10:27 ` Biju Das
2024-10-14 0:06 ` Dmitry Baryshkov
1 sibling, 1 reply; 49+ messages in thread
From: Biju Das @ 2024-10-13 10:27 UTC (permalink / raw)
To: Dmitry Baryshkov, Liu Ying
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org, andrzej.hajda@intel.com,
neil.armstrong@linaro.org, rfoss@kernel.org, laurent.pinchart,
jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com,
simona@ffwll.ch, maarten.lankhorst@linux.intel.com,
mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com,
catalin.marinas@arm.com, will@kernel.org,
quic_bjorande@quicinc.com, geert+renesas@glider.be, arnd@arndb.de,
nfraprado@collabora.com, o.rempel@pengutronix.de,
y.moog@phytec.de, marex@denx.de, isaac.scott@ideasonboard.com
Hi Dmitry Baryshkov,
> -----Original Message-----
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Sent: Saturday, October 12, 2024 9:45 AM
> Subject: Re: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
>
> On Sat, Oct 12, 2024 at 03:35:40PM +0800, Liu Ying wrote:
> > Add basic HDMI video output support. Currently, only RGB888 output
> > pixel format is supported. At the LVDS input side, the driver
> > supports single LVDS link and dual LVDS links with "jeida-24" LVDS
> > mapping.
> >
> > Product link:
> > https://www.ite.com.tw/en/product/cate1/IT6263
> >
> > Signed-off-by: Liu Ying <victor.liu@nxp.com>
> > ---
> > v2:
> > * Add AVI inforframe support. (Maxime)
>
> Maxime asked to wire up the HDMI Connector framework. I have pushed the patch that converts lt9611.c
> driver. Please implement similar changes in your driver.
>
> > * Add DRM_MODE_CONNECTOR_HDMIA. (Biju)
> > * Rename it6263_reset() to it6263_hw_reset(). (Biju)
> > * Check number of LVDS link data lanes. (Biju)
> >
> > drivers/gpu/drm/bridge/Kconfig | 8 +
> > drivers/gpu/drm/bridge/Makefile | 1 +
> > drivers/gpu/drm/bridge/ite-it6263.c | 919
> > ++++++++++++++++++++++++++++
> > 3 files changed, 928 insertions(+)
> > create mode 100644 drivers/gpu/drm/bridge/ite-it6263.c
> >
> > diff --git a/drivers/gpu/drm/bridge/Kconfig
> > b/drivers/gpu/drm/bridge/Kconfig index 3eb955333c80..93f99682a090
> > 100644
> > --- a/drivers/gpu/drm/bridge/Kconfig
> > +++ b/drivers/gpu/drm/bridge/Kconfig
> > @@ -90,6 +90,14 @@ config DRM_FSL_LDB
> > help
> > Support for i.MX8MP DPI-to-LVDS on-SoC encoder.
> >
> > +config DRM_ITE_IT6263
> > + tristate "ITE IT6263 LVDS/HDMI bridge"
> > + depends on OF
> > + select DRM_KMS_HELPER
> > + select REGMAP_I2C
> > + help
> > + ITE IT6263 LVDS to HDMI bridge chip driver.
> > +
> > config DRM_ITE_IT6505
> > tristate "ITE IT6505 DisplayPort bridge"
> > depends on OF
> > diff --git a/drivers/gpu/drm/bridge/Makefile
> > b/drivers/gpu/drm/bridge/Makefile index 7df87b582dca..f3776dd473fd
> > 100644
> > --- a/drivers/gpu/drm/bridge/Makefile
> > +++ b/drivers/gpu/drm/bridge/Makefile
> > @@ -6,6 +6,7 @@ obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
> > obj-$(CONFIG_DRM_CROS_EC_ANX7688) += cros-ec-anx7688.o
> > obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
> > obj-$(CONFIG_DRM_FSL_LDB) += fsl-ldb.o
> > +obj-$(CONFIG_DRM_ITE_IT6263) += ite-it6263.o
> > obj-$(CONFIG_DRM_ITE_IT6505) += ite-it6505.o
> > obj-$(CONFIG_DRM_LONTIUM_LT8912B) += lontium-lt8912b.o
> > obj-$(CONFIG_DRM_LONTIUM_LT9211) += lontium-lt9211.o diff --git
> > a/drivers/gpu/drm/bridge/ite-it6263.c
> > b/drivers/gpu/drm/bridge/ite-it6263.c
> > new file mode 100644
> > index 000000000000..9b3318792f15
> > --- /dev/null
> > +++ b/drivers/gpu/drm/bridge/ite-it6263.c
> > @@ -0,0 +1,919 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +#include <linux/bitfield.h>
> > +#include <linux/bits.h>
> > +#include <linux/delay.h>
> > +#include <linux/gpio/consumer.h>
> > +#include <linux/hdmi.h>
> > +#include <linux/i2c.h>
> > +#include <linux/media-bus-format.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/regmap.h>
> > +#include <linux/regulator/consumer.h>
> > +
> > +#include <drm/drm_atomic.h>
> > +#include <drm/drm_atomic_helper.h>
> > +#include <drm/drm_atomic_state_helper.h> #include <drm/drm_bridge.h>
> > +#include <drm/drm_connector.h> #include <drm/drm_crtc.h> #include
> > +<drm/drm_edid.h> #include <drm/drm_of.h> #include
> > +<drm/drm_probe_helper.h>
> > +
> > +/*
> > +---------------------------------------------------------------------
> > +--------
> > + * LVDS registers
> > + */
> > +
> > +/* LVDS software reset registers */
> > +#define LVDS_REG_05 0x05
> > +#define REG_SOFT_P_RST BIT(1)
> > +
> > +/* LVDS system configuration registers */
> > +/* 0x0b */
> > +#define LVDS_REG_0B 0x0b
> > +#define REG_SSC_PCLK_RF BIT(0)
> > +#define REG_LVDS_IN_SWAP BIT(1)
> > +
> > +/* LVDS test pattern gen control registers */
> > +/* 0x2c */
> > +#define LVDS_REG_2C 0x2c
> > +#define REG_COL_DEP GENMASK(1, 0)
> > +#define BIT8 FIELD_PREP(REG_COL_DEP, 2)
> > +#define OUT_MAP BIT(4)
> > +#define JEIDA 0
> > +#define REG_DESSC_ENB BIT(6)
> > +#define DMODE BIT(7)
> > +#define DISO BIT(7)
> > +#define SISO 0
> > +
> > +#define LVDS_REG_3C 0x3c
> > +#define LVDS_REG_3F 0x3f
> > +#define LVDS_REG_47 0x47
> > +#define LVDS_REG_48 0x48
> > +#define LVDS_REG_4F 0x4f
> > +#define LVDS_REG_52 0x52
> > +
> > +/*
> > +---------------------------------------------------------------------
> > +--------
> > + * HDMI registers are separated into three banks:
> > + * 1) HDMI register common bank: 0x00 ~ 0x2f */
> > +
> > +/* HDMI genernal registers */
> > +#define HDMI_REG_SW_RST 0x04
> > +#define SOFTREF_RST BIT(5)
> > +#define SOFTA_RST BIT(4)
> > +#define SOFTV_RST BIT(3)
> > +#define AUD_RST BIT(2)
> > +#define HDCP_RST BIT(0)
> > +#define HDMI_RST_ALL (SOFTREF_RST | SOFTA_RST | SOFTV_RST | \
> > + AUD_RST | HDCP_RST)
> > +
> > +#define HDMI_REG_SYS_STATUS 0x0e
> > +#define HPDETECT BIT(6)
> > +#define TXVIDSTABLE BIT(4)
> > +
> > +#define HDMI_REG_BANK_CTRL 0x0f
> > +#define REG_BANK_SEL BIT(0)
> > +
> > +/* HDMI System DDC control registers */
> > +#define HDMI_REG_DDC_MASTER_CTRL 0x10
> > +#define MASTER_SEL_HOST BIT(0)
> > +
> > +#define HDMI_REG_DDC_HEADER 0x11
> > +
> > +#define HDMI_REG_DDC_REQOFF 0x12
> > +#define HDMI_REG_DDC_REQCOUNT 0x13
> > +#define HDMI_REG_DDC_EDIDSEG 0x14
> > +
> > +#define HDMI_REG_DDC_CMD 0x15
> > +#define DDC_CMD_EDID_READ 0x3
> > +#define DDC_CMD_FIFO_CLR 0x9
> > +
> > +#define HDMI_REG_DDC_STATUS 0x16
> > +#define DDC_DONE BIT(7)
> > +#define DDC_NOACK BIT(5)
> > +#define DDC_WAITBUS BIT(4)
> > +#define DDC_ARBILOSE BIT(3)
> > +#define DDC_ERROR (DDC_NOACK | DDC_WAITBUS | DDC_ARBILOSE)
> > +
> > +#define HDMI_DDC_FIFO_BYTES 32
> > +#define HDMI_REG_DDC_READFIFO 0x17
> > +#define HDMI_REG_LVDS_PORT 0x1d /* LVDS input control I2C addr */
> > +#define HDMI_REG_LVDS_PORT_EN 0x1e
> > +#define LVDS_INPUT_CTRL_I2C_ADDR 0x33
> > +
> > +/*
> > +---------------------------------------------------------------------
> > +--------
> > + * 2) HDMI register bank0: 0x30 ~ 0xff */
> > +
> > +/* HDMI AFE registers */
> > +#define HDMI_REG_AFE_DRV_CTRL 0x61
> > +#define AFE_DRV_PWD BIT(5)
> > +#define AFE_DRV_RST BIT(4)
> > +
> > +#define HDMI_REG_AFE_XP_CTRL 0x62
> > +#define AFE_XP_GAINBIT BIT(7)
> > +#define AFE_XP_ER0 BIT(4)
> > +#define AFE_XP_RESETB BIT(3)
> > +
> > +#define HDMI_REG_AFE_ISW_CTRL 0x63
> > +
> > +#define HDMI_REG_AFE_IP_CTRL 0x64
> > +#define AFE_IP_GAINBIT BIT(7)
> > +#define AFE_IP_ER0 BIT(3)
> > +#define AFE_IP_RESETB BIT(2)
> > +
> > +/* HDMI input data format registers */
> > +#define HDMI_REG_INPUT_MODE 0x70
> > +#define IN_RGB 0x00
> > +
> > +/* HDMI general control registers */
> > +#define HDMI_REG_HDMI_MODE 0xc0
> > +#define TX_HDMI_MODE BIT(0)
> > +
> > +#define HDMI_REG_GCP 0xc1
> > +#define AVMUTE BIT(0)
> > +#define HDMI_COLOR_DEPTH GENMASK(6, 4)
> > +#define HDMI_COLOR_DEPTH_24 FIELD_PREP(HDMI_COLOR_DEPTH, 4)
> > +
> > +#define HDMI_REG_PKT_GENERAL_CTRL 0xc6
> > +#define ENABLE_PKT BIT(0)
> > +#define REPEAT_PKT BIT(1)
> > +
> > +/*
> > +---------------------------------------------------------------------
> > +--------
> > + * 3) HDMI register bank1: 0x130 ~ 0x1ff (HDMI packet registers) */
> > +
> > +/* AVI packet registers */
> > +#define HDMI_REG_AVI_DB1 0x158
> > +#define HDMI_REG_AVI_DB2 0x159
> > +#define HDMI_REG_AVI_DB3 0x15a
> > +#define HDMI_REG_AVI_DB4 0x15b
> > +#define HDMI_REG_AVI_DB5 0x15c
> > +#define HDMI_REG_AVI_CSUM 0x15d
> > +#define HDMI_REG_AVI_DB6 0x15e
> > +#define HDMI_REG_AVI_DB7 0x15f
> > +#define HDMI_REG_AVI_DB8 0x160
> > +#define HDMI_REG_AVI_DB9 0x161
> > +#define HDMI_REG_AVI_DB10 0x162
> > +#define HDMI_REG_AVI_DB11 0x163
> > +#define HDMI_REG_AVI_DB12 0x164
> > +#define HDMI_REG_AVI_DB13 0x165
> > +
> > +#define HDMI_AVI_DB_CHUNK1_SIZE (HDMI_REG_AVI_DB5 - HDMI_REG_AVI_DB1 + 1)
> > +#define HDMI_AVI_DB_CHUNK2_SIZE (HDMI_REG_AVI_DB13 - HDMI_REG_AVI_DB6 + 1)
> > +
> > +#define MAX_PIXEL_CLOCK_KHZ 150000
> > +#define HIGH_PIXEL_CLOCK_KHZ 80000
> > +
> > +struct it6263 {
> > + struct device *dev;
> > + struct i2c_client *hdmi_i2c;
> > + struct i2c_client *lvds_i2c;
> > + struct regmap *hdmi_regmap;
> > + struct regmap *lvds_regmap;
> > + struct drm_bridge bridge;
> > + struct drm_bridge *next_bridge;
> > + struct drm_connector connector;
> > + struct gpio_desc *reset_gpio;
> > + u8 lvds_link_num_dlanes;
> > + bool lvds_dual_link;
> > + bool lvds_link12_swap;
> > +};
> > +
> > +static inline struct it6263 *bridge_to_it6263(struct drm_bridge
> > +*bridge) {
> > + return container_of(bridge, struct it6263, bridge); }
> > +
> > +static inline struct it6263 *connector_to_it6263(struct drm_connector
> > +*conn) {
> > + return container_of(conn, struct it6263, connector); }
> > +
> > +static bool it6263_hdmi_writeable_reg(struct device *dev, unsigned
> > +int reg) {
> > + switch (reg) {
> > + case HDMI_REG_SW_RST:
> > + case HDMI_REG_BANK_CTRL:
> > + case HDMI_REG_DDC_MASTER_CTRL:
> > + case HDMI_REG_DDC_HEADER:
> > + case HDMI_REG_DDC_REQOFF:
> > + case HDMI_REG_DDC_REQCOUNT:
> > + case HDMI_REG_DDC_EDIDSEG:
> > + case HDMI_REG_DDC_CMD:
> > + case HDMI_REG_LVDS_PORT:
> > + case HDMI_REG_LVDS_PORT_EN:
> > + case HDMI_REG_AFE_DRV_CTRL:
> > + case HDMI_REG_AFE_XP_CTRL:
> > + case HDMI_REG_AFE_ISW_CTRL:
> > + case HDMI_REG_AFE_IP_CTRL:
> > + case HDMI_REG_INPUT_MODE:
> > + case HDMI_REG_HDMI_MODE:
> > + case HDMI_REG_GCP:
> > + case HDMI_REG_PKT_GENERAL_CTRL:
> > + case HDMI_REG_AVI_DB1:
> > + case HDMI_REG_AVI_DB2:
> > + case HDMI_REG_AVI_DB3:
> > + case HDMI_REG_AVI_DB4:
> > + case HDMI_REG_AVI_DB5:
> > + case HDMI_REG_AVI_CSUM:
> > + case HDMI_REG_AVI_DB6:
> > + case HDMI_REG_AVI_DB7:
> > + case HDMI_REG_AVI_DB8:
> > + case HDMI_REG_AVI_DB9:
> > + case HDMI_REG_AVI_DB10:
> > + case HDMI_REG_AVI_DB11:
> > + case HDMI_REG_AVI_DB12:
> > + case HDMI_REG_AVI_DB13:
> > + return true;
> > + default:
> > + return false;
> > + }
> > +}
> > +
> > +static bool it6263_hdmi_readable_reg(struct device *dev, unsigned int
> > +reg) {
> > + if (it6263_hdmi_writeable_reg(dev, reg))
> > + return true;
> > +
> > + switch (reg) {
> > + case HDMI_REG_SYS_STATUS:
> > + case HDMI_REG_DDC_STATUS:
> > + case HDMI_REG_DDC_READFIFO:
> > + return true;
> > + default:
> > + return false;
> > + }
> > +}
> > +
> > +static bool it6263_hdmi_volatile_reg(struct device *dev, unsigned int
> > +reg) {
> > + switch (reg) {
> > + case HDMI_REG_SW_RST:
> > + case HDMI_REG_SYS_STATUS:
> > + case HDMI_REG_DDC_STATUS:
> > + case HDMI_REG_DDC_READFIFO:
> > + return true;
> > + default:
> > + return false;
> > + }
> > +}
> > +
> > +static const struct regmap_range_cfg it6263_hdmi_range_cfg = {
> > + .range_min = 0x00,
> > + .range_max = HDMI_REG_AVI_DB13,
> > + .selector_reg = HDMI_REG_BANK_CTRL,
> > + .selector_mask = REG_BANK_SEL,
> > + .selector_shift = 0,
> > + .window_start = 0x00,
> > + .window_len = 0x100,
> > +};
> > +
> > +static const struct regmap_config it6263_hdmi_regmap_config = {
> > + .name = "it6263-hdmi",
> > + .reg_bits = 8,
> > + .val_bits = 8,
> > + .writeable_reg = it6263_hdmi_writeable_reg,
> > + .readable_reg = it6263_hdmi_readable_reg,
> > + .volatile_reg = it6263_hdmi_volatile_reg,
> > + .max_register = HDMI_REG_AVI_DB13,
> > + .ranges = &it6263_hdmi_range_cfg,
> > + .num_ranges = 1,
> > + .cache_type = REGCACHE_MAPLE,
> > +};
> > +
> > +static bool it6263_lvds_writeable_reg(struct device *dev, unsigned
> > +int reg) {
> > + switch (reg) {
> > + case LVDS_REG_05:
> > + case LVDS_REG_0B:
> > + case LVDS_REG_2C:
> > + case LVDS_REG_3C:
> > + case LVDS_REG_3F:
> > + case LVDS_REG_47:
> > + case LVDS_REG_48:
> > + case LVDS_REG_4F:
> > + case LVDS_REG_52:
> > + return true;
> > + default:
> > + return false;
> > + }
> > +}
> > +
> > +static bool it6263_lvds_readable_reg(struct device *dev, unsigned int
> > +reg) {
> > + return it6263_lvds_writeable_reg(dev, reg); }
> > +
> > +static bool it6263_lvds_volatile_reg(struct device *dev, unsigned int
> > +reg) {
> > + return reg == LVDS_REG_05;
> > +}
> > +
> > +static const struct regmap_config it6263_lvds_regmap_config = {
> > + .name = "it6263-lvds",
> > + .reg_bits = 8,
> > + .val_bits = 8,
> > + .writeable_reg = it6263_lvds_writeable_reg,
> > + .readable_reg = it6263_lvds_readable_reg,
> > + .volatile_reg = it6263_lvds_volatile_reg,
> > + .max_register = LVDS_REG_52,
> > + .cache_type = REGCACHE_MAPLE,
> > +};
> > +
> > +static const char * const it6263_supplies[] = {
> > + "ivdd", "ovdd", "txavcc18", "txavcc33", "pvcc1", "pvcc2",
> > + "avcc", "anvdd", "apvdd"
> > +};
> > +
> > +static int it6263_parse_dt(struct it6263 *it) {
> > + struct device *dev = it->dev;
> > + struct device_node *port0, *port1;
> > + int ret;
> > +
> > + ret = of_property_read_u8(dev->of_node, "ite,lvds-link-num-data-lanes",
> > + &it->lvds_link_num_dlanes);
> > + if (ret) {
> > + dev_err(dev, "failed to get LVDS link number of data lanes: %d\n",
> > + ret);
> > + return ret;
> > + }
> > +
> > + it->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0);
> > + if (IS_ERR(it->next_bridge))
> > + return dev_err_probe(dev, PTR_ERR(it->next_bridge),
> > + "failed to get next bridge\n");
> > +
> > + port0 = of_graph_get_port_by_id(dev->of_node, 0);
> > + port1 = of_graph_get_port_by_id(dev->of_node, 1);
> > + if (port0 && port1) {
> > + if (of_property_read_bool(port0, "dual-lvds-even-pixels") &&
> > + of_property_read_bool(port1, "dual-lvds-odd-pixels")) {
> > + it->lvds_dual_link = true;
> > + it->lvds_link12_swap = true;
>
> This is a nice name for the propery in the Dual Link LVDS case:
>
> ite,lvds-link-swap
>
>
> > + } else if (of_property_read_bool(port0, "dual-lvds-odd-pixels") &&
> > + of_property_read_bool(port1, "dual-lvds-even-pixels")) {
> > + it->lvds_dual_link = true;
> > + }
> > +
> > + if (!it->lvds_dual_link) {
> > + dev_err(dev,
> > + "failed to get LVDS dual link pixel order\n");
> > + ret = -EINVAL;
> > + }
> > + } else if (port1) {
> > + ret = -EINVAL;
> > + dev_err(dev, "single input LVDS port1 is not supported\n");
> > + } else if (!port0) {
> > + ret = -EINVAL;
> > + dev_err(dev, "no input LVDS port\n");
> > + }
> > +
> > + of_node_put(port0);
> > + of_node_put(port1);
> > +
> > + return ret;
> > +}
> > +
> > +static inline void it6263_hw_reset(struct it6263 *it) {
> > + if (!it->reset_gpio)
> > + return;
> > +
> > + gpiod_set_value_cansleep(it->reset_gpio, 0);
> > + fsleep(1000);
> > + gpiod_set_value_cansleep(it->reset_gpio, 1);
> > + /* The chip maker says the low pulse should be at least 40ms. */
> > + fsleep(40000);
> > + gpiod_set_value_cansleep(it->reset_gpio, 0);
> > + /* addtional time to wait the high voltage to be stable */
> > + fsleep(5000);
> > +}
> > +
> > +static inline int it6263_lvds_set_i2c_addr(struct it6263 *it) {
> > + int ret;
> > +
> > + ret = regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT,
> > + LVDS_INPUT_CTRL_I2C_ADDR << 1);
> > + if (ret)
> > + return ret;
> > +
> > + return regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT_EN, BIT(0));
> > +}
> > +
> > +static inline void it6263_lvds_reset(struct it6263 *it) {
> > + /* AFE PLL reset */
> > + regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), 0x0);
> > + fsleep(1000);
> > + regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), BIT(0));
> > +
> > + /* software pixel clock domain reset */
> > + regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST,
> > + REG_SOFT_P_RST);
> > + fsleep(1000);
> > + regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST, 0x0);
> > + fsleep(10000);
> > +}
> > +
> > +static inline void it6263_lvds_set_interface(struct it6263 *it) {
> > + /* color depth */
> > + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_COL_DEP, BIT8);
> > + /* output mapping */
> > + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, OUT_MAP, JEIDA);
> > +
> > + if (it->lvds_dual_link) {
> > + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, DISO);
> > + regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), BIT(1));
> > + } else {
> > + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, SISO);
> > + regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), 0);
> > + }
> > +}
> > +
> > +static inline void it6263_lvds_set_afe(struct it6263 *it) {
> > + regmap_write(it->lvds_regmap, LVDS_REG_3C, 0xaa);
> > + regmap_write(it->lvds_regmap, LVDS_REG_3F, 0x02);
> > + regmap_write(it->lvds_regmap, LVDS_REG_47, 0xaa);
> > + regmap_write(it->lvds_regmap, LVDS_REG_48, 0x02);
> > + regmap_write(it->lvds_regmap, LVDS_REG_4F, 0x11);
> > +
> > + regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_SSC_PCLK_RF,
> > + REG_SSC_PCLK_RF);
> > + regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, 0x07, 0);
> > + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_DESSC_ENB,
> > + REG_DESSC_ENB);
> > +}
> > +
> > +static inline void it6263_lvds_sys_cfg(struct it6263 *it) {
> > + regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_LVDS_IN_SWAP,
> > + it->lvds_link12_swap ? REG_LVDS_IN_SWAP : 0); }
> > +
> > +static inline void it6263_lvds_config(struct it6263 *it) {
> > + it6263_lvds_reset(it);
> > + it6263_lvds_set_interface(it);
> > + it6263_lvds_set_afe(it);
> > + it6263_lvds_sys_cfg(it);
> > +}
> > +
> > +static inline void it6263_hdmi_config(struct it6263 *it) {
> > + regmap_write(it->hdmi_regmap, HDMI_REG_SW_RST, HDMI_RST_ALL);
> > + regmap_write(it->hdmi_regmap, HDMI_REG_INPUT_MODE, IN_RGB);
> > + regmap_write_bits(it->hdmi_regmap, HDMI_REG_GCP, HDMI_COLOR_DEPTH,
> > + HDMI_COLOR_DEPTH_24);
> > +}
> > +
> > +static enum drm_connector_status it6263_detect(struct it6263 *it) {
> > + unsigned int val;
> > +
> > + regmap_read(it->hdmi_regmap, HDMI_REG_SYS_STATUS, &val);
> > + if (val & HPDETECT)
> > + return connector_status_connected;
> > + else
> > + return connector_status_disconnected; }
> > +
> > +static enum drm_connector_status
> > +it6263_connector_detect(struct drm_connector *connector, bool force)
> > +{
> > + struct it6263 *it = connector_to_it6263(connector);
> > +
> > + return it6263_detect(it);
> > +}
> > +
> > +static const struct drm_connector_funcs it6263_connector_funcs = {
> > + .detect = it6263_connector_detect,
> > + .fill_modes = drm_helper_probe_single_connector_modes,
> > + .destroy = drm_connector_cleanup,
> > + .reset = drm_atomic_helper_connector_reset,
> > + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
> > + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> > +};
> > +
> > +static int it6263_read_edid(void *data, u8 *buf, unsigned int block,
> > +size_t len) {
> > + struct it6263 *it = data;
> > + struct regmap *regmap = it->hdmi_regmap;
> > + unsigned int start = (block % 2) * EDID_LENGTH;
> > + unsigned int segment = block >> 1;
> > + unsigned int count, val;
> > + int ret;
> > +
> > + regmap_write(regmap, HDMI_REG_DDC_MASTER_CTRL, MASTER_SEL_HOST);
> > + regmap_write(regmap, HDMI_REG_DDC_HEADER, DDC_ADDR << 1);
> > + regmap_write(regmap, HDMI_REG_DDC_EDIDSEG, segment);
> > +
> > + while (len) {
> > + /* clear DDC FIFO */
> > + regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_FIFO_CLR);
> > +
> > + ret = regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS,
> > + val, val & DDC_DONE,
> > + 2000, 10000);
> > + if (ret) {
> > + dev_err(it->dev, "failed to clear DDC FIFO:%d\n", ret);
> > + return ret;
> > + }
> > +
> > + count = len > HDMI_DDC_FIFO_BYTES ? HDMI_DDC_FIFO_BYTES : len;
> > +
> > + /* fire the read command */
> > + regmap_write(regmap, HDMI_REG_DDC_REQOFF, start);
> > + regmap_write(regmap, HDMI_REG_DDC_REQCOUNT, count);
> > + regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_EDID_READ);
> > +
> > + start += count;
> > + len -= count;
> > +
> > + ret = regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS, val,
> > + val & (DDC_DONE | DDC_ERROR),
> > + 20000, 250000);
> > + if (ret && !(val & DDC_ERROR)) {
> > + dev_err(it->dev, "failed to read EDID:%d\n", ret);
> > + return ret;
> > + }
> > +
> > + if (val & DDC_ERROR) {
> > + dev_err(it->dev, "DDC error\n");
> > + return -EIO;
> > + }
> > +
> > + /* cache to buffer */
> > + for (; count > 0; count--) {
> > + regmap_read(regmap, HDMI_REG_DDC_READFIFO, &val);
> > + *(buf++) = val;
> > + }
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int it6263_connector_get_modes(struct drm_connector
> > +*connector) {
> > + struct it6263 *it = connector_to_it6263(connector);
> > + const struct drm_edid *drm_edid;
> > + int count;
> > +
> > + drm_edid = drm_edid_read_custom(connector, it6263_read_edid, it);
> > +
> > + drm_edid_connector_update(connector, drm_edid);
> > + count = drm_edid_connector_add_modes(connector);
> > +
> > + drm_edid_free(drm_edid);
> > +
> > + return count;
> > +}
> > +
> > +static const struct drm_connector_helper_funcs it6263_connector_helper_funcs = {
> > + .get_modes = it6263_connector_get_modes, };
> > +
> > +static int it6263_bridge_atomic_check(struct drm_bridge *bridge,
> > + struct drm_bridge_state *bridge_state,
> > + struct drm_crtc_state *crtc_state,
> > + struct drm_connector_state *conn_state) {
> > + struct drm_display_mode *mode = &crtc_state->adjusted_mode;
>
> Use drm_atomic_helper_connector_hdmi_check().
>
> Implement .hdmi_tmds_char_rate_valid(). Also, I think, single and dual link LVDS have different max
> clock rates. Please correct me if I'm wrong.
I guess this rate will be same for both links in dual lvds mode.
For single link, it supports only link0.
We cannot operate link1 its Own.
From ITE point the max rate is rate corresponding to 1080p(148-150MHz)
single and dual link LVDS have different max clock rates, but that constraint is
in SoC side?? ITE HW manual does not mention about this.
>
> > +
> > + return mode->clock > MAX_PIXEL_CLOCK_KHZ ? -EINVAL : 0; }
> > +
> > +static void
> > +it6263_bridge_atomic_disable(struct drm_bridge *bridge,
> > + struct drm_bridge_state *old_bridge_state) {
> > + struct it6263 *it = bridge_to_it6263(bridge);
> > +
> > + regmap_write_bits(it->hdmi_regmap, HDMI_REG_GCP, AVMUTE, AVMUTE);
> > + regmap_write(it->hdmi_regmap, HDMI_REG_PKT_GENERAL_CTRL, 0);
> > + regmap_write(it->hdmi_regmap, HDMI_REG_AFE_DRV_CTRL,
> > + AFE_DRV_RST | AFE_DRV_PWD);
> > +}
> > +
> > +static void
> > +it6263_hdmi_avi_infoframe_configure(struct it6263 *it,
> > + struct drm_connector *connector,
> > + const struct drm_display_mode *mode)
>
> -> .hdmi_write_infoframe() , .hdmi_clear_infoframe().
>
> > +{
> > + struct hdmi_avi_infoframe frame;
> > + u8 buf[HDMI_INFOFRAME_SIZE(AVI)];
> > + int ret;
> > +
> > + ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
> > + if (ret) {
> > + dev_err(it->dev, "failed to setup AVI infoframe: %d\n", ret);
> > + return;
> > + }
> > +
> > + ret = hdmi_avi_infoframe_pack(&frame, buf, sizeof(buf));
> > + if (ret < 0) {
> > + dev_err(it->dev, "failed to pack infoframe: %d\n", ret);
> > + return;
> > + }
> > +
> > + /* write the first AVI infoframe data byte chunk(DB1-DB5) */
> > + ret = regmap_bulk_write(it->hdmi_regmap, HDMI_REG_AVI_DB1,
> > + &buf[HDMI_INFOFRAME_HEADER_SIZE],
> > + HDMI_AVI_DB_CHUNK1_SIZE);
> > + if (ret) {
> > + dev_err(it->dev, "failed to write the 1st AVI infoframe data byte chunk: %d\n",
> > + ret);
> > + return;
> > + }
> > +
> > + /* write the second AVI infoframe data byte chunk(DB6-DB13) */
> > + ret = regmap_bulk_write(it->hdmi_regmap, HDMI_REG_AVI_DB6,
> > + &buf[HDMI_INFOFRAME_HEADER_SIZE +
> > + HDMI_AVI_DB_CHUNK1_SIZE],
> > + HDMI_AVI_DB_CHUNK2_SIZE);
> > + if (ret) {
> > + dev_err(it->dev, "failed to write the 2nd AVI infoframe data byte chunk: %d\n",
> > + ret);
> > + return;
> > + }
> > +
> > + ret = regmap_write(it->hdmi_regmap, HDMI_REG_AVI_CSUM, buf[3]);
> > + if (ret)
> > + dev_err(it->dev, "failed to set AVI infoframe checksum: %d\n",
> > + ret);
> > +}
> > +
> > +static void
> > +it6263_bridge_atomic_enable(struct drm_bridge *bridge,
> > + struct drm_bridge_state *old_bridge_state) {
> > + struct drm_atomic_state *state = old_bridge_state->base.state;
> > + struct it6263 *it = bridge_to_it6263(bridge);
> > + const struct drm_crtc_state *crtc_state;
> > + struct regmap *regmap = it->hdmi_regmap;
> > + const struct drm_display_mode *mode;
> > + struct drm_connector *connector;
> > + bool is_stable = false;
> > + struct drm_crtc *crtc;
> > + unsigned int val;
> > + bool pclk_high;
> > + int i, ret;
> > +
> > + connector = drm_atomic_get_new_connector_for_encoder(state,
> > + bridge->encoder);
> > + crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
> > + crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
> > + mode = &crtc_state->adjusted_mode;
> > +
> > + regmap_write(regmap, HDMI_REG_HDMI_MODE, TX_HDMI_MODE);
> > +
> > + it6263_hdmi_avi_infoframe_configure(it, connector, mode);
>
> drm_atomic_helper_connector_hdmi_update_infoframes
>
> > +
> > + /* HDMI AFE setup */
> > + pclk_high = mode->clock > HIGH_PIXEL_CLOCK_KHZ ? true : false;
> > + regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, AFE_DRV_RST);
> > + if (pclk_high)
> > + regmap_write(regmap, HDMI_REG_AFE_XP_CTRL,
> > + AFE_XP_GAINBIT | AFE_XP_RESETB);
> > + else
> > + regmap_write(regmap, HDMI_REG_AFE_XP_CTRL,
> > + AFE_XP_ER0 | AFE_XP_RESETB);
> > + regmap_write(regmap, HDMI_REG_AFE_ISW_CTRL, 0x10);
> > + if (pclk_high)
> > + regmap_write(regmap, HDMI_REG_AFE_IP_CTRL,
> > + AFE_IP_GAINBIT | AFE_IP_RESETB);
> > + else
> > + regmap_write(regmap, HDMI_REG_AFE_IP_CTRL,
> > + AFE_IP_ER0 | AFE_IP_RESETB);
> > +
> > + /* HDMI software video reset */
> > + regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, SOFTV_RST);
> > + fsleep(1000);
> > + regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, 0);
> > +
> > + /* reconfigure LVDS and retry several times in case video is instable */
> > + for (i = 0; i < 3; i++) {
> > + ret = regmap_read_poll_timeout(regmap, HDMI_REG_SYS_STATUS, val,
> > + val & TXVIDSTABLE,
> > + 20000, 500000);
> > + if (!ret) {
> > + is_stable = true;
> > + break;
> > + }
> > +
> > + it6263_lvds_config(it);
> > + }
> > +
> > + if (!is_stable)
> > + dev_warn(it->dev, "failed to wait for video stable\n");
> > +
> > + /* HDMI AFE reset release and power up */
> > + regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, 0);
> > +
> > + regmap_write_bits(regmap, HDMI_REG_GCP, AVMUTE, 0);
> > +
> > + regmap_write(regmap, HDMI_REG_PKT_GENERAL_CTRL, ENABLE_PKT |
> > +REPEAT_PKT); }
> > +
> > +static enum drm_mode_status
> > +it6263_bridge_mode_valid(struct drm_bridge *bridge,
> > + const struct drm_display_info *info,
> > + const struct drm_display_mode *mode) {
> > + return mode->clock > MAX_PIXEL_CLOCK_KHZ ? MODE_CLOCK_HIGH :
> > +MODE_OK;
>
> rate = drm_hdmi_compute_mode_clock(mode, 8, HDMI_COLORSPACE_RGB);
> return bridge->funcs->hdmi_tmds_char_rate_valid(bridge, mode, rate);
>
> > +}
> > +
> > +static int it6263_bridge_attach(struct drm_bridge *bridge,
> > + enum drm_bridge_attach_flags flags) {
> > + struct it6263 *it = bridge_to_it6263(bridge);
> > + int ret;
> > +
> > + ret = drm_bridge_attach(bridge->encoder, it->next_bridge, bridge,
> > + flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
> > + if (ret < 0)
> > + return ret;
> > +
> > + if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
> > + return 0;
> > +
> > + it->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
> > + DRM_CONNECTOR_POLL_DISCONNECT;
> > +
>
> Please strongly consider dropping this and using drm_bridge_connector in the host driver.
>
> > + ret = drm_connector_init(bridge->dev, &it->connector,
> > + &it6263_connector_funcs,
> > + DRM_MODE_CONNECTOR_HDMIA);
> > + if (ret)
> > + return ret;
> > +
> > + drm_connector_helper_add(&it->connector,
> > + &it6263_connector_helper_funcs);
> > + drm_connector_attach_encoder(&it->connector, bridge->encoder);
> > +
> > + return 0;
> > +}
> > +
> > +static enum drm_connector_status it6263_bridge_detect(struct
> > +drm_bridge *bridge) {
> > + struct it6263 *it = bridge_to_it6263(bridge);
> > +
> > + return it6263_detect(it);
> > +}
> > +
> > +static const struct drm_edid *
> > +it6263_bridge_edid_read(struct drm_bridge *bridge,
> > + struct drm_connector *connector)
> > +{
> > + struct it6263 *it = bridge_to_it6263(bridge);
> > +
> > + return drm_edid_read_custom(connector, it6263_read_edid, it); }
> > +
> > +static u32 *
> > +it6263_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
> > + struct drm_bridge_state *bridge_state,
> > + struct drm_crtc_state *crtc_state,
> > + struct drm_connector_state *conn_state,
> > + u32 output_fmt,
> > + unsigned int *num_input_fmts)
> > +{
> > + struct it6263 *it = bridge_to_it6263(bridge);
> > + u32 *input_fmts;
> > +
> > + *num_input_fmts = 0;
> > +
> > + if (it->lvds_link_num_dlanes == 3)
> > + return NULL;
> > +
> > + input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
> > + if (!input_fmts)
> > + return NULL;
> > +
> > + input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA;
> > + *num_input_fmts = 1;
> > +
> > + return input_fmts;
> > +}
> > +
> > +static const struct drm_bridge_funcs it6263_bridge_funcs = {
> > + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
> > + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
> > + .atomic_reset = drm_atomic_helper_bridge_reset,
> > + .attach = it6263_bridge_attach,
> > + .mode_valid = it6263_bridge_mode_valid,
> > + .atomic_disable = it6263_bridge_atomic_disable,
> > + .atomic_enable = it6263_bridge_atomic_enable,
> > + .atomic_check = it6263_bridge_atomic_check,
> > + .detect = it6263_bridge_detect,
> > + .edid_read = it6263_bridge_edid_read,
> > + .atomic_get_input_bus_fmts =
> > +it6263_bridge_atomic_get_input_bus_fmts,
> > +};
> > +
> > +static int it6263_probe(struct i2c_client *client) {
> > + struct device *dev = &client->dev;
> > + struct it6263 *it;
> > + int ret;
> > +
> > + it = devm_kzalloc(dev, sizeof(*it), GFP_KERNEL);
> > + if (!it)
> > + return -ENOMEM;
> > +
> > + it->dev = dev;
> > + it->hdmi_i2c = client;
> > +
> > + it->hdmi_regmap = devm_regmap_init_i2c(client,
> > + &it6263_hdmi_regmap_config);
> > + if (IS_ERR(it->hdmi_regmap))
> > + return dev_err_probe(dev, PTR_ERR(it->hdmi_regmap),
> > + "failed to init I2C regmap for HDMI\n");
> > +
> > + it->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
> > + if (IS_ERR(it->reset_gpio))
> > + return dev_err_probe(dev, PTR_ERR(it->reset_gpio),
> > + "failed to get reset gpio\n");
> > +
> > + ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(it6263_supplies),
> > + it6263_supplies);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "failed to get power supplies\n");
> > +
> > + ret = it6263_parse_dt(it);
> > + if (ret)
> > + return ret;
> > +
> > + it6263_hw_reset(it);
> > +
> > + ret = it6263_lvds_set_i2c_addr(it);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "failed to set I2C addr\n");
> > +
> > + it->lvds_i2c = devm_i2c_new_dummy_device(dev, client->adapter,
> > + LVDS_INPUT_CTRL_I2C_ADDR);
> > + if (IS_ERR(it->lvds_i2c))
> > + dev_err_probe(it->dev, PTR_ERR(it->lvds_i2c),
> > + "failed to allocate I2C device for LVDS\n");
> > +
> > + it->lvds_regmap = devm_regmap_init_i2c(it->lvds_i2c,
> > + &it6263_lvds_regmap_config);
> > + if (IS_ERR(it->lvds_regmap))
> > + return dev_err_probe(dev, PTR_ERR(it->lvds_regmap),
> > + "failed to init I2C regmap for LVDS\n");
> > +
> > + it6263_lvds_config(it);
> > + it6263_hdmi_config(it);
> > +
> > + i2c_set_clientdata(client, it);
> > +
> > + it->bridge.funcs = &it6263_bridge_funcs;
> > + it->bridge.of_node = dev->of_node;
> > + it->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT;
>
> | DRM_BRIDGE_OP_HDMI
>
> BTW: No HPD IRQ support?
Renesas SMARC RZ/G3E this signal is internal. No dedicted IRQ line
Populated for this signal. I don't know about NXP and any other platforms
has HPD wired to test the HPD IRQ support.
Maybe go with poll method now and add hot plug support,
when we have platform with HPD to test.
Cheers,
Biju
>
> > + it->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
> > + drm_bridge_add(&it->bridge);
>
> devm_drm_bridge_add()
>
> > +
> > + return 0;
> > +}
> > +
> > +static void it6263_remove(struct i2c_client *client) {
> > + struct it6263 *it = i2c_get_clientdata(client);
> > +
> > + drm_bridge_remove(&it->bridge);
>
> Remove, it becomes unused with the devm_ function.
>
> > +}
> > +
> > +static const struct of_device_id it6263_of_match[] = {
> > + { .compatible = "ite,it6263", },
> > + { }
> > +};
> > +MODULE_DEVICE_TABLE(of, it6263_of_match);
> > +
> > +static const struct i2c_device_id it6263_i2c_ids[] = {
> > + { "it6263", 0 },
> > + { }
> > +};
> > +MODULE_DEVICE_TABLE(i2c, it6263_i2c_ids);
> > +
> > +static struct i2c_driver it6263_driver = {
> > + .probe = it6263_probe,
> > + .remove = it6263_remove,
> > + .driver = {
> > + .name = "it6263",
> > + .of_match_table = it6263_of_match,
> > + },
> > + .id_table = it6263_i2c_ids,
> > +};
> > +module_i2c_driver(it6263_driver);
> > +
> > +MODULE_DESCRIPTION("ITE Tech. Inc. IT6263 LVDS/HDMI bridge");
> > +MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>");
> > +MODULE_LICENSE("GPL");
> > --
> > 2.34.1
> >
>
> --
> With best wishes
> Dmitry
^ permalink raw reply [flat|nested] 49+ messages in thread
* RE: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-12 10:01 ` Liu Ying
@ 2024-10-13 10:48 ` Biju Das
2024-10-14 0:00 ` Dmitry Baryshkov
2024-10-13 23:58 ` Dmitry Baryshkov
1 sibling, 1 reply; 49+ messages in thread
From: Biju Das @ 2024-10-13 10:48 UTC (permalink / raw)
To: Liu Ying, Dmitry Baryshkov
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, imx@lists.linux.dev,
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Hi Liu Ying,
> -----Original Message-----
> From: Liu Ying <victor.liu@nxp.com>
> Sent: Saturday, October 12, 2024 11:02 AM
> To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Cc: dri-devel@lists.freedesktop.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> Subject: Re: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
>
> On 10/12/2024, Dmitry Baryshkov wrote:
> > On Sat, Oct 12, 2024 at 03:35:40PM +0800, Liu Ying wrote:
> >> Add basic HDMI video output support. Currently, only RGB888 output
> >> pixel format is supported. At the LVDS input side, the driver
> >> supports single LVDS link and dual LVDS links with "jeida-24" LVDS
> >> mapping.
> >>
> >> Product link:
> >> https://www.ite.com.tw/en/product/cate1/IT6263
> >>
> >> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> >> ---
> >> v2:
> >> * Add AVI inforframe support. (Maxime)
> >
> > Maxime asked to wire up the HDMI Connector framework. I have pushed
> > the patch that converts lt9611.c driver. Please implement similar
> > changes in your driver.
>
> Hmm, didn't fully get the meaning of "the new HDMI bridge infrastructure"
> maxime asked. Ok, will take a look at lt9611.c.
>
> >
> >> * Add DRM_MODE_CONNECTOR_HDMIA. (Biju)
> >> * Rename it6263_reset() to it6263_hw_reset(). (Biju)
> >> * Check number of LVDS link data lanes. (Biju)
> >>
> >> drivers/gpu/drm/bridge/Kconfig | 8 +
> >> drivers/gpu/drm/bridge/Makefile | 1 +
> >> drivers/gpu/drm/bridge/ite-it6263.c | 919
> >> ++++++++++++++++++++++++++++
> >> 3 files changed, 928 insertions(+)
> >> create mode 100644 drivers/gpu/drm/bridge/ite-it6263.c
> >>
> >> diff --git a/drivers/gpu/drm/bridge/Kconfig
> >> b/drivers/gpu/drm/bridge/Kconfig index 3eb955333c80..93f99682a090
> >> 100644
> >> --- a/drivers/gpu/drm/bridge/Kconfig
> >> +++ b/drivers/gpu/drm/bridge/Kconfig
> >> @@ -90,6 +90,14 @@ config DRM_FSL_LDB
> >> help
> >> Support for i.MX8MP DPI-to-LVDS on-SoC encoder.
> >>
> >> +config DRM_ITE_IT6263
> >> + tristate "ITE IT6263 LVDS/HDMI bridge"
> >> + depends on OF
> >> + select DRM_KMS_HELPER
> >> + select REGMAP_I2C
> >> + help
> >> + ITE IT6263 LVDS to HDMI bridge chip driver.
> >> +
> >> config DRM_ITE_IT6505
> >> tristate "ITE IT6505 DisplayPort bridge"
> >> depends on OF
> >> diff --git a/drivers/gpu/drm/bridge/Makefile
> >> b/drivers/gpu/drm/bridge/Makefile index 7df87b582dca..f3776dd473fd
> >> 100644
> >> --- a/drivers/gpu/drm/bridge/Makefile
> >> +++ b/drivers/gpu/drm/bridge/Makefile
> >> @@ -6,6 +6,7 @@ obj-$(CONFIG_DRM_CHRONTEL_CH7033) +=
> >> chrontel-ch7033.o
> >> obj-$(CONFIG_DRM_CROS_EC_ANX7688) += cros-ec-anx7688.o
> >> obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
> >> obj-$(CONFIG_DRM_FSL_LDB) += fsl-ldb.o
> >> +obj-$(CONFIG_DRM_ITE_IT6263) += ite-it6263.o
> >> obj-$(CONFIG_DRM_ITE_IT6505) += ite-it6505.o
> >> obj-$(CONFIG_DRM_LONTIUM_LT8912B) += lontium-lt8912b.o
> >> obj-$(CONFIG_DRM_LONTIUM_LT9211) += lontium-lt9211.o diff --git
> >> a/drivers/gpu/drm/bridge/ite-it6263.c
> >> b/drivers/gpu/drm/bridge/ite-it6263.c
> >> new file mode 100644
> >> index 000000000000..9b3318792f15
> >> --- /dev/null
> >> +++ b/drivers/gpu/drm/bridge/ite-it6263.c
> >> @@ -0,0 +1,919 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +/*
> >> + * Copyright 2024 NXP
> >> + */
> >> +
> >> +#include <linux/bitfield.h>
> >> +#include <linux/bits.h>
> >> +#include <linux/delay.h>
> >> +#include <linux/gpio/consumer.h>
> >> +#include <linux/hdmi.h>
> >> +#include <linux/i2c.h>
> >> +#include <linux/media-bus-format.h>
> >> +#include <linux/module.h>
> >> +#include <linux/of.h>
> >> +#include <linux/regmap.h>
> >> +#include <linux/regulator/consumer.h>
> >> +
> >> +#include <drm/drm_atomic.h>
> >> +#include <drm/drm_atomic_helper.h>
> >> +#include <drm/drm_atomic_state_helper.h> #include <drm/drm_bridge.h>
> >> +#include <drm/drm_connector.h> #include <drm/drm_crtc.h> #include
> >> +<drm/drm_edid.h> #include <drm/drm_of.h> #include
> >> +<drm/drm_probe_helper.h>
> >> +
> >> +/*
> >> +--------------------------------------------------------------------
> >> +---------
> >> + * LVDS registers
> >> + */
> >> +
> >> +/* LVDS software reset registers */
> >> +#define LVDS_REG_05 0x05
> >> +#define REG_SOFT_P_RST BIT(1)
> >> +
> >> +/* LVDS system configuration registers */
> >> +/* 0x0b */
> >> +#define LVDS_REG_0B 0x0b
> >> +#define REG_SSC_PCLK_RF BIT(0)
> >> +#define REG_LVDS_IN_SWAP BIT(1)
> >> +
> >> +/* LVDS test pattern gen control registers */
> >> +/* 0x2c */
> >> +#define LVDS_REG_2C 0x2c
> >> +#define REG_COL_DEP GENMASK(1, 0)
> >> +#define BIT8 FIELD_PREP(REG_COL_DEP, 2)
> >> +#define OUT_MAP BIT(4)
> >> +#define JEIDA 0
> >> +#define REG_DESSC_ENB BIT(6)
> >> +#define DMODE BIT(7)
> >> +#define DISO BIT(7)
> >> +#define SISO 0
> >> +
> >> +#define LVDS_REG_3C 0x3c
> >> +#define LVDS_REG_3F 0x3f
> >> +#define LVDS_REG_47 0x47
> >> +#define LVDS_REG_48 0x48
> >> +#define LVDS_REG_4F 0x4f
> >> +#define LVDS_REG_52 0x52
> >> +
> >> +/*
> >> +--------------------------------------------------------------------
> >> +---------
> >> + * HDMI registers are separated into three banks:
> >> + * 1) HDMI register common bank: 0x00 ~ 0x2f */
> >> +
> >> +/* HDMI genernal registers */
> >> +#define HDMI_REG_SW_RST 0x04
> >> +#define SOFTREF_RST BIT(5)
> >> +#define SOFTA_RST BIT(4)
> >> +#define SOFTV_RST BIT(3)
> >> +#define AUD_RST BIT(2)
> >> +#define HDCP_RST BIT(0)
> >> +#define HDMI_RST_ALL (SOFTREF_RST | SOFTA_RST | SOFTV_RST | \
> >> + AUD_RST | HDCP_RST)
> >> +
> >> +#define HDMI_REG_SYS_STATUS 0x0e
> >> +#define HPDETECT BIT(6)
> >> +#define TXVIDSTABLE BIT(4)
> >> +
> >> +#define HDMI_REG_BANK_CTRL 0x0f
> >> +#define REG_BANK_SEL BIT(0)
> >> +
> >> +/* HDMI System DDC control registers */
> >> +#define HDMI_REG_DDC_MASTER_CTRL 0x10
> >> +#define MASTER_SEL_HOST BIT(0)
> >> +
> >> +#define HDMI_REG_DDC_HEADER 0x11
> >> +
> >> +#define HDMI_REG_DDC_REQOFF 0x12
> >> +#define HDMI_REG_DDC_REQCOUNT 0x13
> >> +#define HDMI_REG_DDC_EDIDSEG 0x14
> >> +
> >> +#define HDMI_REG_DDC_CMD 0x15
> >> +#define DDC_CMD_EDID_READ 0x3
> >> +#define DDC_CMD_FIFO_CLR 0x9
> >> +
> >> +#define HDMI_REG_DDC_STATUS 0x16
> >> +#define DDC_DONE BIT(7)
> >> +#define DDC_NOACK BIT(5)
> >> +#define DDC_WAITBUS BIT(4)
> >> +#define DDC_ARBILOSE BIT(3)
> >> +#define DDC_ERROR (DDC_NOACK | DDC_WAITBUS | DDC_ARBILOSE)
> >> +
> >> +#define HDMI_DDC_FIFO_BYTES 32
> >> +#define HDMI_REG_DDC_READFIFO 0x17
> >> +#define HDMI_REG_LVDS_PORT 0x1d /* LVDS input control I2C addr */
> >> +#define HDMI_REG_LVDS_PORT_EN 0x1e
> >> +#define LVDS_INPUT_CTRL_I2C_ADDR 0x33
> >> +
> >> +/*
> >> +--------------------------------------------------------------------
> >> +---------
> >> + * 2) HDMI register bank0: 0x30 ~ 0xff */
> >> +
> >> +/* HDMI AFE registers */
> >> +#define HDMI_REG_AFE_DRV_CTRL 0x61
> >> +#define AFE_DRV_PWD BIT(5)
> >> +#define AFE_DRV_RST BIT(4)
> >> +
> >> +#define HDMI_REG_AFE_XP_CTRL 0x62
> >> +#define AFE_XP_GAINBIT BIT(7)
> >> +#define AFE_XP_ER0 BIT(4)
> >> +#define AFE_XP_RESETB BIT(3)
> >> +
> >> +#define HDMI_REG_AFE_ISW_CTRL 0x63
> >> +
> >> +#define HDMI_REG_AFE_IP_CTRL 0x64
> >> +#define AFE_IP_GAINBIT BIT(7)
> >> +#define AFE_IP_ER0 BIT(3)
> >> +#define AFE_IP_RESETB BIT(2)
> >> +
> >> +/* HDMI input data format registers */
> >> +#define HDMI_REG_INPUT_MODE 0x70
> >> +#define IN_RGB 0x00
> >> +
> >> +/* HDMI general control registers */
> >> +#define HDMI_REG_HDMI_MODE 0xc0
> >> +#define TX_HDMI_MODE BIT(0)
> >> +
> >> +#define HDMI_REG_GCP 0xc1
> >> +#define AVMUTE BIT(0)
> >> +#define HDMI_COLOR_DEPTH GENMASK(6, 4)
> >> +#define HDMI_COLOR_DEPTH_24 FIELD_PREP(HDMI_COLOR_DEPTH, 4)
> >> +
> >> +#define HDMI_REG_PKT_GENERAL_CTRL 0xc6
> >> +#define ENABLE_PKT BIT(0)
> >> +#define REPEAT_PKT BIT(1)
> >> +
> >> +/*
> >> +--------------------------------------------------------------------
> >> +---------
> >> + * 3) HDMI register bank1: 0x130 ~ 0x1ff (HDMI packet registers) */
> >> +
> >> +/* AVI packet registers */
> >> +#define HDMI_REG_AVI_DB1 0x158
> >> +#define HDMI_REG_AVI_DB2 0x159
> >> +#define HDMI_REG_AVI_DB3 0x15a
> >> +#define HDMI_REG_AVI_DB4 0x15b
> >> +#define HDMI_REG_AVI_DB5 0x15c
> >> +#define HDMI_REG_AVI_CSUM 0x15d
> >> +#define HDMI_REG_AVI_DB6 0x15e
> >> +#define HDMI_REG_AVI_DB7 0x15f
> >> +#define HDMI_REG_AVI_DB8 0x160
> >> +#define HDMI_REG_AVI_DB9 0x161
> >> +#define HDMI_REG_AVI_DB10 0x162
> >> +#define HDMI_REG_AVI_DB11 0x163
> >> +#define HDMI_REG_AVI_DB12 0x164
> >> +#define HDMI_REG_AVI_DB13 0x165
> >> +
> >> +#define HDMI_AVI_DB_CHUNK1_SIZE (HDMI_REG_AVI_DB5 - HDMI_REG_AVI_DB1 + 1)
> >> +#define HDMI_AVI_DB_CHUNK2_SIZE (HDMI_REG_AVI_DB13 - HDMI_REG_AVI_DB6 + 1)
> >> +
> >> +#define MAX_PIXEL_CLOCK_KHZ 150000
> >> +#define HIGH_PIXEL_CLOCK_KHZ 80000
> >> +
> >> +struct it6263 {
> >> + struct device *dev;
> >> + struct i2c_client *hdmi_i2c;
> >> + struct i2c_client *lvds_i2c;
> >> + struct regmap *hdmi_regmap;
> >> + struct regmap *lvds_regmap;
> >> + struct drm_bridge bridge;
> >> + struct drm_bridge *next_bridge;
> >> + struct drm_connector connector;
> >> + struct gpio_desc *reset_gpio;
> >> + u8 lvds_link_num_dlanes;
> >> + bool lvds_dual_link;
> >> + bool lvds_link12_swap;
> >> +};
> >> +
> >> +static inline struct it6263 *bridge_to_it6263(struct drm_bridge
> >> +*bridge) {
> >> + return container_of(bridge, struct it6263, bridge); }
> >> +
> >> +static inline struct it6263 *connector_to_it6263(struct
> >> +drm_connector *conn) {
> >> + return container_of(conn, struct it6263, connector); }
> >> +
> >> +static bool it6263_hdmi_writeable_reg(struct device *dev, unsigned
> >> +int reg) {
> >> + switch (reg) {
> >> + case HDMI_REG_SW_RST:
> >> + case HDMI_REG_BANK_CTRL:
> >> + case HDMI_REG_DDC_MASTER_CTRL:
> >> + case HDMI_REG_DDC_HEADER:
> >> + case HDMI_REG_DDC_REQOFF:
> >> + case HDMI_REG_DDC_REQCOUNT:
> >> + case HDMI_REG_DDC_EDIDSEG:
> >> + case HDMI_REG_DDC_CMD:
> >> + case HDMI_REG_LVDS_PORT:
> >> + case HDMI_REG_LVDS_PORT_EN:
> >> + case HDMI_REG_AFE_DRV_CTRL:
> >> + case HDMI_REG_AFE_XP_CTRL:
> >> + case HDMI_REG_AFE_ISW_CTRL:
> >> + case HDMI_REG_AFE_IP_CTRL:
> >> + case HDMI_REG_INPUT_MODE:
> >> + case HDMI_REG_HDMI_MODE:
> >> + case HDMI_REG_GCP:
> >> + case HDMI_REG_PKT_GENERAL_CTRL:
> >> + case HDMI_REG_AVI_DB1:
> >> + case HDMI_REG_AVI_DB2:
> >> + case HDMI_REG_AVI_DB3:
> >> + case HDMI_REG_AVI_DB4:
> >> + case HDMI_REG_AVI_DB5:
> >> + case HDMI_REG_AVI_CSUM:
> >> + case HDMI_REG_AVI_DB6:
> >> + case HDMI_REG_AVI_DB7:
> >> + case HDMI_REG_AVI_DB8:
> >> + case HDMI_REG_AVI_DB9:
> >> + case HDMI_REG_AVI_DB10:
> >> + case HDMI_REG_AVI_DB11:
> >> + case HDMI_REG_AVI_DB12:
> >> + case HDMI_REG_AVI_DB13:
> >> + return true;
> >> + default:
> >> + return false;
> >> + }
> >> +}
> >> +
> >> +static bool it6263_hdmi_readable_reg(struct device *dev, unsigned
> >> +int reg) {
> >> + if (it6263_hdmi_writeable_reg(dev, reg))
> >> + return true;
> >> +
> >> + switch (reg) {
> >> + case HDMI_REG_SYS_STATUS:
> >> + case HDMI_REG_DDC_STATUS:
> >> + case HDMI_REG_DDC_READFIFO:
> >> + return true;
> >> + default:
> >> + return false;
> >> + }
> >> +}
> >> +
> >> +static bool it6263_hdmi_volatile_reg(struct device *dev, unsigned
> >> +int reg) {
> >> + switch (reg) {
> >> + case HDMI_REG_SW_RST:
> >> + case HDMI_REG_SYS_STATUS:
> >> + case HDMI_REG_DDC_STATUS:
> >> + case HDMI_REG_DDC_READFIFO:
> >> + return true;
> >> + default:
> >> + return false;
> >> + }
> >> +}
> >> +
> >> +static const struct regmap_range_cfg it6263_hdmi_range_cfg = {
> >> + .range_min = 0x00,
> >> + .range_max = HDMI_REG_AVI_DB13,
> >> + .selector_reg = HDMI_REG_BANK_CTRL,
> >> + .selector_mask = REG_BANK_SEL,
> >> + .selector_shift = 0,
> >> + .window_start = 0x00,
> >> + .window_len = 0x100,
> >> +};
> >> +
> >> +static const struct regmap_config it6263_hdmi_regmap_config = {
> >> + .name = "it6263-hdmi",
> >> + .reg_bits = 8,
> >> + .val_bits = 8,
> >> + .writeable_reg = it6263_hdmi_writeable_reg,
> >> + .readable_reg = it6263_hdmi_readable_reg,
> >> + .volatile_reg = it6263_hdmi_volatile_reg,
> >> + .max_register = HDMI_REG_AVI_DB13,
> >> + .ranges = &it6263_hdmi_range_cfg,
> >> + .num_ranges = 1,
> >> + .cache_type = REGCACHE_MAPLE,
> >> +};
> >> +
> >> +static bool it6263_lvds_writeable_reg(struct device *dev, unsigned
> >> +int reg) {
> >> + switch (reg) {
> >> + case LVDS_REG_05:
> >> + case LVDS_REG_0B:
> >> + case LVDS_REG_2C:
> >> + case LVDS_REG_3C:
> >> + case LVDS_REG_3F:
> >> + case LVDS_REG_47:
> >> + case LVDS_REG_48:
> >> + case LVDS_REG_4F:
> >> + case LVDS_REG_52:
> >> + return true;
> >> + default:
> >> + return false;
> >> + }
> >> +}
> >> +
> >> +static bool it6263_lvds_readable_reg(struct device *dev, unsigned
> >> +int reg) {
> >> + return it6263_lvds_writeable_reg(dev, reg); }
> >> +
> >> +static bool it6263_lvds_volatile_reg(struct device *dev, unsigned
> >> +int reg) {
> >> + return reg == LVDS_REG_05;
> >> +}
> >> +
> >> +static const struct regmap_config it6263_lvds_regmap_config = {
> >> + .name = "it6263-lvds",
> >> + .reg_bits = 8,
> >> + .val_bits = 8,
> >> + .writeable_reg = it6263_lvds_writeable_reg,
> >> + .readable_reg = it6263_lvds_readable_reg,
> >> + .volatile_reg = it6263_lvds_volatile_reg,
> >> + .max_register = LVDS_REG_52,
> >> + .cache_type = REGCACHE_MAPLE,
> >> +};
> >> +
> >> +static const char * const it6263_supplies[] = {
> >> + "ivdd", "ovdd", "txavcc18", "txavcc33", "pvcc1", "pvcc2",
> >> + "avcc", "anvdd", "apvdd"
> >> +};
> >> +
> >> +static int it6263_parse_dt(struct it6263 *it) {
> >> + struct device *dev = it->dev;
> >> + struct device_node *port0, *port1;
> >> + int ret;
> >> +
> >> + ret = of_property_read_u8(dev->of_node, "ite,lvds-link-num-data-lanes",
> >> + &it->lvds_link_num_dlanes);
> >> + if (ret) {
> >> + dev_err(dev, "failed to get LVDS link number of data lanes: %d\n",
> >> + ret);
> >> + return ret;
> >> + }
> >> +
> >> + it->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0);
> >> + if (IS_ERR(it->next_bridge))
> >> + return dev_err_probe(dev, PTR_ERR(it->next_bridge),
> >> + "failed to get next bridge\n");
> >> +
> >> + port0 = of_graph_get_port_by_id(dev->of_node, 0);
> >> + port1 = of_graph_get_port_by_id(dev->of_node, 1);
> >> + if (port0 && port1) {
> >> + if (of_property_read_bool(port0, "dual-lvds-even-pixels") &&
> >> + of_property_read_bool(port1, "dual-lvds-odd-pixels")) {
> >> + it->lvds_dual_link = true;
> >> + it->lvds_link12_swap = true;
> >
> > This is a nice name for the propery in the Dual Link LVDS case:
> >
> > ite,lvds-link-swap
>
> Swapping LVDS link1&2 is implied by the dual-lvds-{even,odd}-pixels properties that DT writers specify
> in port@0 and port@1.
>
> The DT writers don't need to use a dedicated property like ite,lvds-link-swap to explicitly indicate
> the swap.
>
> >
> >
> >> + } else if (of_property_read_bool(port0, "dual-lvds-odd-pixels") &&
> >> + of_property_read_bool(port1, "dual-lvds-even-pixels")) {
> >> + it->lvds_dual_link = true;
> >> + }
> >> +
> >> + if (!it->lvds_dual_link) {
> >> + dev_err(dev,
> >> + "failed to get LVDS dual link pixel order\n");
> >> + ret = -EINVAL;
> >> + }
> >> + } else if (port1) {
> >> + ret = -EINVAL;
> >> + dev_err(dev, "single input LVDS port1 is not supported\n");
> >> + } else if (!port0) {
> >> + ret = -EINVAL;
> >> + dev_err(dev, "no input LVDS port\n");
> >> + }
> >> +
> >> + of_node_put(port0);
> >> + of_node_put(port1);
> >> +
> >> + return ret;
> >> +}
> >> +
> >> +static inline void it6263_hw_reset(struct it6263 *it) {
> >> + if (!it->reset_gpio)
> >> + return;
> >> +
> >> + gpiod_set_value_cansleep(it->reset_gpio, 0);
> >> + fsleep(1000);
> >> + gpiod_set_value_cansleep(it->reset_gpio, 1);
> >> + /* The chip maker says the low pulse should be at least 40ms. */
> >> + fsleep(40000);
> >> + gpiod_set_value_cansleep(it->reset_gpio, 0);
> >> + /* addtional time to wait the high voltage to be stable */
> >> + fsleep(5000);
> >> +}
> >> +
> >> +static inline int it6263_lvds_set_i2c_addr(struct it6263 *it) {
> >> + int ret;
> >> +
> >> + ret = regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT,
> >> + LVDS_INPUT_CTRL_I2C_ADDR << 1);
> >> + if (ret)
> >> + return ret;
> >> +
> >> + return regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT_EN,
> >> +BIT(0)); }
> >> +
> >> +static inline void it6263_lvds_reset(struct it6263 *it) {
> >> + /* AFE PLL reset */
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), 0x0);
> >> + fsleep(1000);
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), BIT(0));
> >> +
> >> + /* software pixel clock domain reset */
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST,
> >> + REG_SOFT_P_RST);
> >> + fsleep(1000);
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST, 0x0);
> >> + fsleep(10000);
> >> +}
> >> +
> >> +static inline void it6263_lvds_set_interface(struct it6263 *it) {
> >> + /* color depth */
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_COL_DEP, BIT8);
> >> + /* output mapping */
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, OUT_MAP, JEIDA);
> >> +
> >> + if (it->lvds_dual_link) {
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, DISO);
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), BIT(1));
> >> + } else {
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, SISO);
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), 0);
> >> + }
> >> +}
> >> +
> >> +static inline void it6263_lvds_set_afe(struct it6263 *it) {
> >> + regmap_write(it->lvds_regmap, LVDS_REG_3C, 0xaa);
> >> + regmap_write(it->lvds_regmap, LVDS_REG_3F, 0x02);
> >> + regmap_write(it->lvds_regmap, LVDS_REG_47, 0xaa);
> >> + regmap_write(it->lvds_regmap, LVDS_REG_48, 0x02);
> >> + regmap_write(it->lvds_regmap, LVDS_REG_4F, 0x11);
> >> +
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_SSC_PCLK_RF,
> >> + REG_SSC_PCLK_RF);
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, 0x07, 0);
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_DESSC_ENB,
> >> + REG_DESSC_ENB);
> >> +}
> >> +
> >> +static inline void it6263_lvds_sys_cfg(struct it6263 *it) {
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_LVDS_IN_SWAP,
> >> + it->lvds_link12_swap ? REG_LVDS_IN_SWAP : 0); }
> >> +
> >> +static inline void it6263_lvds_config(struct it6263 *it) {
> >> + it6263_lvds_reset(it);
> >> + it6263_lvds_set_interface(it);
> >> + it6263_lvds_set_afe(it);
> >> + it6263_lvds_sys_cfg(it);
> >> +}
> >> +
> >> +static inline void it6263_hdmi_config(struct it6263 *it) {
> >> + regmap_write(it->hdmi_regmap, HDMI_REG_SW_RST, HDMI_RST_ALL);
> >> + regmap_write(it->hdmi_regmap, HDMI_REG_INPUT_MODE, IN_RGB);
> >> + regmap_write_bits(it->hdmi_regmap, HDMI_REG_GCP, HDMI_COLOR_DEPTH,
> >> + HDMI_COLOR_DEPTH_24);
> >> +}
> >> +
> >> +static enum drm_connector_status it6263_detect(struct it6263 *it) {
> >> + unsigned int val;
> >> +
> >> + regmap_read(it->hdmi_regmap, HDMI_REG_SYS_STATUS, &val);
> >> + if (val & HPDETECT)
> >> + return connector_status_connected;
> >> + else
> >> + return connector_status_disconnected; }
> >> +
> >> +static enum drm_connector_status
> >> +it6263_connector_detect(struct drm_connector *connector, bool force)
> >> +{
> >> + struct it6263 *it = connector_to_it6263(connector);
> >> +
> >> + return it6263_detect(it);
> >> +}
> >> +
> >> +static const struct drm_connector_funcs it6263_connector_funcs = {
> >> + .detect = it6263_connector_detect,
> >> + .fill_modes = drm_helper_probe_single_connector_modes,
> >> + .destroy = drm_connector_cleanup,
> >> + .reset = drm_atomic_helper_connector_reset,
> >> + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
> >> + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> >> +};
> >> +
> >> +static int it6263_read_edid(void *data, u8 *buf, unsigned int block,
> >> +size_t len) {
> >> + struct it6263 *it = data;
> >> + struct regmap *regmap = it->hdmi_regmap;
> >> + unsigned int start = (block % 2) * EDID_LENGTH;
> >> + unsigned int segment = block >> 1;
> >> + unsigned int count, val;
> >> + int ret;
> >> +
> >> + regmap_write(regmap, HDMI_REG_DDC_MASTER_CTRL, MASTER_SEL_HOST);
> >> + regmap_write(regmap, HDMI_REG_DDC_HEADER, DDC_ADDR << 1);
> >> + regmap_write(regmap, HDMI_REG_DDC_EDIDSEG, segment);
> >> +
> >> + while (len) {
> >> + /* clear DDC FIFO */
> >> + regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_FIFO_CLR);
> >> +
> >> + ret = regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS,
> >> + val, val & DDC_DONE,
> >> + 2000, 10000);
> >> + if (ret) {
> >> + dev_err(it->dev, "failed to clear DDC FIFO:%d\n", ret);
> >> + return ret;
> >> + }
> >> +
> >> + count = len > HDMI_DDC_FIFO_BYTES ? HDMI_DDC_FIFO_BYTES : len;
> >> +
> >> + /* fire the read command */
> >> + regmap_write(regmap, HDMI_REG_DDC_REQOFF, start);
> >> + regmap_write(regmap, HDMI_REG_DDC_REQCOUNT, count);
> >> + regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_EDID_READ);
> >> +
> >> + start += count;
> >> + len -= count;
> >> +
> >> + ret = regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS, val,
> >> + val & (DDC_DONE | DDC_ERROR),
> >> + 20000, 250000);
> >> + if (ret && !(val & DDC_ERROR)) {
> >> + dev_err(it->dev, "failed to read EDID:%d\n", ret);
> >> + return ret;
> >> + }
> >> +
> >> + if (val & DDC_ERROR) {
> >> + dev_err(it->dev, "DDC error\n");
> >> + return -EIO;
> >> + }
> >> +
> >> + /* cache to buffer */
> >> + for (; count > 0; count--) {
> >> + regmap_read(regmap, HDMI_REG_DDC_READFIFO, &val);
> >> + *(buf++) = val;
> >> + }
> >> + }
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static int it6263_connector_get_modes(struct drm_connector
> >> +*connector) {
> >> + struct it6263 *it = connector_to_it6263(connector);
> >> + const struct drm_edid *drm_edid;
> >> + int count;
> >> +
> >> + drm_edid = drm_edid_read_custom(connector, it6263_read_edid, it);
> >> +
> >> + drm_edid_connector_update(connector, drm_edid);
> >> + count = drm_edid_connector_add_modes(connector);
> >> +
> >> + drm_edid_free(drm_edid);
> >> +
> >> + return count;
> >> +}
> >> +
> >> +static const struct drm_connector_helper_funcs it6263_connector_helper_funcs = {
> >> + .get_modes = it6263_connector_get_modes, };
> >> +
> >> +static int it6263_bridge_atomic_check(struct drm_bridge *bridge,
> >> + struct drm_bridge_state *bridge_state,
> >> + struct drm_crtc_state *crtc_state,
> >> + struct drm_connector_state *conn_state) {
> >> + struct drm_display_mode *mode = &crtc_state->adjusted_mode;
> >
> > Use drm_atomic_helper_connector_hdmi_check().
>
> Will take a look at this.
>
> >
> > Implement .hdmi_tmds_char_rate_valid(). Also, I think, single and dual
>
> Will take a look at this.
>
> > link LVDS have different max clock rates. Please correct me if I'm
> > wrong.
>
> Yes, I think so too. But, I don't know the exact max clock rates.
> IT6263 data sheet only says LVDS RX supports clock rate up to 150MHz.
>
> >
> >> +
> >> + return mode->clock > MAX_PIXEL_CLOCK_KHZ ? -EINVAL : 0; }
> >> +
> >> +static void
> >> +it6263_bridge_atomic_disable(struct drm_bridge *bridge,
> >> + struct drm_bridge_state *old_bridge_state) {
> >> + struct it6263 *it = bridge_to_it6263(bridge);
> >> +
> >> + regmap_write_bits(it->hdmi_regmap, HDMI_REG_GCP, AVMUTE, AVMUTE);
> >> + regmap_write(it->hdmi_regmap, HDMI_REG_PKT_GENERAL_CTRL, 0);
> >> + regmap_write(it->hdmi_regmap, HDMI_REG_AFE_DRV_CTRL,
> >> + AFE_DRV_RST | AFE_DRV_PWD);
> >> +}
> >> +
> >> +static void
> >> +it6263_hdmi_avi_infoframe_configure(struct it6263 *it,
> >> + struct drm_connector *connector,
> >> + const struct drm_display_mode *mode)
> >
> > -> .hdmi_write_infoframe() , .hdmi_clear_infoframe().
>
>
> Will take a look at them.
>
> >
> >> +{
> >> + struct hdmi_avi_infoframe frame;
> >> + u8 buf[HDMI_INFOFRAME_SIZE(AVI)];
> >> + int ret;
> >> +
> >> + ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
> >> + if (ret) {
> >> + dev_err(it->dev, "failed to setup AVI infoframe: %d\n", ret);
> >> + return;
> >> + }
> >> +
> >> + ret = hdmi_avi_infoframe_pack(&frame, buf, sizeof(buf));
> >> + if (ret < 0) {
> >> + dev_err(it->dev, "failed to pack infoframe: %d\n", ret);
> >> + return;
> >> + }
> >> +
> >> + /* write the first AVI infoframe data byte chunk(DB1-DB5) */
> >> + ret = regmap_bulk_write(it->hdmi_regmap, HDMI_REG_AVI_DB1,
> >> + &buf[HDMI_INFOFRAME_HEADER_SIZE],
> >> + HDMI_AVI_DB_CHUNK1_SIZE);
> >> + if (ret) {
> >> + dev_err(it->dev, "failed to write the 1st AVI infoframe data byte chunk: %d\n",
> >> + ret);
> >> + return;
> >> + }
> >> +
> >> + /* write the second AVI infoframe data byte chunk(DB6-DB13) */
> >> + ret = regmap_bulk_write(it->hdmi_regmap, HDMI_REG_AVI_DB6,
> >> + &buf[HDMI_INFOFRAME_HEADER_SIZE +
> >> + HDMI_AVI_DB_CHUNK1_SIZE],
> >> + HDMI_AVI_DB_CHUNK2_SIZE);
> >> + if (ret) {
> >> + dev_err(it->dev, "failed to write the 2nd AVI infoframe data byte chunk: %d\n",
> >> + ret);
> >> + return;
> >> + }
> >> +
> >> + ret = regmap_write(it->hdmi_regmap, HDMI_REG_AVI_CSUM, buf[3]);
> >> + if (ret)
> >> + dev_err(it->dev, "failed to set AVI infoframe checksum: %d\n",
> >> + ret);
> >> +}
> >> +
> >> +static void
> >> +it6263_bridge_atomic_enable(struct drm_bridge *bridge,
> >> + struct drm_bridge_state *old_bridge_state) {
> >> + struct drm_atomic_state *state = old_bridge_state->base.state;
> >> + struct it6263 *it = bridge_to_it6263(bridge);
> >> + const struct drm_crtc_state *crtc_state;
> >> + struct regmap *regmap = it->hdmi_regmap;
> >> + const struct drm_display_mode *mode;
> >> + struct drm_connector *connector;
> >> + bool is_stable = false;
> >> + struct drm_crtc *crtc;
> >> + unsigned int val;
> >> + bool pclk_high;
> >> + int i, ret;
> >> +
> >> + connector = drm_atomic_get_new_connector_for_encoder(state,
> >> + bridge->encoder);
> >> + crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
> >> + crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
> >> + mode = &crtc_state->adjusted_mode;
> >> +
> >> + regmap_write(regmap, HDMI_REG_HDMI_MODE, TX_HDMI_MODE);
> >> +
> >> + it6263_hdmi_avi_infoframe_configure(it, connector, mode);
> >
> > drm_atomic_helper_connector_hdmi_update_infoframes
>
> Will take a look at this.
>
> >
> >> +
> >> + /* HDMI AFE setup */
> >> + pclk_high = mode->clock > HIGH_PIXEL_CLOCK_KHZ ? true : false;
> >> + regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, AFE_DRV_RST);
> >> + if (pclk_high)
> >> + regmap_write(regmap, HDMI_REG_AFE_XP_CTRL,
> >> + AFE_XP_GAINBIT | AFE_XP_RESETB);
> >> + else
> >> + regmap_write(regmap, HDMI_REG_AFE_XP_CTRL,
> >> + AFE_XP_ER0 | AFE_XP_RESETB);
> >> + regmap_write(regmap, HDMI_REG_AFE_ISW_CTRL, 0x10);
> >> + if (pclk_high)
> >> + regmap_write(regmap, HDMI_REG_AFE_IP_CTRL,
> >> + AFE_IP_GAINBIT | AFE_IP_RESETB);
> >> + else
> >> + regmap_write(regmap, HDMI_REG_AFE_IP_CTRL,
> >> + AFE_IP_ER0 | AFE_IP_RESETB);
> >> +
> >> + /* HDMI software video reset */
> >> + regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, SOFTV_RST);
> >> + fsleep(1000);
> >> + regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, 0);
> >> +
> >> + /* reconfigure LVDS and retry several times in case video is instable */
> >> + for (i = 0; i < 3; i++) {
> >> + ret = regmap_read_poll_timeout(regmap, HDMI_REG_SYS_STATUS, val,
> >> + val & TXVIDSTABLE,
> >> + 20000, 500000);
> >> + if (!ret) {
> >> + is_stable = true;
> >> + break;
> >> + }
> >> +
> >> + it6263_lvds_config(it);
> >> + }
> >> +
> >> + if (!is_stable)
> >> + dev_warn(it->dev, "failed to wait for video stable\n");
> >> +
> >> + /* HDMI AFE reset release and power up */
> >> + regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, 0);
> >> +
> >> + regmap_write_bits(regmap, HDMI_REG_GCP, AVMUTE, 0);
> >> +
> >> + regmap_write(regmap, HDMI_REG_PKT_GENERAL_CTRL, ENABLE_PKT |
> >> +REPEAT_PKT); }
> >> +
> >> +static enum drm_mode_status
> >> +it6263_bridge_mode_valid(struct drm_bridge *bridge,
> >> + const struct drm_display_info *info,
> >> + const struct drm_display_mode *mode) {
> >> + return mode->clock > MAX_PIXEL_CLOCK_KHZ ? MODE_CLOCK_HIGH :
> >> +MODE_OK;
> >
> > rate = drm_hdmi_compute_mode_clock(mode, 8, HDMI_COLORSPACE_RGB);
> > return bridge->funcs->hdmi_tmds_char_rate_valid(bridge, mode,
> > rate);
>
> Will look into the two lines.
>
> >
> >> +}
> >> +
> >> +static int it6263_bridge_attach(struct drm_bridge *bridge,
> >> + enum drm_bridge_attach_flags flags) {
> >> + struct it6263 *it = bridge_to_it6263(bridge);
> >> + int ret;
> >> +
> >> + ret = drm_bridge_attach(bridge->encoder, it->next_bridge, bridge,
> >> + flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
> >> + if (ret < 0)
> >> + return ret;
> >> +
> >> + if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
> >> + return 0;
> >> +
> >> + it->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
> >> + DRM_CONNECTOR_POLL_DISCONNECT;
> >> +
> >
> > Please strongly consider dropping this and using drm_bridge_connector
> > in the host driver.
>
> I can't afford to make i.MX8MP imx-lcdif KMS use drm_bridge_connector currently. Maybe the Renesas
> RZ/G3E SMARC EVK Biju tested v1 patch set with is also not using drm_bridge_connector. I hope we can
> leave it as-is for now.
Renesas platform use the drm_bridge_connector_init() helper to create a drm_connector for
each output, instead of relying on the bridge drivers doing so. It attach
the bridges with the DRM_BRIDGE_ATTACH_NO_CONNECTOR flag to instruct
them not to create a connector.
On Renesas platform, it exit from here
if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
return 0;
Maybe it is good to have both cases to start with. Add support for both cases now,
Later when imx-lcdif KMS start using drm_bridge_connector,
we can start dropping bridge devices to create connector??
Dmitry, are you ok with this?
Cheers,
Biju
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-12 9:14 ` Liu Ying
@ 2024-10-13 23:45 ` Dmitry Baryshkov
2024-10-14 5:33 ` Liu Ying
0 siblings, 1 reply; 49+ messages in thread
From: Dmitry Baryshkov @ 2024-10-13 23:45 UTC (permalink / raw)
To: Liu Ying
Cc: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel,
andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
arnd, nfraprado, o.rempel, y.moog, marex, isaac.scott,
biju.das.jz
On Sat, Oct 12, 2024 at 05:14:13PM +0800, Liu Ying wrote:
> On 10/12/2024, Dmitry Baryshkov wrote:
> > On Sat, Oct 12, 2024 at 03:35:39PM +0800, Liu Ying wrote:
> >> Document ITE IT6263 LVDS to HDMI converter.
> >>
> >> Product link:
> >> https://www.ite.com.tw/en/product/cate1/IT6263
> >>
> >> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> >> ---
> >> v2:
> >> * Document number of LVDS link data lanes. (Biju)
> >> * Simplify ports property by dropping "oneOf". (Rob)
> >>
> >> .../bindings/display/bridge/ite,it6263.yaml | 276 ++++++++++++++++++
> >> 1 file changed, 276 insertions(+)
> >> create mode 100644 Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
> >>
> >> diff --git a/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
> >> new file mode 100644
> >> index 000000000000..bc2bbec07623
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
> >> @@ -0,0 +1,276 @@
> >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >> +%YAML 1.2
> >> +---
> >> +$id: http://devicetree.org/schemas/display/bridge/ite,it6263.yaml#
> >> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >> +
> >> +title: ITE IT6263 LVDS to HDMI converter
> >> +
> >> +maintainers:
> >> + - Liu Ying <victor.liu@nxp.com>
> >> +
> >> +description: |
> >> + The IT6263 is a high-performance single-chip De-SSC(De-Spread Spectrum) LVDS
> >> + to HDMI converter. Combined with LVDS receiver and HDMI 1.4a transmitter,
> >> + the IT6263 supports LVDS input and HDMI 1.4 output by conversion function.
> >> + The built-in LVDS receiver can support single-link and dual-link LVDS inputs,
> >> + and the built-in HDMI transmitter is fully compliant with HDMI 1.4a/3D, HDCP
> >> + 1.2 and backward compatible with DVI 1.0 specification.
> >> +
> >> + The IT6263 also encodes and transmits up to 8 channels of I2S digital audio,
> >> + with sampling rate up to 192KHz and sample size up to 24 bits. In addition,
> >> + an S/PDIF input port takes in compressed audio of up to 192KHz frame rate.
> >> +
> >> + The newly supported High-Bit Rate(HBR) audio by HDMI specifications v1.3 is
> >> + provided by the IT6263 in two interfaces: the four I2S input ports or the
> >> + S/PDIF input port. With both interfaces the highest possible HBR frame rate
> >> + is supported at up to 768KHz.
> >> +
> >> +properties:
> >
> > No LVDS data-mapping support?
>
> It is enough to document number of LVDS link data lanes
> because OS should be able to determine the data-mapping
> by looking at the number and the data-mapping capability
> of the other side of the LVDS link.
From what I can see, data-mapping is specified on the consumer sink side
of the LVDS link. This means it should go to the bridge's device node.
>
> >
> >> + compatible:
> >> + const: ite,it6263
> >> +
> >> + reg:
> >> + maxItems: 1
> >> +
> >> + clocks:
> >> + maxItems: 1
> >> + description: audio master clock
> >> +
> >> + clock-names:
> >> + const: mclk
> >> +
> >> + reset-gpios:
> >> + maxItems: 1
> >> +
> >> + ivdd-supply:
> >> + description: 1.8V digital logic power
> >> +
> >> + ovdd-supply:
> >> + description: 3.3V I/O pin power
> >> +
> >> + txavcc18-supply:
> >> + description: 1.8V HDMI analog frontend power
> >> +
> >> + txavcc33-supply:
> >> + description: 3.3V HDMI analog frontend power
> >> +
> >> + pvcc1-supply:
> >> + description: 1.8V HDMI frontend core PLL power
> >> +
> >> + pvcc2-supply:
> >> + description: 1.8V HDMI frontend filter PLL power
> >> +
> >> + avcc-supply:
> >> + description: 3.3V LVDS frontend power
> >> +
> >> + anvdd-supply:
> >> + description: 1.8V LVDS frontend analog power
> >> +
> >> + apvdd-supply:
> >> + description: 1.8V LVDS frontend PLL power
> >> +
> >> + "#sound-dai-cells":
> >> + const: 0
> >> +
> >> + ite,lvds-link-num-data-lanes:
> >> + $ref: /schemas/types.yaml#/definitions/uint8
> >> + enum: [3, 4, 5]
> >> + description: number of data lanes per LVDS link
> >
> > Please use data-lanes property inside the OF graph.
>
> In both port@0 and port@1?
Yes
>
> >
> >> +
> >> + ite,i2s-audio-fifo-sources:
> >> + $ref: /schemas/types.yaml#/definitions/uint32-array
> >> + minItems: 1
> >> + maxItems: 4
> >> + items:
> >> + enum: [0, 1, 2, 3]
> >> + description:
> >> + Each array element indicates the pin number of an I2S serial data input
> >> + line which is connected to an audio FIFO, from audio FIFO0 to FIFO3.
> >
> > What does that mean from the board point of view? Routed audio links for
> > the multichannel audio?
>
> Yes, also for single channel audio.
>
> >
> >> +
> >> + ite,rl-channel-swap-audio-sources:
> >> + $ref: /schemas/types.yaml#/definitions/uint32-array
> >> + minItems: 1
> >> + maxItems: 4
> >> + uniqueItems: true
> >> + items:
> >> + enum: [0, 1, 2, 3]
> >> + description:
> >> + Each array element indicates an audio source whose right channel and left
> >> + channel are swapped by this converter. For I2S, the element is the pin
> >> + number of an I2S serial data input line. For S/PDIF, the element is always
> >> + 0.
> >
> > Why?
>
> Because this converter has the capability to swap right channel
> and left channel and S/PDIF always uses audio source0.
>
> >
> >> +
> >> + ports:
> >> + $ref: /schemas/graph.yaml#/properties/ports
> >> +
> >> + properties:
> >> + port@0:
> >> + $ref: /schemas/graph.yaml#/$defs/port-base
> >> + unevaluatedProperties: false
> >> + description:
> >> + The first LVDS input link.
> >> + In dual-link LVDS mode, this link works together with the second LVDS
> >> + input link, and one link receives odd pixels while the other receives
> >> + even pixels. Specify the pixels with one of the dual-lvds-odd-pixels
> >> + and dual-lvds-even-pixels properties when and only when dual-link LVDS
> >> + mode is used.
> >> +
> >> + properties:
> >> + dual-lvds-odd-pixels:
> >> + type: boolean
> >> + description: the first sink port for odd pixels
> >> +
> >> + dual-lvds-even-pixels:
> >> + type: boolean
> >> + description: the first sink port for even pixels
> >> +
> >> + port@1:
> >> + $ref: /schemas/graph.yaml#/$defs/port-base
> >> + unevaluatedProperties: false
> >> + description: the second LVDS input link
> >> +
> >> + properties:
> >> + dual-lvds-even-pixels:
> >> + type: boolean
> >> + description: the second sink port for even pixels
> >> +
> >> + dual-lvds-odd-pixels:
> >> + type: boolean
> >> + description: the second sink port for odd pixels
> >> +
> >> + oneOf:
> >> + - required: [dual-lvds-even-pixels]
> >> + - required: [dual-lvds-odd-pixels]
> >
> > This still allows one to specify that both ports provide odd pixels. Is
> > that expected? Also why do you need two properties which specify the
> > same option.
>
> No, that is not expected. Description for port@0 already mentions
> one link receives odd pixels while the other receives even pixels.
That's not expected, but permitted by the bindings.
>
> Two options are supported for dual-link LVDS, not the same option:
> 1) LVDS link1(port@0) gets odd pixels
> and
> LVDS link2(port@1) gets even pixels.
>
> 2) LVDS link1(port@0) gets even pixels
> and
> LVDS link2(port@1) gets odd pixels.
> That's the reason why each port needs two properties to define
> odd/even pixels.
>
> >
> > My suggestion would be to add a single root-level property which
> > specifies which port provides even pixel data.
>
> That won't work. The LVDS source side expects the ports of
> the sink side specify dual-lvds-{odd,even}-pixels properties.
I didn't notice that these properties are already defined.
As these properties are common between several schema files, please
extract them to a common schema file (like lvds.yaml).
>
> >
> >> +
> >> + port@2:
> >> + $ref: /schemas/graph.yaml#/properties/port
> >> + description: video port for the HDMI output
> >> +
> >> + port@3:
> >> + $ref: /schemas/graph.yaml#/properties/port
> >> + description: sound input port
> >> +
> >> + required:
> >> + - port@0
> >> + - port@2
> >> +
> >> +required:
> >> + - compatible
> >> + - reg
> >> + - ivdd-supply
> >> + - ovdd-supply
> >> + - txavcc18-supply
> >> + - txavcc33-supply
> >> + - pvcc1-supply
> >> + - pvcc2-supply
> >> + - avcc-supply
> >> + - anvdd-supply
> >> + - apvdd-supply
> >> + - ite,lvds-link-num-data-lanes
> >> + - ports
> >> +
> >> +additionalProperties: false
> >> +
> >> +examples:
> >> + - |
> >> + /* single-link LVDS input */
> >> + #include <dt-bindings/gpio/gpio.h>
> >> +
> >> + i2c {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + hdmi@4c {
> >> + compatible = "ite,it6263";
> >> + reg = <0x4c>;
> >> + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
> >> + ivdd-supply = <®_buck5>;
> >> + ovdd-supply = <®_vext_3v3>;
> >> + txavcc18-supply = <®_buck5>;
> >> + txavcc33-supply = <®_vext_3v3>;
> >> + pvcc1-supply = <®_buck5>;
> >> + pvcc2-supply = <®_buck5>;
> >> + avcc-supply = <®_vext_3v3>;
> >> + anvdd-supply = <®_buck5>;
> >> + apvdd-supply = <®_buck5>;
> >> + ite,lvds-link-num-data-lanes = /bits/ 8 <4>;
> >> +
> >> + ports {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + port@0 {
> >> + reg = <0>;
> >> +
> >> + it6263_lvds_link1: endpoint {
> >> + remote-endpoint = <&ldb_lvds_ch0>;
> >> + };
> >> + };
> >> +
> >> + port@2 {
> >> + reg = <2>;
> >> +
> >> + it6263_out: endpoint {
> >> + remote-endpoint = <&hdmi_in>;
> >> + };
> >> + };
> >> + };
> >> + };
> >> + };
> >> +
> >> + - |
> >> + /* dual-link LVDS input */
> >> + #include <dt-bindings/gpio/gpio.h>
> >> +
> >> + i2c {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + hdmi@4c {
> >> + compatible = "ite,it6263";
> >> + reg = <0x4c>;
> >> + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
> >> + ivdd-supply = <®_buck5>;
> >> + ovdd-supply = <®_vext_3v3>;
> >> + txavcc18-supply = <®_buck5>;
> >> + txavcc33-supply = <®_vext_3v3>;
> >> + pvcc1-supply = <®_buck5>;
> >> + pvcc2-supply = <®_buck5>;
> >> + avcc-supply = <®_vext_3v3>;
> >> + anvdd-supply = <®_buck5>;
> >> + apvdd-supply = <®_buck5>;
> >> + ite,lvds-link-num-data-lanes = /bits/ 8 <4>;
> >> +
> >> + ports {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + port@0 {
> >> + reg = <0>;
> >> + dual-lvds-odd-pixels;
> >> +
> >> + it6263_lvds_link1_dual: endpoint {
> >> + remote-endpoint = <&ldb_lvds_ch0>;
> >> + };
> >> + };
> >> +
> >> + port@1 {
> >> + reg = <1>;
> >> + dual-lvds-even-pixels;
> >> +
> >> + it6263_lvds_link2_dual: endpoint {
> >> + remote-endpoint = <&ldb_lvds_ch1>;
> >> + };
> >> + };
> >> +
> >> + port@2 {
> >> + reg = <2>;
> >> +
> >> + it6263_out_dual: endpoint {
> >> + remote-endpoint = <&hdmi_in>;
> >> + };
> >> + };
> >> + };
> >> + };
> >> + };
> >> --
> >> 2.34.1
> >>
> >
>
> --
> Regards,
> Liu Ying
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-12 10:01 ` Liu Ying
2024-10-13 10:48 ` Biju Das
@ 2024-10-13 23:58 ` Dmitry Baryshkov
1 sibling, 0 replies; 49+ messages in thread
From: Dmitry Baryshkov @ 2024-10-13 23:58 UTC (permalink / raw)
To: Liu Ying
Cc: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel,
andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
arnd, nfraprado, o.rempel, y.moog, marex, isaac.scott,
biju.das.jz
On Sat, Oct 12, 2024 at 06:01:30PM +0800, Liu Ying wrote:
> On 10/12/2024, Dmitry Baryshkov wrote:
> > On Sat, Oct 12, 2024 at 03:35:40PM +0800, Liu Ying wrote:
> >> Add basic HDMI video output support. Currently, only RGB888 output
> >> pixel format is supported. At the LVDS input side, the driver
> >> supports single LVDS link and dual LVDS links with "jeida-24" LVDS
> >> mapping.
> >>
> >> Product link:
> >> https://www.ite.com.tw/en/product/cate1/IT6263
> >>
> >> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> >> ---
> >> v2:
> >> * Add AVI inforframe support. (Maxime)
> >
> > Maxime asked to wire up the HDMI Connector framework. I have pushed the
> > patch that converts lt9611.c driver. Please implement similar changes in
> > your driver.
>
> Hmm, didn't fully get the meaning of "the new HDMI bridge infrastructure"
> maxime asked. Ok, will take a look at lt9611.c.
>
> >
> >> * Add DRM_MODE_CONNECTOR_HDMIA. (Biju)
> >> * Rename it6263_reset() to it6263_hw_reset(). (Biju)
> >> * Check number of LVDS link data lanes. (Biju)
> >>
> >> drivers/gpu/drm/bridge/Kconfig | 8 +
> >> drivers/gpu/drm/bridge/Makefile | 1 +
> >> drivers/gpu/drm/bridge/ite-it6263.c | 919 ++++++++++++++++++++++++++++
> >> 3 files changed, 928 insertions(+)
> >> create mode 100644 drivers/gpu/drm/bridge/ite-it6263.c
> >>
> >> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> >> index 3eb955333c80..93f99682a090 100644
> >> --- a/drivers/gpu/drm/bridge/Kconfig
> >> +++ b/drivers/gpu/drm/bridge/Kconfig
> >> @@ -90,6 +90,14 @@ config DRM_FSL_LDB
> >> help
> >> Support for i.MX8MP DPI-to-LVDS on-SoC encoder.
> >>
> >> +config DRM_ITE_IT6263
> >> + tristate "ITE IT6263 LVDS/HDMI bridge"
> >> + depends on OF
> >> + select DRM_KMS_HELPER
> >> + select REGMAP_I2C
> >> + help
> >> + ITE IT6263 LVDS to HDMI bridge chip driver.
> >> +
> >> config DRM_ITE_IT6505
> >> tristate "ITE IT6505 DisplayPort bridge"
> >> depends on OF
> >> diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
> >> index 7df87b582dca..f3776dd473fd 100644
> >> --- a/drivers/gpu/drm/bridge/Makefile
> >> +++ b/drivers/gpu/drm/bridge/Makefile
> >> @@ -6,6 +6,7 @@ obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
> >> obj-$(CONFIG_DRM_CROS_EC_ANX7688) += cros-ec-anx7688.o
> >> obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
> >> obj-$(CONFIG_DRM_FSL_LDB) += fsl-ldb.o
> >> +obj-$(CONFIG_DRM_ITE_IT6263) += ite-it6263.o
> >> obj-$(CONFIG_DRM_ITE_IT6505) += ite-it6505.o
> >> obj-$(CONFIG_DRM_LONTIUM_LT8912B) += lontium-lt8912b.o
> >> obj-$(CONFIG_DRM_LONTIUM_LT9211) += lontium-lt9211.o
> >> diff --git a/drivers/gpu/drm/bridge/ite-it6263.c b/drivers/gpu/drm/bridge/ite-it6263.c
> >> new file mode 100644
> >> index 000000000000..9b3318792f15
> >> --- /dev/null
> >> +++ b/drivers/gpu/drm/bridge/ite-it6263.c
> >> @@ -0,0 +1,919 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +/*
> >> + * Copyright 2024 NXP
> >> + */
> >> +
> >> +#include <linux/bitfield.h>
> >> +#include <linux/bits.h>
> >> +#include <linux/delay.h>
> >> +#include <linux/gpio/consumer.h>
> >> +#include <linux/hdmi.h>
> >> +#include <linux/i2c.h>
> >> +#include <linux/media-bus-format.h>
> >> +#include <linux/module.h>
> >> +#include <linux/of.h>
> >> +#include <linux/regmap.h>
> >> +#include <linux/regulator/consumer.h>
> >> +
> >> +#include <drm/drm_atomic.h>
> >> +#include <drm/drm_atomic_helper.h>
> >> +#include <drm/drm_atomic_state_helper.h>
> >> +#include <drm/drm_bridge.h>
> >> +#include <drm/drm_connector.h>
> >> +#include <drm/drm_crtc.h>
> >> +#include <drm/drm_edid.h>
> >> +#include <drm/drm_of.h>
> >> +#include <drm/drm_probe_helper.h>
> >> +
> >> +/* -----------------------------------------------------------------------------
> >> + * LVDS registers
> >> + */
> >> +
> >> +/* LVDS software reset registers */
> >> +#define LVDS_REG_05 0x05
> >> +#define REG_SOFT_P_RST BIT(1)
> >> +
> >> +/* LVDS system configuration registers */
> >> +/* 0x0b */
> >> +#define LVDS_REG_0B 0x0b
> >> +#define REG_SSC_PCLK_RF BIT(0)
> >> +#define REG_LVDS_IN_SWAP BIT(1)
> >> +
> >> +/* LVDS test pattern gen control registers */
> >> +/* 0x2c */
> >> +#define LVDS_REG_2C 0x2c
> >> +#define REG_COL_DEP GENMASK(1, 0)
> >> +#define BIT8 FIELD_PREP(REG_COL_DEP, 2)
> >> +#define OUT_MAP BIT(4)
> >> +#define JEIDA 0
> >> +#define REG_DESSC_ENB BIT(6)
> >> +#define DMODE BIT(7)
> >> +#define DISO BIT(7)
> >> +#define SISO 0
> >> +
> >> +#define LVDS_REG_3C 0x3c
> >> +#define LVDS_REG_3F 0x3f
> >> +#define LVDS_REG_47 0x47
> >> +#define LVDS_REG_48 0x48
> >> +#define LVDS_REG_4F 0x4f
> >> +#define LVDS_REG_52 0x52
> >> +
> >> +/* -----------------------------------------------------------------------------
> >> + * HDMI registers are separated into three banks:
> >> + * 1) HDMI register common bank: 0x00 ~ 0x2f
> >> + */
> >> +
> >> +/* HDMI genernal registers */
> >> +#define HDMI_REG_SW_RST 0x04
> >> +#define SOFTREF_RST BIT(5)
> >> +#define SOFTA_RST BIT(4)
> >> +#define SOFTV_RST BIT(3)
> >> +#define AUD_RST BIT(2)
> >> +#define HDCP_RST BIT(0)
> >> +#define HDMI_RST_ALL (SOFTREF_RST | SOFTA_RST | SOFTV_RST | \
> >> + AUD_RST | HDCP_RST)
> >> +
> >> +#define HDMI_REG_SYS_STATUS 0x0e
> >> +#define HPDETECT BIT(6)
> >> +#define TXVIDSTABLE BIT(4)
> >> +
> >> +#define HDMI_REG_BANK_CTRL 0x0f
> >> +#define REG_BANK_SEL BIT(0)
> >> +
> >> +/* HDMI System DDC control registers */
> >> +#define HDMI_REG_DDC_MASTER_CTRL 0x10
> >> +#define MASTER_SEL_HOST BIT(0)
> >> +
> >> +#define HDMI_REG_DDC_HEADER 0x11
> >> +
> >> +#define HDMI_REG_DDC_REQOFF 0x12
> >> +#define HDMI_REG_DDC_REQCOUNT 0x13
> >> +#define HDMI_REG_DDC_EDIDSEG 0x14
> >> +
> >> +#define HDMI_REG_DDC_CMD 0x15
> >> +#define DDC_CMD_EDID_READ 0x3
> >> +#define DDC_CMD_FIFO_CLR 0x9
> >> +
> >> +#define HDMI_REG_DDC_STATUS 0x16
> >> +#define DDC_DONE BIT(7)
> >> +#define DDC_NOACK BIT(5)
> >> +#define DDC_WAITBUS BIT(4)
> >> +#define DDC_ARBILOSE BIT(3)
> >> +#define DDC_ERROR (DDC_NOACK | DDC_WAITBUS | DDC_ARBILOSE)
> >> +
> >> +#define HDMI_DDC_FIFO_BYTES 32
> >> +#define HDMI_REG_DDC_READFIFO 0x17
> >> +#define HDMI_REG_LVDS_PORT 0x1d /* LVDS input control I2C addr */
> >> +#define HDMI_REG_LVDS_PORT_EN 0x1e
> >> +#define LVDS_INPUT_CTRL_I2C_ADDR 0x33
> >> +
> >> +/* -----------------------------------------------------------------------------
> >> + * 2) HDMI register bank0: 0x30 ~ 0xff
> >> + */
> >> +
> >> +/* HDMI AFE registers */
> >> +#define HDMI_REG_AFE_DRV_CTRL 0x61
> >> +#define AFE_DRV_PWD BIT(5)
> >> +#define AFE_DRV_RST BIT(4)
> >> +
> >> +#define HDMI_REG_AFE_XP_CTRL 0x62
> >> +#define AFE_XP_GAINBIT BIT(7)
> >> +#define AFE_XP_ER0 BIT(4)
> >> +#define AFE_XP_RESETB BIT(3)
> >> +
> >> +#define HDMI_REG_AFE_ISW_CTRL 0x63
> >> +
> >> +#define HDMI_REG_AFE_IP_CTRL 0x64
> >> +#define AFE_IP_GAINBIT BIT(7)
> >> +#define AFE_IP_ER0 BIT(3)
> >> +#define AFE_IP_RESETB BIT(2)
> >> +
> >> +/* HDMI input data format registers */
> >> +#define HDMI_REG_INPUT_MODE 0x70
> >> +#define IN_RGB 0x00
> >> +
> >> +/* HDMI general control registers */
> >> +#define HDMI_REG_HDMI_MODE 0xc0
> >> +#define TX_HDMI_MODE BIT(0)
> >> +
> >> +#define HDMI_REG_GCP 0xc1
> >> +#define AVMUTE BIT(0)
> >> +#define HDMI_COLOR_DEPTH GENMASK(6, 4)
> >> +#define HDMI_COLOR_DEPTH_24 FIELD_PREP(HDMI_COLOR_DEPTH, 4)
> >> +
> >> +#define HDMI_REG_PKT_GENERAL_CTRL 0xc6
> >> +#define ENABLE_PKT BIT(0)
> >> +#define REPEAT_PKT BIT(1)
> >> +
> >> +/* -----------------------------------------------------------------------------
> >> + * 3) HDMI register bank1: 0x130 ~ 0x1ff (HDMI packet registers)
> >> + */
> >> +
> >> +/* AVI packet registers */
> >> +#define HDMI_REG_AVI_DB1 0x158
> >> +#define HDMI_REG_AVI_DB2 0x159
> >> +#define HDMI_REG_AVI_DB3 0x15a
> >> +#define HDMI_REG_AVI_DB4 0x15b
> >> +#define HDMI_REG_AVI_DB5 0x15c
> >> +#define HDMI_REG_AVI_CSUM 0x15d
> >> +#define HDMI_REG_AVI_DB6 0x15e
> >> +#define HDMI_REG_AVI_DB7 0x15f
> >> +#define HDMI_REG_AVI_DB8 0x160
> >> +#define HDMI_REG_AVI_DB9 0x161
> >> +#define HDMI_REG_AVI_DB10 0x162
> >> +#define HDMI_REG_AVI_DB11 0x163
> >> +#define HDMI_REG_AVI_DB12 0x164
> >> +#define HDMI_REG_AVI_DB13 0x165
> >> +
> >> +#define HDMI_AVI_DB_CHUNK1_SIZE (HDMI_REG_AVI_DB5 - HDMI_REG_AVI_DB1 + 1)
> >> +#define HDMI_AVI_DB_CHUNK2_SIZE (HDMI_REG_AVI_DB13 - HDMI_REG_AVI_DB6 + 1)
> >> +
> >> +#define MAX_PIXEL_CLOCK_KHZ 150000
> >> +#define HIGH_PIXEL_CLOCK_KHZ 80000
> >> +
> >> +struct it6263 {
> >> + struct device *dev;
> >> + struct i2c_client *hdmi_i2c;
> >> + struct i2c_client *lvds_i2c;
> >> + struct regmap *hdmi_regmap;
> >> + struct regmap *lvds_regmap;
> >> + struct drm_bridge bridge;
> >> + struct drm_bridge *next_bridge;
> >> + struct drm_connector connector;
> >> + struct gpio_desc *reset_gpio;
> >> + u8 lvds_link_num_dlanes;
> >> + bool lvds_dual_link;
> >> + bool lvds_link12_swap;
> >> +};
> >> +
> >> +static inline struct it6263 *bridge_to_it6263(struct drm_bridge *bridge)
> >> +{
> >> + return container_of(bridge, struct it6263, bridge);
> >> +}
> >> +
> >> +static inline struct it6263 *connector_to_it6263(struct drm_connector *conn)
> >> +{
> >> + return container_of(conn, struct it6263, connector);
> >> +}
> >> +
> >> +static bool it6263_hdmi_writeable_reg(struct device *dev, unsigned int reg)
> >> +{
> >> + switch (reg) {
> >> + case HDMI_REG_SW_RST:
> >> + case HDMI_REG_BANK_CTRL:
> >> + case HDMI_REG_DDC_MASTER_CTRL:
> >> + case HDMI_REG_DDC_HEADER:
> >> + case HDMI_REG_DDC_REQOFF:
> >> + case HDMI_REG_DDC_REQCOUNT:
> >> + case HDMI_REG_DDC_EDIDSEG:
> >> + case HDMI_REG_DDC_CMD:
> >> + case HDMI_REG_LVDS_PORT:
> >> + case HDMI_REG_LVDS_PORT_EN:
> >> + case HDMI_REG_AFE_DRV_CTRL:
> >> + case HDMI_REG_AFE_XP_CTRL:
> >> + case HDMI_REG_AFE_ISW_CTRL:
> >> + case HDMI_REG_AFE_IP_CTRL:
> >> + case HDMI_REG_INPUT_MODE:
> >> + case HDMI_REG_HDMI_MODE:
> >> + case HDMI_REG_GCP:
> >> + case HDMI_REG_PKT_GENERAL_CTRL:
> >> + case HDMI_REG_AVI_DB1:
> >> + case HDMI_REG_AVI_DB2:
> >> + case HDMI_REG_AVI_DB3:
> >> + case HDMI_REG_AVI_DB4:
> >> + case HDMI_REG_AVI_DB5:
> >> + case HDMI_REG_AVI_CSUM:
> >> + case HDMI_REG_AVI_DB6:
> >> + case HDMI_REG_AVI_DB7:
> >> + case HDMI_REG_AVI_DB8:
> >> + case HDMI_REG_AVI_DB9:
> >> + case HDMI_REG_AVI_DB10:
> >> + case HDMI_REG_AVI_DB11:
> >> + case HDMI_REG_AVI_DB12:
> >> + case HDMI_REG_AVI_DB13:
> >> + return true;
> >> + default:
> >> + return false;
> >> + }
> >> +}
> >> +
> >> +static bool it6263_hdmi_readable_reg(struct device *dev, unsigned int reg)
> >> +{
> >> + if (it6263_hdmi_writeable_reg(dev, reg))
> >> + return true;
> >> +
> >> + switch (reg) {
> >> + case HDMI_REG_SYS_STATUS:
> >> + case HDMI_REG_DDC_STATUS:
> >> + case HDMI_REG_DDC_READFIFO:
> >> + return true;
> >> + default:
> >> + return false;
> >> + }
> >> +}
> >> +
> >> +static bool it6263_hdmi_volatile_reg(struct device *dev, unsigned int reg)
> >> +{
> >> + switch (reg) {
> >> + case HDMI_REG_SW_RST:
> >> + case HDMI_REG_SYS_STATUS:
> >> + case HDMI_REG_DDC_STATUS:
> >> + case HDMI_REG_DDC_READFIFO:
> >> + return true;
> >> + default:
> >> + return false;
> >> + }
> >> +}
> >> +
> >> +static const struct regmap_range_cfg it6263_hdmi_range_cfg = {
> >> + .range_min = 0x00,
> >> + .range_max = HDMI_REG_AVI_DB13,
> >> + .selector_reg = HDMI_REG_BANK_CTRL,
> >> + .selector_mask = REG_BANK_SEL,
> >> + .selector_shift = 0,
> >> + .window_start = 0x00,
> >> + .window_len = 0x100,
> >> +};
> >> +
> >> +static const struct regmap_config it6263_hdmi_regmap_config = {
> >> + .name = "it6263-hdmi",
> >> + .reg_bits = 8,
> >> + .val_bits = 8,
> >> + .writeable_reg = it6263_hdmi_writeable_reg,
> >> + .readable_reg = it6263_hdmi_readable_reg,
> >> + .volatile_reg = it6263_hdmi_volatile_reg,
> >> + .max_register = HDMI_REG_AVI_DB13,
> >> + .ranges = &it6263_hdmi_range_cfg,
> >> + .num_ranges = 1,
> >> + .cache_type = REGCACHE_MAPLE,
> >> +};
> >> +
> >> +static bool it6263_lvds_writeable_reg(struct device *dev, unsigned int reg)
> >> +{
> >> + switch (reg) {
> >> + case LVDS_REG_05:
> >> + case LVDS_REG_0B:
> >> + case LVDS_REG_2C:
> >> + case LVDS_REG_3C:
> >> + case LVDS_REG_3F:
> >> + case LVDS_REG_47:
> >> + case LVDS_REG_48:
> >> + case LVDS_REG_4F:
> >> + case LVDS_REG_52:
> >> + return true;
> >> + default:
> >> + return false;
> >> + }
> >> +}
> >> +
> >> +static bool it6263_lvds_readable_reg(struct device *dev, unsigned int reg)
> >> +{
> >> + return it6263_lvds_writeable_reg(dev, reg);
> >> +}
> >> +
> >> +static bool it6263_lvds_volatile_reg(struct device *dev, unsigned int reg)
> >> +{
> >> + return reg == LVDS_REG_05;
> >> +}
> >> +
> >> +static const struct regmap_config it6263_lvds_regmap_config = {
> >> + .name = "it6263-lvds",
> >> + .reg_bits = 8,
> >> + .val_bits = 8,
> >> + .writeable_reg = it6263_lvds_writeable_reg,
> >> + .readable_reg = it6263_lvds_readable_reg,
> >> + .volatile_reg = it6263_lvds_volatile_reg,
> >> + .max_register = LVDS_REG_52,
> >> + .cache_type = REGCACHE_MAPLE,
> >> +};
> >> +
> >> +static const char * const it6263_supplies[] = {
> >> + "ivdd", "ovdd", "txavcc18", "txavcc33", "pvcc1", "pvcc2",
> >> + "avcc", "anvdd", "apvdd"
> >> +};
> >> +
> >> +static int it6263_parse_dt(struct it6263 *it)
> >> +{
> >> + struct device *dev = it->dev;
> >> + struct device_node *port0, *port1;
> >> + int ret;
> >> +
> >> + ret = of_property_read_u8(dev->of_node, "ite,lvds-link-num-data-lanes",
> >> + &it->lvds_link_num_dlanes);
> >> + if (ret) {
> >> + dev_err(dev, "failed to get LVDS link number of data lanes: %d\n",
> >> + ret);
> >> + return ret;
> >> + }
> >> +
> >> + it->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0);
> >> + if (IS_ERR(it->next_bridge))
> >> + return dev_err_probe(dev, PTR_ERR(it->next_bridge),
> >> + "failed to get next bridge\n");
> >> +
> >> + port0 = of_graph_get_port_by_id(dev->of_node, 0);
> >> + port1 = of_graph_get_port_by_id(dev->of_node, 1);
> >> + if (port0 && port1) {
> >> + if (of_property_read_bool(port0, "dual-lvds-even-pixels") &&
> >> + of_property_read_bool(port1, "dual-lvds-odd-pixels")) {
> >> + it->lvds_dual_link = true;
> >> + it->lvds_link12_swap = true;
> >
> > This is a nice name for the propery in the Dual Link LVDS case:
> >
> > ite,lvds-link-swap
>
> Swapping LVDS link1&2 is implied by the dual-lvds-{even,odd}-pixels
> properties that DT writers specify in port@0 and port@1.
>
> The DT writers don't need to use a dedicated property like
> ite,lvds-link-swap to explicitly indicate the swap.
Ack
>
> >
> >
> >> + } else if (of_property_read_bool(port0, "dual-lvds-odd-pixels") &&
> >> + of_property_read_bool(port1, "dual-lvds-even-pixels")) {
> >> + it->lvds_dual_link = true;
> >> + }
> >> +
> >> + if (!it->lvds_dual_link) {
> >> + dev_err(dev,
> >> + "failed to get LVDS dual link pixel order\n");
> >> + ret = -EINVAL;
> >> + }
> >> + } else if (port1) {
> >> + ret = -EINVAL;
> >> + dev_err(dev, "single input LVDS port1 is not supported\n");
> >> + } else if (!port0) {
> >> + ret = -EINVAL;
> >> + dev_err(dev, "no input LVDS port\n");
> >> + }
> >> +
> >> + of_node_put(port0);
> >> + of_node_put(port1);
> >> +
> >> + return ret;
> >> +}
> >> +
> >> +static inline void it6263_hw_reset(struct it6263 *it)
> >> +{
> >> + if (!it->reset_gpio)
> >> + return;
> >> +
> >> + gpiod_set_value_cansleep(it->reset_gpio, 0);
> >> + fsleep(1000);
> >> + gpiod_set_value_cansleep(it->reset_gpio, 1);
> >> + /* The chip maker says the low pulse should be at least 40ms. */
> >> + fsleep(40000);
> >> + gpiod_set_value_cansleep(it->reset_gpio, 0);
> >> + /* addtional time to wait the high voltage to be stable */
> >> + fsleep(5000);
> >> +}
> >> +
> >> +static inline int it6263_lvds_set_i2c_addr(struct it6263 *it)
> >> +{
> >> + int ret;
> >> +
> >> + ret = regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT,
> >> + LVDS_INPUT_CTRL_I2C_ADDR << 1);
> >> + if (ret)
> >> + return ret;
> >> +
> >> + return regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT_EN, BIT(0));
> >> +}
> >> +
> >> +static inline void it6263_lvds_reset(struct it6263 *it)
> >> +{
> >> + /* AFE PLL reset */
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), 0x0);
> >> + fsleep(1000);
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), BIT(0));
> >> +
> >> + /* software pixel clock domain reset */
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST,
> >> + REG_SOFT_P_RST);
> >> + fsleep(1000);
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST, 0x0);
> >> + fsleep(10000);
> >> +}
> >> +
> >> +static inline void it6263_lvds_set_interface(struct it6263 *it)
> >> +{
> >> + /* color depth */
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_COL_DEP, BIT8);
> >> + /* output mapping */
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, OUT_MAP, JEIDA);
> >> +
> >> + if (it->lvds_dual_link) {
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, DISO);
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), BIT(1));
> >> + } else {
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, SISO);
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), 0);
> >> + }
> >> +}
> >> +
> >> +static inline void it6263_lvds_set_afe(struct it6263 *it)
> >> +{
> >> + regmap_write(it->lvds_regmap, LVDS_REG_3C, 0xaa);
> >> + regmap_write(it->lvds_regmap, LVDS_REG_3F, 0x02);
> >> + regmap_write(it->lvds_regmap, LVDS_REG_47, 0xaa);
> >> + regmap_write(it->lvds_regmap, LVDS_REG_48, 0x02);
> >> + regmap_write(it->lvds_regmap, LVDS_REG_4F, 0x11);
> >> +
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_SSC_PCLK_RF,
> >> + REG_SSC_PCLK_RF);
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, 0x07, 0);
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_DESSC_ENB,
> >> + REG_DESSC_ENB);
> >> +}
> >> +
> >> +static inline void it6263_lvds_sys_cfg(struct it6263 *it)
> >> +{
> >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_LVDS_IN_SWAP,
> >> + it->lvds_link12_swap ? REG_LVDS_IN_SWAP : 0);
> >> +}
> >> +
> >> +static inline void it6263_lvds_config(struct it6263 *it)
> >> +{
> >> + it6263_lvds_reset(it);
> >> + it6263_lvds_set_interface(it);
> >> + it6263_lvds_set_afe(it);
> >> + it6263_lvds_sys_cfg(it);
> >> +}
> >> +
> >> +static inline void it6263_hdmi_config(struct it6263 *it)
> >> +{
> >> + regmap_write(it->hdmi_regmap, HDMI_REG_SW_RST, HDMI_RST_ALL);
> >> + regmap_write(it->hdmi_regmap, HDMI_REG_INPUT_MODE, IN_RGB);
> >> + regmap_write_bits(it->hdmi_regmap, HDMI_REG_GCP, HDMI_COLOR_DEPTH,
> >> + HDMI_COLOR_DEPTH_24);
> >> +}
> >> +
> >> +static enum drm_connector_status it6263_detect(struct it6263 *it)
> >> +{
> >> + unsigned int val;
> >> +
> >> + regmap_read(it->hdmi_regmap, HDMI_REG_SYS_STATUS, &val);
> >> + if (val & HPDETECT)
> >> + return connector_status_connected;
> >> + else
> >> + return connector_status_disconnected;
> >> +}
> >> +
> >> +static enum drm_connector_status
> >> +it6263_connector_detect(struct drm_connector *connector, bool force)
> >> +{
> >> + struct it6263 *it = connector_to_it6263(connector);
> >> +
> >> + return it6263_detect(it);
> >> +}
> >> +
> >> +static const struct drm_connector_funcs it6263_connector_funcs = {
> >> + .detect = it6263_connector_detect,
> >> + .fill_modes = drm_helper_probe_single_connector_modes,
> >> + .destroy = drm_connector_cleanup,
> >> + .reset = drm_atomic_helper_connector_reset,
> >> + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
> >> + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> >> +};
> >> +
> >> +static int it6263_read_edid(void *data, u8 *buf, unsigned int block, size_t len)
> >> +{
> >> + struct it6263 *it = data;
> >> + struct regmap *regmap = it->hdmi_regmap;
> >> + unsigned int start = (block % 2) * EDID_LENGTH;
> >> + unsigned int segment = block >> 1;
> >> + unsigned int count, val;
> >> + int ret;
> >> +
> >> + regmap_write(regmap, HDMI_REG_DDC_MASTER_CTRL, MASTER_SEL_HOST);
> >> + regmap_write(regmap, HDMI_REG_DDC_HEADER, DDC_ADDR << 1);
> >> + regmap_write(regmap, HDMI_REG_DDC_EDIDSEG, segment);
> >> +
> >> + while (len) {
> >> + /* clear DDC FIFO */
> >> + regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_FIFO_CLR);
> >> +
> >> + ret = regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS,
> >> + val, val & DDC_DONE,
> >> + 2000, 10000);
> >> + if (ret) {
> >> + dev_err(it->dev, "failed to clear DDC FIFO:%d\n", ret);
> >> + return ret;
> >> + }
> >> +
> >> + count = len > HDMI_DDC_FIFO_BYTES ? HDMI_DDC_FIFO_BYTES : len;
> >> +
> >> + /* fire the read command */
> >> + regmap_write(regmap, HDMI_REG_DDC_REQOFF, start);
> >> + regmap_write(regmap, HDMI_REG_DDC_REQCOUNT, count);
> >> + regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_EDID_READ);
> >> +
> >> + start += count;
> >> + len -= count;
> >> +
> >> + ret = regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS, val,
> >> + val & (DDC_DONE | DDC_ERROR),
> >> + 20000, 250000);
> >> + if (ret && !(val & DDC_ERROR)) {
> >> + dev_err(it->dev, "failed to read EDID:%d\n", ret);
> >> + return ret;
> >> + }
> >> +
> >> + if (val & DDC_ERROR) {
> >> + dev_err(it->dev, "DDC error\n");
> >> + return -EIO;
> >> + }
> >> +
> >> + /* cache to buffer */
> >> + for (; count > 0; count--) {
> >> + regmap_read(regmap, HDMI_REG_DDC_READFIFO, &val);
> >> + *(buf++) = val;
> >> + }
> >> + }
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static int it6263_connector_get_modes(struct drm_connector *connector)
> >> +{
> >> + struct it6263 *it = connector_to_it6263(connector);
> >> + const struct drm_edid *drm_edid;
> >> + int count;
> >> +
> >> + drm_edid = drm_edid_read_custom(connector, it6263_read_edid, it);
> >> +
> >> + drm_edid_connector_update(connector, drm_edid);
> >> + count = drm_edid_connector_add_modes(connector);
> >> +
> >> + drm_edid_free(drm_edid);
> >> +
> >> + return count;
> >> +}
> >> +
> >> +static const struct drm_connector_helper_funcs it6263_connector_helper_funcs = {
> >> + .get_modes = it6263_connector_get_modes,
> >> +};
> >> +
> >> +static int it6263_bridge_atomic_check(struct drm_bridge *bridge,
> >> + struct drm_bridge_state *bridge_state,
> >> + struct drm_crtc_state *crtc_state,
> >> + struct drm_connector_state *conn_state)
> >> +{
> >> + struct drm_display_mode *mode = &crtc_state->adjusted_mode;
> >
> > Use drm_atomic_helper_connector_hdmi_check().
>
> Will take a look at this.
>
> >
> > Implement .hdmi_tmds_char_rate_valid(). Also, I think, single and dual
>
> Will take a look at this.
>
> > link LVDS have different max clock rates. Please correct me if I'm
> > wrong.
>
> Yes, I think so too. But, I don't know the exact max clock rates.
> IT6263 data sheet only says LVDS RX supports clock rate up to
> 150MHz.
Is this the mode clock or the LVDS link clock rate?
>
> >
> >> +
> >> + return mode->clock > MAX_PIXEL_CLOCK_KHZ ? -EINVAL : 0;
> >> +}
> >> +
> >> +static void
> >> +it6263_bridge_atomic_disable(struct drm_bridge *bridge,
> >> + struct drm_bridge_state *old_bridge_state)
> >> +{
> >> + struct it6263 *it = bridge_to_it6263(bridge);
> >> +
> >> + regmap_write_bits(it->hdmi_regmap, HDMI_REG_GCP, AVMUTE, AVMUTE);
> >> + regmap_write(it->hdmi_regmap, HDMI_REG_PKT_GENERAL_CTRL, 0);
> >> + regmap_write(it->hdmi_regmap, HDMI_REG_AFE_DRV_CTRL,
> >> + AFE_DRV_RST | AFE_DRV_PWD);
> >> +}
> >> +
> >> +static void
> >> +it6263_hdmi_avi_infoframe_configure(struct it6263 *it,
> >> + struct drm_connector *connector,
> >> + const struct drm_display_mode *mode)
> >
> > -> .hdmi_write_infoframe() , .hdmi_clear_infoframe().
>
>
> Will take a look at them.
>
> >
> >> +{
> >> + struct hdmi_avi_infoframe frame;
> >> + u8 buf[HDMI_INFOFRAME_SIZE(AVI)];
> >> + int ret;
> >> +
> >> + ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
> >> + if (ret) {
> >> + dev_err(it->dev, "failed to setup AVI infoframe: %d\n", ret);
> >> + return;
> >> + }
> >> +
> >> + ret = hdmi_avi_infoframe_pack(&frame, buf, sizeof(buf));
> >> + if (ret < 0) {
> >> + dev_err(it->dev, "failed to pack infoframe: %d\n", ret);
> >> + return;
> >> + }
> >> +
> >> + /* write the first AVI infoframe data byte chunk(DB1-DB5) */
> >> + ret = regmap_bulk_write(it->hdmi_regmap, HDMI_REG_AVI_DB1,
> >> + &buf[HDMI_INFOFRAME_HEADER_SIZE],
> >> + HDMI_AVI_DB_CHUNK1_SIZE);
> >> + if (ret) {
> >> + dev_err(it->dev, "failed to write the 1st AVI infoframe data byte chunk: %d\n",
> >> + ret);
> >> + return;
> >> + }
> >> +
> >> + /* write the second AVI infoframe data byte chunk(DB6-DB13) */
> >> + ret = regmap_bulk_write(it->hdmi_regmap, HDMI_REG_AVI_DB6,
> >> + &buf[HDMI_INFOFRAME_HEADER_SIZE +
> >> + HDMI_AVI_DB_CHUNK1_SIZE],
> >> + HDMI_AVI_DB_CHUNK2_SIZE);
> >> + if (ret) {
> >> + dev_err(it->dev, "failed to write the 2nd AVI infoframe data byte chunk: %d\n",
> >> + ret);
> >> + return;
> >> + }
> >> +
> >> + ret = regmap_write(it->hdmi_regmap, HDMI_REG_AVI_CSUM, buf[3]);
> >> + if (ret)
> >> + dev_err(it->dev, "failed to set AVI infoframe checksum: %d\n",
> >> + ret);
> >> +}
> >> +
> >> +static void
> >> +it6263_bridge_atomic_enable(struct drm_bridge *bridge,
> >> + struct drm_bridge_state *old_bridge_state)
> >> +{
> >> + struct drm_atomic_state *state = old_bridge_state->base.state;
> >> + struct it6263 *it = bridge_to_it6263(bridge);
> >> + const struct drm_crtc_state *crtc_state;
> >> + struct regmap *regmap = it->hdmi_regmap;
> >> + const struct drm_display_mode *mode;
> >> + struct drm_connector *connector;
> >> + bool is_stable = false;
> >> + struct drm_crtc *crtc;
> >> + unsigned int val;
> >> + bool pclk_high;
> >> + int i, ret;
> >> +
> >> + connector = drm_atomic_get_new_connector_for_encoder(state,
> >> + bridge->encoder);
> >> + crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
> >> + crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
> >> + mode = &crtc_state->adjusted_mode;
> >> +
> >> + regmap_write(regmap, HDMI_REG_HDMI_MODE, TX_HDMI_MODE);
> >> +
> >> + it6263_hdmi_avi_infoframe_configure(it, connector, mode);
> >
> > drm_atomic_helper_connector_hdmi_update_infoframes
>
> Will take a look at this.
>
> >
> >> +
> >> + /* HDMI AFE setup */
> >> + pclk_high = mode->clock > HIGH_PIXEL_CLOCK_KHZ ? true : false;
> >> + regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, AFE_DRV_RST);
> >> + if (pclk_high)
> >> + regmap_write(regmap, HDMI_REG_AFE_XP_CTRL,
> >> + AFE_XP_GAINBIT | AFE_XP_RESETB);
> >> + else
> >> + regmap_write(regmap, HDMI_REG_AFE_XP_CTRL,
> >> + AFE_XP_ER0 | AFE_XP_RESETB);
> >> + regmap_write(regmap, HDMI_REG_AFE_ISW_CTRL, 0x10);
> >> + if (pclk_high)
> >> + regmap_write(regmap, HDMI_REG_AFE_IP_CTRL,
> >> + AFE_IP_GAINBIT | AFE_IP_RESETB);
> >> + else
> >> + regmap_write(regmap, HDMI_REG_AFE_IP_CTRL,
> >> + AFE_IP_ER0 | AFE_IP_RESETB);
> >> +
> >> + /* HDMI software video reset */
> >> + regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, SOFTV_RST);
> >> + fsleep(1000);
> >> + regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, 0);
> >> +
> >> + /* reconfigure LVDS and retry several times in case video is instable */
> >> + for (i = 0; i < 3; i++) {
> >> + ret = regmap_read_poll_timeout(regmap, HDMI_REG_SYS_STATUS, val,
> >> + val & TXVIDSTABLE,
> >> + 20000, 500000);
> >> + if (!ret) {
> >> + is_stable = true;
> >> + break;
> >> + }
> >> +
> >> + it6263_lvds_config(it);
> >> + }
> >> +
> >> + if (!is_stable)
> >> + dev_warn(it->dev, "failed to wait for video stable\n");
> >> +
> >> + /* HDMI AFE reset release and power up */
> >> + regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, 0);
> >> +
> >> + regmap_write_bits(regmap, HDMI_REG_GCP, AVMUTE, 0);
> >> +
> >> + regmap_write(regmap, HDMI_REG_PKT_GENERAL_CTRL, ENABLE_PKT | REPEAT_PKT);
> >> +}
> >> +
> >> +static enum drm_mode_status
> >> +it6263_bridge_mode_valid(struct drm_bridge *bridge,
> >> + const struct drm_display_info *info,
> >> + const struct drm_display_mode *mode)
> >> +{
> >> + return mode->clock > MAX_PIXEL_CLOCK_KHZ ? MODE_CLOCK_HIGH : MODE_OK;
> >
> > rate = drm_hdmi_compute_mode_clock(mode, 8, HDMI_COLORSPACE_RGB);
> > return bridge->funcs->hdmi_tmds_char_rate_valid(bridge, mode, rate);
>
> Will look into the two lines.
>
> >
> >> +}
> >> +
> >> +static int it6263_bridge_attach(struct drm_bridge *bridge,
> >> + enum drm_bridge_attach_flags flags)
> >> +{
> >> + struct it6263 *it = bridge_to_it6263(bridge);
> >> + int ret;
> >> +
> >> + ret = drm_bridge_attach(bridge->encoder, it->next_bridge, bridge,
> >> + flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
> >> + if (ret < 0)
> >> + return ret;
> >> +
> >> + if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
> >> + return 0;
> >> +
> >> + it->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
> >> + DRM_CONNECTOR_POLL_DISCONNECT;
> >> +
> >
> > Please strongly consider dropping this and using drm_bridge_connector in
> > the host driver.
>
> I can't afford to make i.MX8MP imx-lcdif KMS use drm_bridge_connector
> currently. Maybe the Renesas RZ/G3E SMARC EVK Biju tested v1 patch
> set with is also not using drm_bridge_connector. I hope we can leave
> it as-is for now.
At least you can use drm_bridge_connector in this driver rather than
open-coding yet another connector implementation wich doesn't work with
the next bridges.
>
> >
> >> + ret = drm_connector_init(bridge->dev, &it->connector,
> >> + &it6263_connector_funcs,
> >> + DRM_MODE_CONNECTOR_HDMIA);
> >> + if (ret)
> >> + return ret;
> >> +
> >> + drm_connector_helper_add(&it->connector,
> >> + &it6263_connector_helper_funcs);
> >> + drm_connector_attach_encoder(&it->connector, bridge->encoder);
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static enum drm_connector_status it6263_bridge_detect(struct drm_bridge *bridge)
> >> +{
> >> + struct it6263 *it = bridge_to_it6263(bridge);
> >> +
> >> + return it6263_detect(it);
> >> +}
> >> +
> >> +static const struct drm_edid *
> >> +it6263_bridge_edid_read(struct drm_bridge *bridge,
> >> + struct drm_connector *connector)
> >> +{
> >> + struct it6263 *it = bridge_to_it6263(bridge);
> >> +
> >> + return drm_edid_read_custom(connector, it6263_read_edid, it);
> >> +}
> >> +
> >> +static u32 *
> >> +it6263_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
> >> + struct drm_bridge_state *bridge_state,
> >> + struct drm_crtc_state *crtc_state,
> >> + struct drm_connector_state *conn_state,
> >> + u32 output_fmt,
> >> + unsigned int *num_input_fmts)
> >> +{
> >> + struct it6263 *it = bridge_to_it6263(bridge);
> >> + u32 *input_fmts;
> >> +
> >> + *num_input_fmts = 0;
> >> +
> >> + if (it->lvds_link_num_dlanes == 3)
> >> + return NULL;
> >> +
> >> + input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
> >> + if (!input_fmts)
> >> + return NULL;
> >> +
> >> + input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA;
> >> + *num_input_fmts = 1;
> >> +
> >> + return input_fmts;
> >> +}
> >> +
> >> +static const struct drm_bridge_funcs it6263_bridge_funcs = {
> >> + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
> >> + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
> >> + .atomic_reset = drm_atomic_helper_bridge_reset,
> >> + .attach = it6263_bridge_attach,
> >> + .mode_valid = it6263_bridge_mode_valid,
> >> + .atomic_disable = it6263_bridge_atomic_disable,
> >> + .atomic_enable = it6263_bridge_atomic_enable,
> >> + .atomic_check = it6263_bridge_atomic_check,
> >> + .detect = it6263_bridge_detect,
> >> + .edid_read = it6263_bridge_edid_read,
> >> + .atomic_get_input_bus_fmts = it6263_bridge_atomic_get_input_bus_fmts,
> >> +};
> >> +
> >> +static int it6263_probe(struct i2c_client *client)
> >> +{
> >> + struct device *dev = &client->dev;
> >> + struct it6263 *it;
> >> + int ret;
> >> +
> >> + it = devm_kzalloc(dev, sizeof(*it), GFP_KERNEL);
> >> + if (!it)
> >> + return -ENOMEM;
> >> +
> >> + it->dev = dev;
> >> + it->hdmi_i2c = client;
> >> +
> >> + it->hdmi_regmap = devm_regmap_init_i2c(client,
> >> + &it6263_hdmi_regmap_config);
> >> + if (IS_ERR(it->hdmi_regmap))
> >> + return dev_err_probe(dev, PTR_ERR(it->hdmi_regmap),
> >> + "failed to init I2C regmap for HDMI\n");
> >> +
> >> + it->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
> >> + if (IS_ERR(it->reset_gpio))
> >> + return dev_err_probe(dev, PTR_ERR(it->reset_gpio),
> >> + "failed to get reset gpio\n");
> >> +
> >> + ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(it6263_supplies),
> >> + it6263_supplies);
> >> + if (ret)
> >> + return dev_err_probe(dev, ret, "failed to get power supplies\n");
> >> +
> >> + ret = it6263_parse_dt(it);
> >> + if (ret)
> >> + return ret;
> >> +
> >> + it6263_hw_reset(it);
> >> +
> >> + ret = it6263_lvds_set_i2c_addr(it);
> >> + if (ret)
> >> + return dev_err_probe(dev, ret, "failed to set I2C addr\n");
> >> +
> >> + it->lvds_i2c = devm_i2c_new_dummy_device(dev, client->adapter,
> >> + LVDS_INPUT_CTRL_I2C_ADDR);
> >> + if (IS_ERR(it->lvds_i2c))
> >> + dev_err_probe(it->dev, PTR_ERR(it->lvds_i2c),
> >> + "failed to allocate I2C device for LVDS\n");
> >> +
> >> + it->lvds_regmap = devm_regmap_init_i2c(it->lvds_i2c,
> >> + &it6263_lvds_regmap_config);
> >> + if (IS_ERR(it->lvds_regmap))
> >> + return dev_err_probe(dev, PTR_ERR(it->lvds_regmap),
> >> + "failed to init I2C regmap for LVDS\n");
> >> +
> >> + it6263_lvds_config(it);
> >> + it6263_hdmi_config(it);
> >> +
> >> + i2c_set_clientdata(client, it);
> >> +
> >> + it->bridge.funcs = &it6263_bridge_funcs;
> >> + it->bridge.of_node = dev->of_node;
> >> + it->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT;
> >
> > | DRM_BRIDGE_OP_HDMI
>
> Will take a look at this.
>
> >
> > BTW: No HPD IRQ support?
> IT6263 chip doesn't support HPD IRQ.
ack
>
> >
> >> + it->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
> >> + drm_bridge_add(&it->bridge);
> >
> > devm_drm_bridge_add()
>
> Will try to use this. Thanks.
>
> >
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static void it6263_remove(struct i2c_client *client)
> >> +{
> >> + struct it6263 *it = i2c_get_clientdata(client);
> >> +
> >> + drm_bridge_remove(&it->bridge);
> >
> > Remove, it becomes unused with the devm_ function.
> >
> >> +}
> >> +
> >> +static const struct of_device_id it6263_of_match[] = {
> >> + { .compatible = "ite,it6263", },
> >> + { }
> >> +};
> >> +MODULE_DEVICE_TABLE(of, it6263_of_match);
> >> +
> >> +static const struct i2c_device_id it6263_i2c_ids[] = {
> >> + { "it6263", 0 },
> >> + { }
> >> +};
> >> +MODULE_DEVICE_TABLE(i2c, it6263_i2c_ids);
> >> +
> >> +static struct i2c_driver it6263_driver = {
> >> + .probe = it6263_probe,
> >> + .remove = it6263_remove,
> >> + .driver = {
> >> + .name = "it6263",
> >> + .of_match_table = it6263_of_match,
> >> + },
> >> + .id_table = it6263_i2c_ids,
> >> +};
> >> +module_i2c_driver(it6263_driver);
> >> +
> >> +MODULE_DESCRIPTION("ITE Tech. Inc. IT6263 LVDS/HDMI bridge");
> >> +MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>");
> >> +MODULE_LICENSE("GPL");
> >> --
> >> 2.34.1
> >>
> >
>
> --
> Regards,
> Liu Ying
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-13 10:48 ` Biju Das
@ 2024-10-14 0:00 ` Dmitry Baryshkov
2024-10-18 6:58 ` Liu Ying
0 siblings, 1 reply; 49+ messages in thread
From: Dmitry Baryshkov @ 2024-10-14 0:00 UTC (permalink / raw)
To: Biju Das
Cc: Liu Ying, dri-devel@lists.freedesktop.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
andrzej.hajda@intel.com, neil.armstrong@linaro.org,
rfoss@kernel.org, laurent.pinchart, jonas@kwiboo.se,
jernej.skrabec@gmail.com, airlied@gmail.com, simona@ffwll.ch,
maarten.lankhorst@linux.intel.com, mripard@kernel.org,
tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com,
catalin.marinas@arm.com, will@kernel.org,
quic_bjorande@quicinc.com, geert+renesas@glider.be, arnd@arndb.de,
nfraprado@collabora.com, o.rempel@pengutronix.de,
y.moog@phytec.de, marex@denx.de, isaac.scott@ideasonboard.com
On Sun, Oct 13, 2024 at 10:48:54AM +0000, Biju Das wrote:
> Hi Liu Ying,
>
> > -----Original Message-----
> > From: Liu Ying <victor.liu@nxp.com>
> > Sent: Saturday, October 12, 2024 11:02 AM
> > To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > Cc: dri-devel@lists.freedesktop.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> > Subject: Re: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
> >
> > On 10/12/2024, Dmitry Baryshkov wrote:
> > > On Sat, Oct 12, 2024 at 03:35:40PM +0800, Liu Ying wrote:
> > >> Add basic HDMI video output support. Currently, only RGB888 output
> > >> pixel format is supported. At the LVDS input side, the driver
> > >> supports single LVDS link and dual LVDS links with "jeida-24" LVDS
> > >> mapping.
> > >>
> > >> Product link:
> > >> https://www.ite.com.tw/en/product/cate1/IT6263
> > >>
> > >> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> > >> ---
> > >> v2:
> > >> * Add AVI inforframe support. (Maxime)
> > >
> > > Maxime asked to wire up the HDMI Connector framework. I have pushed
> > > the patch that converts lt9611.c driver. Please implement similar
> > > changes in your driver.
> >
> > Hmm, didn't fully get the meaning of "the new HDMI bridge infrastructure"
> > maxime asked. Ok, will take a look at lt9611.c.
> >
> > >
> > >> * Add DRM_MODE_CONNECTOR_HDMIA. (Biju)
> > >> * Rename it6263_reset() to it6263_hw_reset(). (Biju)
> > >> * Check number of LVDS link data lanes. (Biju)
> > >>
> > >> drivers/gpu/drm/bridge/Kconfig | 8 +
> > >> drivers/gpu/drm/bridge/Makefile | 1 +
> > >> drivers/gpu/drm/bridge/ite-it6263.c | 919
> > >> ++++++++++++++++++++++++++++
> > >> 3 files changed, 928 insertions(+)
> > >> create mode 100644 drivers/gpu/drm/bridge/ite-it6263.c
> > >>
> > >> diff --git a/drivers/gpu/drm/bridge/Kconfig
> > >> b/drivers/gpu/drm/bridge/Kconfig index 3eb955333c80..93f99682a090
> > >> 100644
> > >> --- a/drivers/gpu/drm/bridge/Kconfig
> > >> +++ b/drivers/gpu/drm/bridge/Kconfig
> > >> @@ -90,6 +90,14 @@ config DRM_FSL_LDB
> > >> help
> > >> Support for i.MX8MP DPI-to-LVDS on-SoC encoder.
> > >>
> > >> +config DRM_ITE_IT6263
> > >> + tristate "ITE IT6263 LVDS/HDMI bridge"
> > >> + depends on OF
> > >> + select DRM_KMS_HELPER
> > >> + select REGMAP_I2C
> > >> + help
> > >> + ITE IT6263 LVDS to HDMI bridge chip driver.
> > >> +
> > >> config DRM_ITE_IT6505
> > >> tristate "ITE IT6505 DisplayPort bridge"
> > >> depends on OF
> > >> diff --git a/drivers/gpu/drm/bridge/Makefile
> > >> b/drivers/gpu/drm/bridge/Makefile index 7df87b582dca..f3776dd473fd
> > >> 100644
> > >> --- a/drivers/gpu/drm/bridge/Makefile
> > >> +++ b/drivers/gpu/drm/bridge/Makefile
> > >> @@ -6,6 +6,7 @@ obj-$(CONFIG_DRM_CHRONTEL_CH7033) +=
> > >> chrontel-ch7033.o
> > >> obj-$(CONFIG_DRM_CROS_EC_ANX7688) += cros-ec-anx7688.o
> > >> obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
> > >> obj-$(CONFIG_DRM_FSL_LDB) += fsl-ldb.o
> > >> +obj-$(CONFIG_DRM_ITE_IT6263) += ite-it6263.o
> > >> obj-$(CONFIG_DRM_ITE_IT6505) += ite-it6505.o
> > >> obj-$(CONFIG_DRM_LONTIUM_LT8912B) += lontium-lt8912b.o
> > >> obj-$(CONFIG_DRM_LONTIUM_LT9211) += lontium-lt9211.o diff --git
> > >> a/drivers/gpu/drm/bridge/ite-it6263.c
> > >> b/drivers/gpu/drm/bridge/ite-it6263.c
> > >> new file mode 100644
> > >> index 000000000000..9b3318792f15
> > >> --- /dev/null
> > >> +++ b/drivers/gpu/drm/bridge/ite-it6263.c
> > >> @@ -0,0 +1,919 @@
> > >> +// SPDX-License-Identifier: GPL-2.0
> > >> +/*
> > >> + * Copyright 2024 NXP
> > >> + */
> > >> +
> > >> +#include <linux/bitfield.h>
> > >> +#include <linux/bits.h>
> > >> +#include <linux/delay.h>
> > >> +#include <linux/gpio/consumer.h>
> > >> +#include <linux/hdmi.h>
> > >> +#include <linux/i2c.h>
> > >> +#include <linux/media-bus-format.h>
> > >> +#include <linux/module.h>
> > >> +#include <linux/of.h>
> > >> +#include <linux/regmap.h>
> > >> +#include <linux/regulator/consumer.h>
> > >> +
> > >> +#include <drm/drm_atomic.h>
> > >> +#include <drm/drm_atomic_helper.h>
> > >> +#include <drm/drm_atomic_state_helper.h> #include <drm/drm_bridge.h>
> > >> +#include <drm/drm_connector.h> #include <drm/drm_crtc.h> #include
> > >> +<drm/drm_edid.h> #include <drm/drm_of.h> #include
> > >> +<drm/drm_probe_helper.h>
> > >> +
> > >> +/*
> > >> +--------------------------------------------------------------------
> > >> +---------
> > >> + * LVDS registers
> > >> + */
> > >> +
> > >> +/* LVDS software reset registers */
> > >> +#define LVDS_REG_05 0x05
> > >> +#define REG_SOFT_P_RST BIT(1)
> > >> +
> > >> +/* LVDS system configuration registers */
> > >> +/* 0x0b */
> > >> +#define LVDS_REG_0B 0x0b
> > >> +#define REG_SSC_PCLK_RF BIT(0)
> > >> +#define REG_LVDS_IN_SWAP BIT(1)
> > >> +
> > >> +/* LVDS test pattern gen control registers */
> > >> +/* 0x2c */
> > >> +#define LVDS_REG_2C 0x2c
> > >> +#define REG_COL_DEP GENMASK(1, 0)
> > >> +#define BIT8 FIELD_PREP(REG_COL_DEP, 2)
> > >> +#define OUT_MAP BIT(4)
> > >> +#define JEIDA 0
> > >> +#define REG_DESSC_ENB BIT(6)
> > >> +#define DMODE BIT(7)
> > >> +#define DISO BIT(7)
> > >> +#define SISO 0
> > >> +
> > >> +#define LVDS_REG_3C 0x3c
> > >> +#define LVDS_REG_3F 0x3f
> > >> +#define LVDS_REG_47 0x47
> > >> +#define LVDS_REG_48 0x48
> > >> +#define LVDS_REG_4F 0x4f
> > >> +#define LVDS_REG_52 0x52
> > >> +
> > >> +/*
> > >> +--------------------------------------------------------------------
> > >> +---------
> > >> + * HDMI registers are separated into three banks:
> > >> + * 1) HDMI register common bank: 0x00 ~ 0x2f */
> > >> +
> > >> +/* HDMI genernal registers */
> > >> +#define HDMI_REG_SW_RST 0x04
> > >> +#define SOFTREF_RST BIT(5)
> > >> +#define SOFTA_RST BIT(4)
> > >> +#define SOFTV_RST BIT(3)
> > >> +#define AUD_RST BIT(2)
> > >> +#define HDCP_RST BIT(0)
> > >> +#define HDMI_RST_ALL (SOFTREF_RST | SOFTA_RST | SOFTV_RST | \
> > >> + AUD_RST | HDCP_RST)
> > >> +
> > >> +#define HDMI_REG_SYS_STATUS 0x0e
> > >> +#define HPDETECT BIT(6)
> > >> +#define TXVIDSTABLE BIT(4)
> > >> +
> > >> +#define HDMI_REG_BANK_CTRL 0x0f
> > >> +#define REG_BANK_SEL BIT(0)
> > >> +
> > >> +/* HDMI System DDC control registers */
> > >> +#define HDMI_REG_DDC_MASTER_CTRL 0x10
> > >> +#define MASTER_SEL_HOST BIT(0)
> > >> +
> > >> +#define HDMI_REG_DDC_HEADER 0x11
> > >> +
> > >> +#define HDMI_REG_DDC_REQOFF 0x12
> > >> +#define HDMI_REG_DDC_REQCOUNT 0x13
> > >> +#define HDMI_REG_DDC_EDIDSEG 0x14
> > >> +
> > >> +#define HDMI_REG_DDC_CMD 0x15
> > >> +#define DDC_CMD_EDID_READ 0x3
> > >> +#define DDC_CMD_FIFO_CLR 0x9
> > >> +
> > >> +#define HDMI_REG_DDC_STATUS 0x16
> > >> +#define DDC_DONE BIT(7)
> > >> +#define DDC_NOACK BIT(5)
> > >> +#define DDC_WAITBUS BIT(4)
> > >> +#define DDC_ARBILOSE BIT(3)
> > >> +#define DDC_ERROR (DDC_NOACK | DDC_WAITBUS | DDC_ARBILOSE)
> > >> +
> > >> +#define HDMI_DDC_FIFO_BYTES 32
> > >> +#define HDMI_REG_DDC_READFIFO 0x17
> > >> +#define HDMI_REG_LVDS_PORT 0x1d /* LVDS input control I2C addr */
> > >> +#define HDMI_REG_LVDS_PORT_EN 0x1e
> > >> +#define LVDS_INPUT_CTRL_I2C_ADDR 0x33
> > >> +
> > >> +/*
> > >> +--------------------------------------------------------------------
> > >> +---------
> > >> + * 2) HDMI register bank0: 0x30 ~ 0xff */
> > >> +
> > >> +/* HDMI AFE registers */
> > >> +#define HDMI_REG_AFE_DRV_CTRL 0x61
> > >> +#define AFE_DRV_PWD BIT(5)
> > >> +#define AFE_DRV_RST BIT(4)
> > >> +
> > >> +#define HDMI_REG_AFE_XP_CTRL 0x62
> > >> +#define AFE_XP_GAINBIT BIT(7)
> > >> +#define AFE_XP_ER0 BIT(4)
> > >> +#define AFE_XP_RESETB BIT(3)
> > >> +
> > >> +#define HDMI_REG_AFE_ISW_CTRL 0x63
> > >> +
> > >> +#define HDMI_REG_AFE_IP_CTRL 0x64
> > >> +#define AFE_IP_GAINBIT BIT(7)
> > >> +#define AFE_IP_ER0 BIT(3)
> > >> +#define AFE_IP_RESETB BIT(2)
> > >> +
> > >> +/* HDMI input data format registers */
> > >> +#define HDMI_REG_INPUT_MODE 0x70
> > >> +#define IN_RGB 0x00
> > >> +
> > >> +/* HDMI general control registers */
> > >> +#define HDMI_REG_HDMI_MODE 0xc0
> > >> +#define TX_HDMI_MODE BIT(0)
> > >> +
> > >> +#define HDMI_REG_GCP 0xc1
> > >> +#define AVMUTE BIT(0)
> > >> +#define HDMI_COLOR_DEPTH GENMASK(6, 4)
> > >> +#define HDMI_COLOR_DEPTH_24 FIELD_PREP(HDMI_COLOR_DEPTH, 4)
> > >> +
> > >> +#define HDMI_REG_PKT_GENERAL_CTRL 0xc6
> > >> +#define ENABLE_PKT BIT(0)
> > >> +#define REPEAT_PKT BIT(1)
> > >> +
> > >> +/*
> > >> +--------------------------------------------------------------------
> > >> +---------
> > >> + * 3) HDMI register bank1: 0x130 ~ 0x1ff (HDMI packet registers) */
> > >> +
> > >> +/* AVI packet registers */
> > >> +#define HDMI_REG_AVI_DB1 0x158
> > >> +#define HDMI_REG_AVI_DB2 0x159
> > >> +#define HDMI_REG_AVI_DB3 0x15a
> > >> +#define HDMI_REG_AVI_DB4 0x15b
> > >> +#define HDMI_REG_AVI_DB5 0x15c
> > >> +#define HDMI_REG_AVI_CSUM 0x15d
> > >> +#define HDMI_REG_AVI_DB6 0x15e
> > >> +#define HDMI_REG_AVI_DB7 0x15f
> > >> +#define HDMI_REG_AVI_DB8 0x160
> > >> +#define HDMI_REG_AVI_DB9 0x161
> > >> +#define HDMI_REG_AVI_DB10 0x162
> > >> +#define HDMI_REG_AVI_DB11 0x163
> > >> +#define HDMI_REG_AVI_DB12 0x164
> > >> +#define HDMI_REG_AVI_DB13 0x165
> > >> +
> > >> +#define HDMI_AVI_DB_CHUNK1_SIZE (HDMI_REG_AVI_DB5 - HDMI_REG_AVI_DB1 + 1)
> > >> +#define HDMI_AVI_DB_CHUNK2_SIZE (HDMI_REG_AVI_DB13 - HDMI_REG_AVI_DB6 + 1)
> > >> +
> > >> +#define MAX_PIXEL_CLOCK_KHZ 150000
> > >> +#define HIGH_PIXEL_CLOCK_KHZ 80000
> > >> +
> > >> +struct it6263 {
> > >> + struct device *dev;
> > >> + struct i2c_client *hdmi_i2c;
> > >> + struct i2c_client *lvds_i2c;
> > >> + struct regmap *hdmi_regmap;
> > >> + struct regmap *lvds_regmap;
> > >> + struct drm_bridge bridge;
> > >> + struct drm_bridge *next_bridge;
> > >> + struct drm_connector connector;
> > >> + struct gpio_desc *reset_gpio;
> > >> + u8 lvds_link_num_dlanes;
> > >> + bool lvds_dual_link;
> > >> + bool lvds_link12_swap;
> > >> +};
> > >> +
> > >> +static inline struct it6263 *bridge_to_it6263(struct drm_bridge
> > >> +*bridge) {
> > >> + return container_of(bridge, struct it6263, bridge); }
> > >> +
> > >> +static inline struct it6263 *connector_to_it6263(struct
> > >> +drm_connector *conn) {
> > >> + return container_of(conn, struct it6263, connector); }
> > >> +
> > >> +static bool it6263_hdmi_writeable_reg(struct device *dev, unsigned
> > >> +int reg) {
> > >> + switch (reg) {
> > >> + case HDMI_REG_SW_RST:
> > >> + case HDMI_REG_BANK_CTRL:
> > >> + case HDMI_REG_DDC_MASTER_CTRL:
> > >> + case HDMI_REG_DDC_HEADER:
> > >> + case HDMI_REG_DDC_REQOFF:
> > >> + case HDMI_REG_DDC_REQCOUNT:
> > >> + case HDMI_REG_DDC_EDIDSEG:
> > >> + case HDMI_REG_DDC_CMD:
> > >> + case HDMI_REG_LVDS_PORT:
> > >> + case HDMI_REG_LVDS_PORT_EN:
> > >> + case HDMI_REG_AFE_DRV_CTRL:
> > >> + case HDMI_REG_AFE_XP_CTRL:
> > >> + case HDMI_REG_AFE_ISW_CTRL:
> > >> + case HDMI_REG_AFE_IP_CTRL:
> > >> + case HDMI_REG_INPUT_MODE:
> > >> + case HDMI_REG_HDMI_MODE:
> > >> + case HDMI_REG_GCP:
> > >> + case HDMI_REG_PKT_GENERAL_CTRL:
> > >> + case HDMI_REG_AVI_DB1:
> > >> + case HDMI_REG_AVI_DB2:
> > >> + case HDMI_REG_AVI_DB3:
> > >> + case HDMI_REG_AVI_DB4:
> > >> + case HDMI_REG_AVI_DB5:
> > >> + case HDMI_REG_AVI_CSUM:
> > >> + case HDMI_REG_AVI_DB6:
> > >> + case HDMI_REG_AVI_DB7:
> > >> + case HDMI_REG_AVI_DB8:
> > >> + case HDMI_REG_AVI_DB9:
> > >> + case HDMI_REG_AVI_DB10:
> > >> + case HDMI_REG_AVI_DB11:
> > >> + case HDMI_REG_AVI_DB12:
> > >> + case HDMI_REG_AVI_DB13:
> > >> + return true;
> > >> + default:
> > >> + return false;
> > >> + }
> > >> +}
> > >> +
> > >> +static bool it6263_hdmi_readable_reg(struct device *dev, unsigned
> > >> +int reg) {
> > >> + if (it6263_hdmi_writeable_reg(dev, reg))
> > >> + return true;
> > >> +
> > >> + switch (reg) {
> > >> + case HDMI_REG_SYS_STATUS:
> > >> + case HDMI_REG_DDC_STATUS:
> > >> + case HDMI_REG_DDC_READFIFO:
> > >> + return true;
> > >> + default:
> > >> + return false;
> > >> + }
> > >> +}
> > >> +
> > >> +static bool it6263_hdmi_volatile_reg(struct device *dev, unsigned
> > >> +int reg) {
> > >> + switch (reg) {
> > >> + case HDMI_REG_SW_RST:
> > >> + case HDMI_REG_SYS_STATUS:
> > >> + case HDMI_REG_DDC_STATUS:
> > >> + case HDMI_REG_DDC_READFIFO:
> > >> + return true;
> > >> + default:
> > >> + return false;
> > >> + }
> > >> +}
> > >> +
> > >> +static const struct regmap_range_cfg it6263_hdmi_range_cfg = {
> > >> + .range_min = 0x00,
> > >> + .range_max = HDMI_REG_AVI_DB13,
> > >> + .selector_reg = HDMI_REG_BANK_CTRL,
> > >> + .selector_mask = REG_BANK_SEL,
> > >> + .selector_shift = 0,
> > >> + .window_start = 0x00,
> > >> + .window_len = 0x100,
> > >> +};
> > >> +
> > >> +static const struct regmap_config it6263_hdmi_regmap_config = {
> > >> + .name = "it6263-hdmi",
> > >> + .reg_bits = 8,
> > >> + .val_bits = 8,
> > >> + .writeable_reg = it6263_hdmi_writeable_reg,
> > >> + .readable_reg = it6263_hdmi_readable_reg,
> > >> + .volatile_reg = it6263_hdmi_volatile_reg,
> > >> + .max_register = HDMI_REG_AVI_DB13,
> > >> + .ranges = &it6263_hdmi_range_cfg,
> > >> + .num_ranges = 1,
> > >> + .cache_type = REGCACHE_MAPLE,
> > >> +};
> > >> +
> > >> +static bool it6263_lvds_writeable_reg(struct device *dev, unsigned
> > >> +int reg) {
> > >> + switch (reg) {
> > >> + case LVDS_REG_05:
> > >> + case LVDS_REG_0B:
> > >> + case LVDS_REG_2C:
> > >> + case LVDS_REG_3C:
> > >> + case LVDS_REG_3F:
> > >> + case LVDS_REG_47:
> > >> + case LVDS_REG_48:
> > >> + case LVDS_REG_4F:
> > >> + case LVDS_REG_52:
> > >> + return true;
> > >> + default:
> > >> + return false;
> > >> + }
> > >> +}
> > >> +
> > >> +static bool it6263_lvds_readable_reg(struct device *dev, unsigned
> > >> +int reg) {
> > >> + return it6263_lvds_writeable_reg(dev, reg); }
> > >> +
> > >> +static bool it6263_lvds_volatile_reg(struct device *dev, unsigned
> > >> +int reg) {
> > >> + return reg == LVDS_REG_05;
> > >> +}
> > >> +
> > >> +static const struct regmap_config it6263_lvds_regmap_config = {
> > >> + .name = "it6263-lvds",
> > >> + .reg_bits = 8,
> > >> + .val_bits = 8,
> > >> + .writeable_reg = it6263_lvds_writeable_reg,
> > >> + .readable_reg = it6263_lvds_readable_reg,
> > >> + .volatile_reg = it6263_lvds_volatile_reg,
> > >> + .max_register = LVDS_REG_52,
> > >> + .cache_type = REGCACHE_MAPLE,
> > >> +};
> > >> +
> > >> +static const char * const it6263_supplies[] = {
> > >> + "ivdd", "ovdd", "txavcc18", "txavcc33", "pvcc1", "pvcc2",
> > >> + "avcc", "anvdd", "apvdd"
> > >> +};
> > >> +
> > >> +static int it6263_parse_dt(struct it6263 *it) {
> > >> + struct device *dev = it->dev;
> > >> + struct device_node *port0, *port1;
> > >> + int ret;
> > >> +
> > >> + ret = of_property_read_u8(dev->of_node, "ite,lvds-link-num-data-lanes",
> > >> + &it->lvds_link_num_dlanes);
> > >> + if (ret) {
> > >> + dev_err(dev, "failed to get LVDS link number of data lanes: %d\n",
> > >> + ret);
> > >> + return ret;
> > >> + }
> > >> +
> > >> + it->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0);
> > >> + if (IS_ERR(it->next_bridge))
> > >> + return dev_err_probe(dev, PTR_ERR(it->next_bridge),
> > >> + "failed to get next bridge\n");
> > >> +
> > >> + port0 = of_graph_get_port_by_id(dev->of_node, 0);
> > >> + port1 = of_graph_get_port_by_id(dev->of_node, 1);
> > >> + if (port0 && port1) {
> > >> + if (of_property_read_bool(port0, "dual-lvds-even-pixels") &&
> > >> + of_property_read_bool(port1, "dual-lvds-odd-pixels")) {
> > >> + it->lvds_dual_link = true;
> > >> + it->lvds_link12_swap = true;
> > >
> > > This is a nice name for the propery in the Dual Link LVDS case:
> > >
> > > ite,lvds-link-swap
> >
> > Swapping LVDS link1&2 is implied by the dual-lvds-{even,odd}-pixels properties that DT writers specify
> > in port@0 and port@1.
> >
> > The DT writers don't need to use a dedicated property like ite,lvds-link-swap to explicitly indicate
> > the swap.
> >
> > >
> > >
> > >> + } else if (of_property_read_bool(port0, "dual-lvds-odd-pixels") &&
> > >> + of_property_read_bool(port1, "dual-lvds-even-pixels")) {
> > >> + it->lvds_dual_link = true;
> > >> + }
> > >> +
> > >> + if (!it->lvds_dual_link) {
> > >> + dev_err(dev,
> > >> + "failed to get LVDS dual link pixel order\n");
> > >> + ret = -EINVAL;
> > >> + }
> > >> + } else if (port1) {
> > >> + ret = -EINVAL;
> > >> + dev_err(dev, "single input LVDS port1 is not supported\n");
> > >> + } else if (!port0) {
> > >> + ret = -EINVAL;
> > >> + dev_err(dev, "no input LVDS port\n");
> > >> + }
> > >> +
> > >> + of_node_put(port0);
> > >> + of_node_put(port1);
> > >> +
> > >> + return ret;
> > >> +}
> > >> +
> > >> +static inline void it6263_hw_reset(struct it6263 *it) {
> > >> + if (!it->reset_gpio)
> > >> + return;
> > >> +
> > >> + gpiod_set_value_cansleep(it->reset_gpio, 0);
> > >> + fsleep(1000);
> > >> + gpiod_set_value_cansleep(it->reset_gpio, 1);
> > >> + /* The chip maker says the low pulse should be at least 40ms. */
> > >> + fsleep(40000);
> > >> + gpiod_set_value_cansleep(it->reset_gpio, 0);
> > >> + /* addtional time to wait the high voltage to be stable */
> > >> + fsleep(5000);
> > >> +}
> > >> +
> > >> +static inline int it6263_lvds_set_i2c_addr(struct it6263 *it) {
> > >> + int ret;
> > >> +
> > >> + ret = regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT,
> > >> + LVDS_INPUT_CTRL_I2C_ADDR << 1);
> > >> + if (ret)
> > >> + return ret;
> > >> +
> > >> + return regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT_EN,
> > >> +BIT(0)); }
> > >> +
> > >> +static inline void it6263_lvds_reset(struct it6263 *it) {
> > >> + /* AFE PLL reset */
> > >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), 0x0);
> > >> + fsleep(1000);
> > >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), BIT(0));
> > >> +
> > >> + /* software pixel clock domain reset */
> > >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST,
> > >> + REG_SOFT_P_RST);
> > >> + fsleep(1000);
> > >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST, 0x0);
> > >> + fsleep(10000);
> > >> +}
> > >> +
> > >> +static inline void it6263_lvds_set_interface(struct it6263 *it) {
> > >> + /* color depth */
> > >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_COL_DEP, BIT8);
> > >> + /* output mapping */
> > >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, OUT_MAP, JEIDA);
> > >> +
> > >> + if (it->lvds_dual_link) {
> > >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, DISO);
> > >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), BIT(1));
> > >> + } else {
> > >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, SISO);
> > >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), 0);
> > >> + }
> > >> +}
> > >> +
> > >> +static inline void it6263_lvds_set_afe(struct it6263 *it) {
> > >> + regmap_write(it->lvds_regmap, LVDS_REG_3C, 0xaa);
> > >> + regmap_write(it->lvds_regmap, LVDS_REG_3F, 0x02);
> > >> + regmap_write(it->lvds_regmap, LVDS_REG_47, 0xaa);
> > >> + regmap_write(it->lvds_regmap, LVDS_REG_48, 0x02);
> > >> + regmap_write(it->lvds_regmap, LVDS_REG_4F, 0x11);
> > >> +
> > >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_SSC_PCLK_RF,
> > >> + REG_SSC_PCLK_RF);
> > >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, 0x07, 0);
> > >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_DESSC_ENB,
> > >> + REG_DESSC_ENB);
> > >> +}
> > >> +
> > >> +static inline void it6263_lvds_sys_cfg(struct it6263 *it) {
> > >> + regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_LVDS_IN_SWAP,
> > >> + it->lvds_link12_swap ? REG_LVDS_IN_SWAP : 0); }
> > >> +
> > >> +static inline void it6263_lvds_config(struct it6263 *it) {
> > >> + it6263_lvds_reset(it);
> > >> + it6263_lvds_set_interface(it);
> > >> + it6263_lvds_set_afe(it);
> > >> + it6263_lvds_sys_cfg(it);
> > >> +}
> > >> +
> > >> +static inline void it6263_hdmi_config(struct it6263 *it) {
> > >> + regmap_write(it->hdmi_regmap, HDMI_REG_SW_RST, HDMI_RST_ALL);
> > >> + regmap_write(it->hdmi_regmap, HDMI_REG_INPUT_MODE, IN_RGB);
> > >> + regmap_write_bits(it->hdmi_regmap, HDMI_REG_GCP, HDMI_COLOR_DEPTH,
> > >> + HDMI_COLOR_DEPTH_24);
> > >> +}
> > >> +
> > >> +static enum drm_connector_status it6263_detect(struct it6263 *it) {
> > >> + unsigned int val;
> > >> +
> > >> + regmap_read(it->hdmi_regmap, HDMI_REG_SYS_STATUS, &val);
> > >> + if (val & HPDETECT)
> > >> + return connector_status_connected;
> > >> + else
> > >> + return connector_status_disconnected; }
> > >> +
> > >> +static enum drm_connector_status
> > >> +it6263_connector_detect(struct drm_connector *connector, bool force)
> > >> +{
> > >> + struct it6263 *it = connector_to_it6263(connector);
> > >> +
> > >> + return it6263_detect(it);
> > >> +}
> > >> +
> > >> +static const struct drm_connector_funcs it6263_connector_funcs = {
> > >> + .detect = it6263_connector_detect,
> > >> + .fill_modes = drm_helper_probe_single_connector_modes,
> > >> + .destroy = drm_connector_cleanup,
> > >> + .reset = drm_atomic_helper_connector_reset,
> > >> + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
> > >> + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> > >> +};
> > >> +
> > >> +static int it6263_read_edid(void *data, u8 *buf, unsigned int block,
> > >> +size_t len) {
> > >> + struct it6263 *it = data;
> > >> + struct regmap *regmap = it->hdmi_regmap;
> > >> + unsigned int start = (block % 2) * EDID_LENGTH;
> > >> + unsigned int segment = block >> 1;
> > >> + unsigned int count, val;
> > >> + int ret;
> > >> +
> > >> + regmap_write(regmap, HDMI_REG_DDC_MASTER_CTRL, MASTER_SEL_HOST);
> > >> + regmap_write(regmap, HDMI_REG_DDC_HEADER, DDC_ADDR << 1);
> > >> + regmap_write(regmap, HDMI_REG_DDC_EDIDSEG, segment);
> > >> +
> > >> + while (len) {
> > >> + /* clear DDC FIFO */
> > >> + regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_FIFO_CLR);
> > >> +
> > >> + ret = regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS,
> > >> + val, val & DDC_DONE,
> > >> + 2000, 10000);
> > >> + if (ret) {
> > >> + dev_err(it->dev, "failed to clear DDC FIFO:%d\n", ret);
> > >> + return ret;
> > >> + }
> > >> +
> > >> + count = len > HDMI_DDC_FIFO_BYTES ? HDMI_DDC_FIFO_BYTES : len;
> > >> +
> > >> + /* fire the read command */
> > >> + regmap_write(regmap, HDMI_REG_DDC_REQOFF, start);
> > >> + regmap_write(regmap, HDMI_REG_DDC_REQCOUNT, count);
> > >> + regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_EDID_READ);
> > >> +
> > >> + start += count;
> > >> + len -= count;
> > >> +
> > >> + ret = regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS, val,
> > >> + val & (DDC_DONE | DDC_ERROR),
> > >> + 20000, 250000);
> > >> + if (ret && !(val & DDC_ERROR)) {
> > >> + dev_err(it->dev, "failed to read EDID:%d\n", ret);
> > >> + return ret;
> > >> + }
> > >> +
> > >> + if (val & DDC_ERROR) {
> > >> + dev_err(it->dev, "DDC error\n");
> > >> + return -EIO;
> > >> + }
> > >> +
> > >> + /* cache to buffer */
> > >> + for (; count > 0; count--) {
> > >> + regmap_read(regmap, HDMI_REG_DDC_READFIFO, &val);
> > >> + *(buf++) = val;
> > >> + }
> > >> + }
> > >> +
> > >> + return 0;
> > >> +}
> > >> +
> > >> +static int it6263_connector_get_modes(struct drm_connector
> > >> +*connector) {
> > >> + struct it6263 *it = connector_to_it6263(connector);
> > >> + const struct drm_edid *drm_edid;
> > >> + int count;
> > >> +
> > >> + drm_edid = drm_edid_read_custom(connector, it6263_read_edid, it);
> > >> +
> > >> + drm_edid_connector_update(connector, drm_edid);
> > >> + count = drm_edid_connector_add_modes(connector);
> > >> +
> > >> + drm_edid_free(drm_edid);
> > >> +
> > >> + return count;
> > >> +}
> > >> +
> > >> +static const struct drm_connector_helper_funcs it6263_connector_helper_funcs = {
> > >> + .get_modes = it6263_connector_get_modes, };
> > >> +
> > >> +static int it6263_bridge_atomic_check(struct drm_bridge *bridge,
> > >> + struct drm_bridge_state *bridge_state,
> > >> + struct drm_crtc_state *crtc_state,
> > >> + struct drm_connector_state *conn_state) {
> > >> + struct drm_display_mode *mode = &crtc_state->adjusted_mode;
> > >
> > > Use drm_atomic_helper_connector_hdmi_check().
> >
> > Will take a look at this.
> >
> > >
> > > Implement .hdmi_tmds_char_rate_valid(). Also, I think, single and dual
> >
> > Will take a look at this.
> >
> > > link LVDS have different max clock rates. Please correct me if I'm
> > > wrong.
> >
> > Yes, I think so too. But, I don't know the exact max clock rates.
> > IT6263 data sheet only says LVDS RX supports clock rate up to 150MHz.
>
> >
> > >
> > >> +
> > >> + return mode->clock > MAX_PIXEL_CLOCK_KHZ ? -EINVAL : 0; }
> > >> +
> > >> +static void
> > >> +it6263_bridge_atomic_disable(struct drm_bridge *bridge,
> > >> + struct drm_bridge_state *old_bridge_state) {
> > >> + struct it6263 *it = bridge_to_it6263(bridge);
> > >> +
> > >> + regmap_write_bits(it->hdmi_regmap, HDMI_REG_GCP, AVMUTE, AVMUTE);
> > >> + regmap_write(it->hdmi_regmap, HDMI_REG_PKT_GENERAL_CTRL, 0);
> > >> + regmap_write(it->hdmi_regmap, HDMI_REG_AFE_DRV_CTRL,
> > >> + AFE_DRV_RST | AFE_DRV_PWD);
> > >> +}
> > >> +
> > >> +static void
> > >> +it6263_hdmi_avi_infoframe_configure(struct it6263 *it,
> > >> + struct drm_connector *connector,
> > >> + const struct drm_display_mode *mode)
> > >
> > > -> .hdmi_write_infoframe() , .hdmi_clear_infoframe().
> >
> >
> > Will take a look at them.
> >
> > >
> > >> +{
> > >> + struct hdmi_avi_infoframe frame;
> > >> + u8 buf[HDMI_INFOFRAME_SIZE(AVI)];
> > >> + int ret;
> > >> +
> > >> + ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
> > >> + if (ret) {
> > >> + dev_err(it->dev, "failed to setup AVI infoframe: %d\n", ret);
> > >> + return;
> > >> + }
> > >> +
> > >> + ret = hdmi_avi_infoframe_pack(&frame, buf, sizeof(buf));
> > >> + if (ret < 0) {
> > >> + dev_err(it->dev, "failed to pack infoframe: %d\n", ret);
> > >> + return;
> > >> + }
> > >> +
> > >> + /* write the first AVI infoframe data byte chunk(DB1-DB5) */
> > >> + ret = regmap_bulk_write(it->hdmi_regmap, HDMI_REG_AVI_DB1,
> > >> + &buf[HDMI_INFOFRAME_HEADER_SIZE],
> > >> + HDMI_AVI_DB_CHUNK1_SIZE);
> > >> + if (ret) {
> > >> + dev_err(it->dev, "failed to write the 1st AVI infoframe data byte chunk: %d\n",
> > >> + ret);
> > >> + return;
> > >> + }
> > >> +
> > >> + /* write the second AVI infoframe data byte chunk(DB6-DB13) */
> > >> + ret = regmap_bulk_write(it->hdmi_regmap, HDMI_REG_AVI_DB6,
> > >> + &buf[HDMI_INFOFRAME_HEADER_SIZE +
> > >> + HDMI_AVI_DB_CHUNK1_SIZE],
> > >> + HDMI_AVI_DB_CHUNK2_SIZE);
> > >> + if (ret) {
> > >> + dev_err(it->dev, "failed to write the 2nd AVI infoframe data byte chunk: %d\n",
> > >> + ret);
> > >> + return;
> > >> + }
> > >> +
> > >> + ret = regmap_write(it->hdmi_regmap, HDMI_REG_AVI_CSUM, buf[3]);
> > >> + if (ret)
> > >> + dev_err(it->dev, "failed to set AVI infoframe checksum: %d\n",
> > >> + ret);
> > >> +}
> > >> +
> > >> +static void
> > >> +it6263_bridge_atomic_enable(struct drm_bridge *bridge,
> > >> + struct drm_bridge_state *old_bridge_state) {
> > >> + struct drm_atomic_state *state = old_bridge_state->base.state;
> > >> + struct it6263 *it = bridge_to_it6263(bridge);
> > >> + const struct drm_crtc_state *crtc_state;
> > >> + struct regmap *regmap = it->hdmi_regmap;
> > >> + const struct drm_display_mode *mode;
> > >> + struct drm_connector *connector;
> > >> + bool is_stable = false;
> > >> + struct drm_crtc *crtc;
> > >> + unsigned int val;
> > >> + bool pclk_high;
> > >> + int i, ret;
> > >> +
> > >> + connector = drm_atomic_get_new_connector_for_encoder(state,
> > >> + bridge->encoder);
> > >> + crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
> > >> + crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
> > >> + mode = &crtc_state->adjusted_mode;
> > >> +
> > >> + regmap_write(regmap, HDMI_REG_HDMI_MODE, TX_HDMI_MODE);
> > >> +
> > >> + it6263_hdmi_avi_infoframe_configure(it, connector, mode);
> > >
> > > drm_atomic_helper_connector_hdmi_update_infoframes
> >
> > Will take a look at this.
> >
> > >
> > >> +
> > >> + /* HDMI AFE setup */
> > >> + pclk_high = mode->clock > HIGH_PIXEL_CLOCK_KHZ ? true : false;
> > >> + regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, AFE_DRV_RST);
> > >> + if (pclk_high)
> > >> + regmap_write(regmap, HDMI_REG_AFE_XP_CTRL,
> > >> + AFE_XP_GAINBIT | AFE_XP_RESETB);
> > >> + else
> > >> + regmap_write(regmap, HDMI_REG_AFE_XP_CTRL,
> > >> + AFE_XP_ER0 | AFE_XP_RESETB);
> > >> + regmap_write(regmap, HDMI_REG_AFE_ISW_CTRL, 0x10);
> > >> + if (pclk_high)
> > >> + regmap_write(regmap, HDMI_REG_AFE_IP_CTRL,
> > >> + AFE_IP_GAINBIT | AFE_IP_RESETB);
> > >> + else
> > >> + regmap_write(regmap, HDMI_REG_AFE_IP_CTRL,
> > >> + AFE_IP_ER0 | AFE_IP_RESETB);
> > >> +
> > >> + /* HDMI software video reset */
> > >> + regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, SOFTV_RST);
> > >> + fsleep(1000);
> > >> + regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, 0);
> > >> +
> > >> + /* reconfigure LVDS and retry several times in case video is instable */
> > >> + for (i = 0; i < 3; i++) {
> > >> + ret = regmap_read_poll_timeout(regmap, HDMI_REG_SYS_STATUS, val,
> > >> + val & TXVIDSTABLE,
> > >> + 20000, 500000);
> > >> + if (!ret) {
> > >> + is_stable = true;
> > >> + break;
> > >> + }
> > >> +
> > >> + it6263_lvds_config(it);
> > >> + }
> > >> +
> > >> + if (!is_stable)
> > >> + dev_warn(it->dev, "failed to wait for video stable\n");
> > >> +
> > >> + /* HDMI AFE reset release and power up */
> > >> + regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, 0);
> > >> +
> > >> + regmap_write_bits(regmap, HDMI_REG_GCP, AVMUTE, 0);
> > >> +
> > >> + regmap_write(regmap, HDMI_REG_PKT_GENERAL_CTRL, ENABLE_PKT |
> > >> +REPEAT_PKT); }
> > >> +
> > >> +static enum drm_mode_status
> > >> +it6263_bridge_mode_valid(struct drm_bridge *bridge,
> > >> + const struct drm_display_info *info,
> > >> + const struct drm_display_mode *mode) {
> > >> + return mode->clock > MAX_PIXEL_CLOCK_KHZ ? MODE_CLOCK_HIGH :
> > >> +MODE_OK;
> > >
> > > rate = drm_hdmi_compute_mode_clock(mode, 8, HDMI_COLORSPACE_RGB);
> > > return bridge->funcs->hdmi_tmds_char_rate_valid(bridge, mode,
> > > rate);
> >
> > Will look into the two lines.
> >
> > >
> > >> +}
> > >> +
> > >> +static int it6263_bridge_attach(struct drm_bridge *bridge,
> > >> + enum drm_bridge_attach_flags flags) {
> > >> + struct it6263 *it = bridge_to_it6263(bridge);
> > >> + int ret;
> > >> +
> > >> + ret = drm_bridge_attach(bridge->encoder, it->next_bridge, bridge,
> > >> + flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
> > >> + if (ret < 0)
> > >> + return ret;
> > >> +
> > >> + if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
> > >> + return 0;
> > >> +
> > >> + it->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
> > >> + DRM_CONNECTOR_POLL_DISCONNECT;
> > >> +
> > >
> > > Please strongly consider dropping this and using drm_bridge_connector
> > > in the host driver.
> >
> > I can't afford to make i.MX8MP imx-lcdif KMS use drm_bridge_connector currently. Maybe the Renesas
> > RZ/G3E SMARC EVK Biju tested v1 patch set with is also not using drm_bridge_connector. I hope we can
> > leave it as-is for now.
>
> Renesas platform use the drm_bridge_connector_init() helper to create a drm_connector for
> each output, instead of relying on the bridge drivers doing so. It attach
> the bridges with the DRM_BRIDGE_ATTACH_NO_CONNECTOR flag to instruct
> them not to create a connector.
>
> On Renesas platform, it exit from here
> if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
> return 0;
>
> Maybe it is good to have both cases to start with. Add support for both cases now,
> Later when imx-lcdif KMS start using drm_bridge_connector,
> we can start dropping bridge devices to create connector??
Do we have a timeline for this?
> Dmitry, are you ok with this?
If we can not requre DRM_BRIDGE_ATTACH_NO_CONNECTOR, my suggestion would
be to use drm_bridge_connector from the bridge driver instead of
open-coding yet another drm_connector implementation.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-13 10:27 ` Biju Das
@ 2024-10-14 0:06 ` Dmitry Baryshkov
2024-10-17 9:53 ` Liu Ying
0 siblings, 1 reply; 49+ messages in thread
From: Dmitry Baryshkov @ 2024-10-14 0:06 UTC (permalink / raw)
To: Biju Das
Cc: Liu Ying, dri-devel@lists.freedesktop.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
andrzej.hajda@intel.com, neil.armstrong@linaro.org,
rfoss@kernel.org, laurent.pinchart, jonas@kwiboo.se,
jernej.skrabec@gmail.com, airlied@gmail.com, simona@ffwll.ch,
maarten.lankhorst@linux.intel.com, mripard@kernel.org,
tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com,
catalin.marinas@arm.com, will@kernel.org,
quic_bjorande@quicinc.com, geert+renesas@glider.be, arnd@arndb.de,
nfraprado@collabora.com, o.rempel@pengutronix.de,
y.moog@phytec.de, marex@denx.de, isaac.scott@ideasonboard.com
On Sun, Oct 13, 2024 at 10:27:39AM +0000, Biju Das wrote:
> Hi Dmitry Baryshkov,
>
> > -----Original Message-----
> > From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > Sent: Saturday, October 12, 2024 9:45 AM
> > Subject: Re: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
> >
> > On Sat, Oct 12, 2024 at 03:35:40PM +0800, Liu Ying wrote:
> > > Add basic HDMI video output support. Currently, only RGB888 output
> > > pixel format is supported. At the LVDS input side, the driver
> > > supports single LVDS link and dual LVDS links with "jeida-24" LVDS
> > > mapping.
> > >
> > > Product link:
> > > https://www.ite.com.tw/en/product/cate1/IT6263
> > >
> > > Signed-off-by: Liu Ying <victor.liu@nxp.com>
> > > ---
> > > v2:
> > > * Add AVI inforframe support. (Maxime)
> >
> > Maxime asked to wire up the HDMI Connector framework. I have pushed the patch that converts lt9611.c
> > driver. Please implement similar changes in your driver.
> >
> > > * Add DRM_MODE_CONNECTOR_HDMIA. (Biju)
> > > * Rename it6263_reset() to it6263_hw_reset(). (Biju)
> > > * Check number of LVDS link data lanes. (Biju)
> > >
> > > drivers/gpu/drm/bridge/Kconfig | 8 +
> > > drivers/gpu/drm/bridge/Makefile | 1 +
> > > drivers/gpu/drm/bridge/ite-it6263.c | 919
> > > ++++++++++++++++++++++++++++
> > > 3 files changed, 928 insertions(+)
> > > create mode 100644 drivers/gpu/drm/bridge/ite-it6263.c
> > >
> > > diff --git a/drivers/gpu/drm/bridge/Kconfig
> > > b/drivers/gpu/drm/bridge/Kconfig index 3eb955333c80..93f99682a090
> > > 100644
> > > --- a/drivers/gpu/drm/bridge/Kconfig
> > > +++ b/drivers/gpu/drm/bridge/Kconfig
> > > @@ -90,6 +90,14 @@ config DRM_FSL_LDB
> > > help
> > > Support for i.MX8MP DPI-to-LVDS on-SoC encoder.
> > >
> > > +config DRM_ITE_IT6263
> > > + tristate "ITE IT6263 LVDS/HDMI bridge"
> > > + depends on OF
> > > + select DRM_KMS_HELPER
> > > + select REGMAP_I2C
> > > + help
> > > + ITE IT6263 LVDS to HDMI bridge chip driver.
> > > +
> > > config DRM_ITE_IT6505
> > > tristate "ITE IT6505 DisplayPort bridge"
> > > depends on OF
> > > diff --git a/drivers/gpu/drm/bridge/Makefile
> > > b/drivers/gpu/drm/bridge/Makefile index 7df87b582dca..f3776dd473fd
> > > 100644
> > > --- a/drivers/gpu/drm/bridge/Makefile
> > > +++ b/drivers/gpu/drm/bridge/Makefile
> > > @@ -6,6 +6,7 @@ obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
> > > obj-$(CONFIG_DRM_CROS_EC_ANX7688) += cros-ec-anx7688.o
> > > obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
> > > obj-$(CONFIG_DRM_FSL_LDB) += fsl-ldb.o
> > > +obj-$(CONFIG_DRM_ITE_IT6263) += ite-it6263.o
> > > obj-$(CONFIG_DRM_ITE_IT6505) += ite-it6505.o
> > > obj-$(CONFIG_DRM_LONTIUM_LT8912B) += lontium-lt8912b.o
> > > obj-$(CONFIG_DRM_LONTIUM_LT9211) += lontium-lt9211.o diff --git
> > > a/drivers/gpu/drm/bridge/ite-it6263.c
> > > b/drivers/gpu/drm/bridge/ite-it6263.c
> > > new file mode 100644
> > > index 000000000000..9b3318792f15
> > > --- /dev/null
> > > +++ b/drivers/gpu/drm/bridge/ite-it6263.c
> > > @@ -0,0 +1,919 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> > > + * Copyright 2024 NXP
> > > + */
> > > +
> > > +#include <linux/bitfield.h>
> > > +#include <linux/bits.h>
> > > +#include <linux/delay.h>
> > > +#include <linux/gpio/consumer.h>
> > > +#include <linux/hdmi.h>
> > > +#include <linux/i2c.h>
> > > +#include <linux/media-bus-format.h>
> > > +#include <linux/module.h>
> > > +#include <linux/of.h>
> > > +#include <linux/regmap.h>
> > > +#include <linux/regulator/consumer.h>
> > > +
> > > +#include <drm/drm_atomic.h>
> > > +#include <drm/drm_atomic_helper.h>
> > > +#include <drm/drm_atomic_state_helper.h> #include <drm/drm_bridge.h>
> > > +#include <drm/drm_connector.h> #include <drm/drm_crtc.h> #include
> > > +<drm/drm_edid.h> #include <drm/drm_of.h> #include
> > > +<drm/drm_probe_helper.h>
> > > +
> > > +/*
> > > +---------------------------------------------------------------------
> > > +--------
> > > + * LVDS registers
> > > + */
> > > +
> > > +/* LVDS software reset registers */
> > > +#define LVDS_REG_05 0x05
> > > +#define REG_SOFT_P_RST BIT(1)
> > > +
> > > +/* LVDS system configuration registers */
> > > +/* 0x0b */
> > > +#define LVDS_REG_0B 0x0b
> > > +#define REG_SSC_PCLK_RF BIT(0)
> > > +#define REG_LVDS_IN_SWAP BIT(1)
> > > +
> > > +/* LVDS test pattern gen control registers */
> > > +/* 0x2c */
> > > +#define LVDS_REG_2C 0x2c
> > > +#define REG_COL_DEP GENMASK(1, 0)
> > > +#define BIT8 FIELD_PREP(REG_COL_DEP, 2)
> > > +#define OUT_MAP BIT(4)
> > > +#define JEIDA 0
> > > +#define REG_DESSC_ENB BIT(6)
> > > +#define DMODE BIT(7)
> > > +#define DISO BIT(7)
> > > +#define SISO 0
> > > +
> > > +#define LVDS_REG_3C 0x3c
> > > +#define LVDS_REG_3F 0x3f
> > > +#define LVDS_REG_47 0x47
> > > +#define LVDS_REG_48 0x48
> > > +#define LVDS_REG_4F 0x4f
> > > +#define LVDS_REG_52 0x52
> > > +
> > > +/*
> > > +---------------------------------------------------------------------
> > > +--------
> > > + * HDMI registers are separated into three banks:
> > > + * 1) HDMI register common bank: 0x00 ~ 0x2f */
> > > +
> > > +/* HDMI genernal registers */
> > > +#define HDMI_REG_SW_RST 0x04
> > > +#define SOFTREF_RST BIT(5)
> > > +#define SOFTA_RST BIT(4)
> > > +#define SOFTV_RST BIT(3)
> > > +#define AUD_RST BIT(2)
> > > +#define HDCP_RST BIT(0)
> > > +#define HDMI_RST_ALL (SOFTREF_RST | SOFTA_RST | SOFTV_RST | \
> > > + AUD_RST | HDCP_RST)
> > > +
> > > +#define HDMI_REG_SYS_STATUS 0x0e
> > > +#define HPDETECT BIT(6)
> > > +#define TXVIDSTABLE BIT(4)
> > > +
> > > +#define HDMI_REG_BANK_CTRL 0x0f
> > > +#define REG_BANK_SEL BIT(0)
> > > +
> > > +/* HDMI System DDC control registers */
> > > +#define HDMI_REG_DDC_MASTER_CTRL 0x10
> > > +#define MASTER_SEL_HOST BIT(0)
> > > +
> > > +#define HDMI_REG_DDC_HEADER 0x11
> > > +
> > > +#define HDMI_REG_DDC_REQOFF 0x12
> > > +#define HDMI_REG_DDC_REQCOUNT 0x13
> > > +#define HDMI_REG_DDC_EDIDSEG 0x14
> > > +
> > > +#define HDMI_REG_DDC_CMD 0x15
> > > +#define DDC_CMD_EDID_READ 0x3
> > > +#define DDC_CMD_FIFO_CLR 0x9
> > > +
> > > +#define HDMI_REG_DDC_STATUS 0x16
> > > +#define DDC_DONE BIT(7)
> > > +#define DDC_NOACK BIT(5)
> > > +#define DDC_WAITBUS BIT(4)
> > > +#define DDC_ARBILOSE BIT(3)
> > > +#define DDC_ERROR (DDC_NOACK | DDC_WAITBUS | DDC_ARBILOSE)
> > > +
> > > +#define HDMI_DDC_FIFO_BYTES 32
> > > +#define HDMI_REG_DDC_READFIFO 0x17
> > > +#define HDMI_REG_LVDS_PORT 0x1d /* LVDS input control I2C addr */
> > > +#define HDMI_REG_LVDS_PORT_EN 0x1e
> > > +#define LVDS_INPUT_CTRL_I2C_ADDR 0x33
> > > +
> > > +/*
> > > +---------------------------------------------------------------------
> > > +--------
> > > + * 2) HDMI register bank0: 0x30 ~ 0xff */
> > > +
> > > +/* HDMI AFE registers */
> > > +#define HDMI_REG_AFE_DRV_CTRL 0x61
> > > +#define AFE_DRV_PWD BIT(5)
> > > +#define AFE_DRV_RST BIT(4)
> > > +
> > > +#define HDMI_REG_AFE_XP_CTRL 0x62
> > > +#define AFE_XP_GAINBIT BIT(7)
> > > +#define AFE_XP_ER0 BIT(4)
> > > +#define AFE_XP_RESETB BIT(3)
> > > +
> > > +#define HDMI_REG_AFE_ISW_CTRL 0x63
> > > +
> > > +#define HDMI_REG_AFE_IP_CTRL 0x64
> > > +#define AFE_IP_GAINBIT BIT(7)
> > > +#define AFE_IP_ER0 BIT(3)
> > > +#define AFE_IP_RESETB BIT(2)
> > > +
> > > +/* HDMI input data format registers */
> > > +#define HDMI_REG_INPUT_MODE 0x70
> > > +#define IN_RGB 0x00
> > > +
> > > +/* HDMI general control registers */
> > > +#define HDMI_REG_HDMI_MODE 0xc0
> > > +#define TX_HDMI_MODE BIT(0)
> > > +
> > > +#define HDMI_REG_GCP 0xc1
> > > +#define AVMUTE BIT(0)
> > > +#define HDMI_COLOR_DEPTH GENMASK(6, 4)
> > > +#define HDMI_COLOR_DEPTH_24 FIELD_PREP(HDMI_COLOR_DEPTH, 4)
> > > +
> > > +#define HDMI_REG_PKT_GENERAL_CTRL 0xc6
> > > +#define ENABLE_PKT BIT(0)
> > > +#define REPEAT_PKT BIT(1)
> > > +
> > > +/*
> > > +---------------------------------------------------------------------
> > > +--------
> > > + * 3) HDMI register bank1: 0x130 ~ 0x1ff (HDMI packet registers) */
> > > +
> > > +/* AVI packet registers */
> > > +#define HDMI_REG_AVI_DB1 0x158
> > > +#define HDMI_REG_AVI_DB2 0x159
> > > +#define HDMI_REG_AVI_DB3 0x15a
> > > +#define HDMI_REG_AVI_DB4 0x15b
> > > +#define HDMI_REG_AVI_DB5 0x15c
> > > +#define HDMI_REG_AVI_CSUM 0x15d
> > > +#define HDMI_REG_AVI_DB6 0x15e
> > > +#define HDMI_REG_AVI_DB7 0x15f
> > > +#define HDMI_REG_AVI_DB8 0x160
> > > +#define HDMI_REG_AVI_DB9 0x161
> > > +#define HDMI_REG_AVI_DB10 0x162
> > > +#define HDMI_REG_AVI_DB11 0x163
> > > +#define HDMI_REG_AVI_DB12 0x164
> > > +#define HDMI_REG_AVI_DB13 0x165
> > > +
> > > +#define HDMI_AVI_DB_CHUNK1_SIZE (HDMI_REG_AVI_DB5 - HDMI_REG_AVI_DB1 + 1)
> > > +#define HDMI_AVI_DB_CHUNK2_SIZE (HDMI_REG_AVI_DB13 - HDMI_REG_AVI_DB6 + 1)
> > > +
> > > +#define MAX_PIXEL_CLOCK_KHZ 150000
> > > +#define HIGH_PIXEL_CLOCK_KHZ 80000
> > > +
> > > +struct it6263 {
> > > + struct device *dev;
> > > + struct i2c_client *hdmi_i2c;
> > > + struct i2c_client *lvds_i2c;
> > > + struct regmap *hdmi_regmap;
> > > + struct regmap *lvds_regmap;
> > > + struct drm_bridge bridge;
> > > + struct drm_bridge *next_bridge;
> > > + struct drm_connector connector;
> > > + struct gpio_desc *reset_gpio;
> > > + u8 lvds_link_num_dlanes;
> > > + bool lvds_dual_link;
> > > + bool lvds_link12_swap;
> > > +};
> > > +
> > > +static inline struct it6263 *bridge_to_it6263(struct drm_bridge
> > > +*bridge) {
> > > + return container_of(bridge, struct it6263, bridge); }
> > > +
> > > +static inline struct it6263 *connector_to_it6263(struct drm_connector
> > > +*conn) {
> > > + return container_of(conn, struct it6263, connector); }
> > > +
> > > +static bool it6263_hdmi_writeable_reg(struct device *dev, unsigned
> > > +int reg) {
> > > + switch (reg) {
> > > + case HDMI_REG_SW_RST:
> > > + case HDMI_REG_BANK_CTRL:
> > > + case HDMI_REG_DDC_MASTER_CTRL:
> > > + case HDMI_REG_DDC_HEADER:
> > > + case HDMI_REG_DDC_REQOFF:
> > > + case HDMI_REG_DDC_REQCOUNT:
> > > + case HDMI_REG_DDC_EDIDSEG:
> > > + case HDMI_REG_DDC_CMD:
> > > + case HDMI_REG_LVDS_PORT:
> > > + case HDMI_REG_LVDS_PORT_EN:
> > > + case HDMI_REG_AFE_DRV_CTRL:
> > > + case HDMI_REG_AFE_XP_CTRL:
> > > + case HDMI_REG_AFE_ISW_CTRL:
> > > + case HDMI_REG_AFE_IP_CTRL:
> > > + case HDMI_REG_INPUT_MODE:
> > > + case HDMI_REG_HDMI_MODE:
> > > + case HDMI_REG_GCP:
> > > + case HDMI_REG_PKT_GENERAL_CTRL:
> > > + case HDMI_REG_AVI_DB1:
> > > + case HDMI_REG_AVI_DB2:
> > > + case HDMI_REG_AVI_DB3:
> > > + case HDMI_REG_AVI_DB4:
> > > + case HDMI_REG_AVI_DB5:
> > > + case HDMI_REG_AVI_CSUM:
> > > + case HDMI_REG_AVI_DB6:
> > > + case HDMI_REG_AVI_DB7:
> > > + case HDMI_REG_AVI_DB8:
> > > + case HDMI_REG_AVI_DB9:
> > > + case HDMI_REG_AVI_DB10:
> > > + case HDMI_REG_AVI_DB11:
> > > + case HDMI_REG_AVI_DB12:
> > > + case HDMI_REG_AVI_DB13:
> > > + return true;
> > > + default:
> > > + return false;
> > > + }
> > > +}
> > > +
> > > +static bool it6263_hdmi_readable_reg(struct device *dev, unsigned int
> > > +reg) {
> > > + if (it6263_hdmi_writeable_reg(dev, reg))
> > > + return true;
> > > +
> > > + switch (reg) {
> > > + case HDMI_REG_SYS_STATUS:
> > > + case HDMI_REG_DDC_STATUS:
> > > + case HDMI_REG_DDC_READFIFO:
> > > + return true;
> > > + default:
> > > + return false;
> > > + }
> > > +}
> > > +
> > > +static bool it6263_hdmi_volatile_reg(struct device *dev, unsigned int
> > > +reg) {
> > > + switch (reg) {
> > > + case HDMI_REG_SW_RST:
> > > + case HDMI_REG_SYS_STATUS:
> > > + case HDMI_REG_DDC_STATUS:
> > > + case HDMI_REG_DDC_READFIFO:
> > > + return true;
> > > + default:
> > > + return false;
> > > + }
> > > +}
> > > +
> > > +static const struct regmap_range_cfg it6263_hdmi_range_cfg = {
> > > + .range_min = 0x00,
> > > + .range_max = HDMI_REG_AVI_DB13,
> > > + .selector_reg = HDMI_REG_BANK_CTRL,
> > > + .selector_mask = REG_BANK_SEL,
> > > + .selector_shift = 0,
> > > + .window_start = 0x00,
> > > + .window_len = 0x100,
> > > +};
> > > +
> > > +static const struct regmap_config it6263_hdmi_regmap_config = {
> > > + .name = "it6263-hdmi",
> > > + .reg_bits = 8,
> > > + .val_bits = 8,
> > > + .writeable_reg = it6263_hdmi_writeable_reg,
> > > + .readable_reg = it6263_hdmi_readable_reg,
> > > + .volatile_reg = it6263_hdmi_volatile_reg,
> > > + .max_register = HDMI_REG_AVI_DB13,
> > > + .ranges = &it6263_hdmi_range_cfg,
> > > + .num_ranges = 1,
> > > + .cache_type = REGCACHE_MAPLE,
> > > +};
> > > +
> > > +static bool it6263_lvds_writeable_reg(struct device *dev, unsigned
> > > +int reg) {
> > > + switch (reg) {
> > > + case LVDS_REG_05:
> > > + case LVDS_REG_0B:
> > > + case LVDS_REG_2C:
> > > + case LVDS_REG_3C:
> > > + case LVDS_REG_3F:
> > > + case LVDS_REG_47:
> > > + case LVDS_REG_48:
> > > + case LVDS_REG_4F:
> > > + case LVDS_REG_52:
> > > + return true;
> > > + default:
> > > + return false;
> > > + }
> > > +}
> > > +
> > > +static bool it6263_lvds_readable_reg(struct device *dev, unsigned int
> > > +reg) {
> > > + return it6263_lvds_writeable_reg(dev, reg); }
> > > +
> > > +static bool it6263_lvds_volatile_reg(struct device *dev, unsigned int
> > > +reg) {
> > > + return reg == LVDS_REG_05;
> > > +}
> > > +
> > > +static const struct regmap_config it6263_lvds_regmap_config = {
> > > + .name = "it6263-lvds",
> > > + .reg_bits = 8,
> > > + .val_bits = 8,
> > > + .writeable_reg = it6263_lvds_writeable_reg,
> > > + .readable_reg = it6263_lvds_readable_reg,
> > > + .volatile_reg = it6263_lvds_volatile_reg,
> > > + .max_register = LVDS_REG_52,
> > > + .cache_type = REGCACHE_MAPLE,
> > > +};
> > > +
> > > +static const char * const it6263_supplies[] = {
> > > + "ivdd", "ovdd", "txavcc18", "txavcc33", "pvcc1", "pvcc2",
> > > + "avcc", "anvdd", "apvdd"
> > > +};
> > > +
> > > +static int it6263_parse_dt(struct it6263 *it) {
> > > + struct device *dev = it->dev;
> > > + struct device_node *port0, *port1;
> > > + int ret;
> > > +
> > > + ret = of_property_read_u8(dev->of_node, "ite,lvds-link-num-data-lanes",
> > > + &it->lvds_link_num_dlanes);
> > > + if (ret) {
> > > + dev_err(dev, "failed to get LVDS link number of data lanes: %d\n",
> > > + ret);
> > > + return ret;
> > > + }
> > > +
> > > + it->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0);
> > > + if (IS_ERR(it->next_bridge))
> > > + return dev_err_probe(dev, PTR_ERR(it->next_bridge),
> > > + "failed to get next bridge\n");
> > > +
> > > + port0 = of_graph_get_port_by_id(dev->of_node, 0);
> > > + port1 = of_graph_get_port_by_id(dev->of_node, 1);
> > > + if (port0 && port1) {
> > > + if (of_property_read_bool(port0, "dual-lvds-even-pixels") &&
> > > + of_property_read_bool(port1, "dual-lvds-odd-pixels")) {
> > > + it->lvds_dual_link = true;
> > > + it->lvds_link12_swap = true;
> >
> > This is a nice name for the propery in the Dual Link LVDS case:
> >
> > ite,lvds-link-swap
> >
> >
> > > + } else if (of_property_read_bool(port0, "dual-lvds-odd-pixels") &&
> > > + of_property_read_bool(port1, "dual-lvds-even-pixels")) {
> > > + it->lvds_dual_link = true;
> > > + }
> > > +
> > > + if (!it->lvds_dual_link) {
> > > + dev_err(dev,
> > > + "failed to get LVDS dual link pixel order\n");
> > > + ret = -EINVAL;
> > > + }
> > > + } else if (port1) {
> > > + ret = -EINVAL;
> > > + dev_err(dev, "single input LVDS port1 is not supported\n");
> > > + } else if (!port0) {
> > > + ret = -EINVAL;
> > > + dev_err(dev, "no input LVDS port\n");
> > > + }
> > > +
> > > + of_node_put(port0);
> > > + of_node_put(port1);
> > > +
> > > + return ret;
> > > +}
> > > +
> > > +static inline void it6263_hw_reset(struct it6263 *it) {
> > > + if (!it->reset_gpio)
> > > + return;
> > > +
> > > + gpiod_set_value_cansleep(it->reset_gpio, 0);
> > > + fsleep(1000);
> > > + gpiod_set_value_cansleep(it->reset_gpio, 1);
> > > + /* The chip maker says the low pulse should be at least 40ms. */
> > > + fsleep(40000);
> > > + gpiod_set_value_cansleep(it->reset_gpio, 0);
> > > + /* addtional time to wait the high voltage to be stable */
> > > + fsleep(5000);
> > > +}
> > > +
> > > +static inline int it6263_lvds_set_i2c_addr(struct it6263 *it) {
> > > + int ret;
> > > +
> > > + ret = regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT,
> > > + LVDS_INPUT_CTRL_I2C_ADDR << 1);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + return regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT_EN, BIT(0));
> > > +}
> > > +
> > > +static inline void it6263_lvds_reset(struct it6263 *it) {
> > > + /* AFE PLL reset */
> > > + regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), 0x0);
> > > + fsleep(1000);
> > > + regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), BIT(0));
> > > +
> > > + /* software pixel clock domain reset */
> > > + regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST,
> > > + REG_SOFT_P_RST);
> > > + fsleep(1000);
> > > + regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST, 0x0);
> > > + fsleep(10000);
> > > +}
> > > +
> > > +static inline void it6263_lvds_set_interface(struct it6263 *it) {
> > > + /* color depth */
> > > + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_COL_DEP, BIT8);
> > > + /* output mapping */
> > > + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, OUT_MAP, JEIDA);
> > > +
> > > + if (it->lvds_dual_link) {
> > > + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, DISO);
> > > + regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), BIT(1));
> > > + } else {
> > > + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, SISO);
> > > + regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), 0);
> > > + }
> > > +}
> > > +
> > > +static inline void it6263_lvds_set_afe(struct it6263 *it) {
> > > + regmap_write(it->lvds_regmap, LVDS_REG_3C, 0xaa);
> > > + regmap_write(it->lvds_regmap, LVDS_REG_3F, 0x02);
> > > + regmap_write(it->lvds_regmap, LVDS_REG_47, 0xaa);
> > > + regmap_write(it->lvds_regmap, LVDS_REG_48, 0x02);
> > > + regmap_write(it->lvds_regmap, LVDS_REG_4F, 0x11);
> > > +
> > > + regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_SSC_PCLK_RF,
> > > + REG_SSC_PCLK_RF);
> > > + regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, 0x07, 0);
> > > + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_DESSC_ENB,
> > > + REG_DESSC_ENB);
> > > +}
> > > +
> > > +static inline void it6263_lvds_sys_cfg(struct it6263 *it) {
> > > + regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_LVDS_IN_SWAP,
> > > + it->lvds_link12_swap ? REG_LVDS_IN_SWAP : 0); }
> > > +
> > > +static inline void it6263_lvds_config(struct it6263 *it) {
> > > + it6263_lvds_reset(it);
> > > + it6263_lvds_set_interface(it);
> > > + it6263_lvds_set_afe(it);
> > > + it6263_lvds_sys_cfg(it);
> > > +}
> > > +
> > > +static inline void it6263_hdmi_config(struct it6263 *it) {
> > > + regmap_write(it->hdmi_regmap, HDMI_REG_SW_RST, HDMI_RST_ALL);
> > > + regmap_write(it->hdmi_regmap, HDMI_REG_INPUT_MODE, IN_RGB);
> > > + regmap_write_bits(it->hdmi_regmap, HDMI_REG_GCP, HDMI_COLOR_DEPTH,
> > > + HDMI_COLOR_DEPTH_24);
> > > +}
> > > +
> > > +static enum drm_connector_status it6263_detect(struct it6263 *it) {
> > > + unsigned int val;
> > > +
> > > + regmap_read(it->hdmi_regmap, HDMI_REG_SYS_STATUS, &val);
> > > + if (val & HPDETECT)
> > > + return connector_status_connected;
> > > + else
> > > + return connector_status_disconnected; }
> > > +
> > > +static enum drm_connector_status
> > > +it6263_connector_detect(struct drm_connector *connector, bool force)
> > > +{
> > > + struct it6263 *it = connector_to_it6263(connector);
> > > +
> > > + return it6263_detect(it);
> > > +}
> > > +
> > > +static const struct drm_connector_funcs it6263_connector_funcs = {
> > > + .detect = it6263_connector_detect,
> > > + .fill_modes = drm_helper_probe_single_connector_modes,
> > > + .destroy = drm_connector_cleanup,
> > > + .reset = drm_atomic_helper_connector_reset,
> > > + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
> > > + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> > > +};
> > > +
> > > +static int it6263_read_edid(void *data, u8 *buf, unsigned int block,
> > > +size_t len) {
> > > + struct it6263 *it = data;
> > > + struct regmap *regmap = it->hdmi_regmap;
> > > + unsigned int start = (block % 2) * EDID_LENGTH;
> > > + unsigned int segment = block >> 1;
> > > + unsigned int count, val;
> > > + int ret;
> > > +
> > > + regmap_write(regmap, HDMI_REG_DDC_MASTER_CTRL, MASTER_SEL_HOST);
> > > + regmap_write(regmap, HDMI_REG_DDC_HEADER, DDC_ADDR << 1);
> > > + regmap_write(regmap, HDMI_REG_DDC_EDIDSEG, segment);
> > > +
> > > + while (len) {
> > > + /* clear DDC FIFO */
> > > + regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_FIFO_CLR);
> > > +
> > > + ret = regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS,
> > > + val, val & DDC_DONE,
> > > + 2000, 10000);
> > > + if (ret) {
> > > + dev_err(it->dev, "failed to clear DDC FIFO:%d\n", ret);
> > > + return ret;
> > > + }
> > > +
> > > + count = len > HDMI_DDC_FIFO_BYTES ? HDMI_DDC_FIFO_BYTES : len;
> > > +
> > > + /* fire the read command */
> > > + regmap_write(regmap, HDMI_REG_DDC_REQOFF, start);
> > > + regmap_write(regmap, HDMI_REG_DDC_REQCOUNT, count);
> > > + regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_EDID_READ);
> > > +
> > > + start += count;
> > > + len -= count;
> > > +
> > > + ret = regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS, val,
> > > + val & (DDC_DONE | DDC_ERROR),
> > > + 20000, 250000);
> > > + if (ret && !(val & DDC_ERROR)) {
> > > + dev_err(it->dev, "failed to read EDID:%d\n", ret);
> > > + return ret;
> > > + }
> > > +
> > > + if (val & DDC_ERROR) {
> > > + dev_err(it->dev, "DDC error\n");
> > > + return -EIO;
> > > + }
> > > +
> > > + /* cache to buffer */
> > > + for (; count > 0; count--) {
> > > + regmap_read(regmap, HDMI_REG_DDC_READFIFO, &val);
> > > + *(buf++) = val;
> > > + }
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int it6263_connector_get_modes(struct drm_connector
> > > +*connector) {
> > > + struct it6263 *it = connector_to_it6263(connector);
> > > + const struct drm_edid *drm_edid;
> > > + int count;
> > > +
> > > + drm_edid = drm_edid_read_custom(connector, it6263_read_edid, it);
> > > +
> > > + drm_edid_connector_update(connector, drm_edid);
> > > + count = drm_edid_connector_add_modes(connector);
> > > +
> > > + drm_edid_free(drm_edid);
> > > +
> > > + return count;
> > > +}
> > > +
> > > +static const struct drm_connector_helper_funcs it6263_connector_helper_funcs = {
> > > + .get_modes = it6263_connector_get_modes, };
> > > +
> > > +static int it6263_bridge_atomic_check(struct drm_bridge *bridge,
> > > + struct drm_bridge_state *bridge_state,
> > > + struct drm_crtc_state *crtc_state,
> > > + struct drm_connector_state *conn_state) {
> > > + struct drm_display_mode *mode = &crtc_state->adjusted_mode;
> >
> > Use drm_atomic_helper_connector_hdmi_check().
> >
> > Implement .hdmi_tmds_char_rate_valid(). Also, I think, single and dual link LVDS have different max
> > clock rates. Please correct me if I'm wrong.
>
> I guess this rate will be same for both links in dual lvds mode.
> For single link, it supports only link0.
> We cannot operate link1 its Own.
>
> From ITE point the max rate is rate corresponding to 1080p(148-150MHz)
>
> single and dual link LVDS have different max clock rates, but that constraint is
> in SoC side?? ITE HW manual does not mention about this.
Huh? I checked the datasheet, version 0.8.
It specifies LVDS clock rate (not the mode clock) up to 150 MHz and HDMI
rate up to 225 MHz. Please check both constraints.
>
> >
> > > +
> > > + return mode->clock > MAX_PIXEL_CLOCK_KHZ ? -EINVAL : 0; }
> > > +
[...]
> > > +
> > > + it->lvds_regmap = devm_regmap_init_i2c(it->lvds_i2c,
> > > + &it6263_lvds_regmap_config);
> > > + if (IS_ERR(it->lvds_regmap))
> > > + return dev_err_probe(dev, PTR_ERR(it->lvds_regmap),
> > > + "failed to init I2C regmap for LVDS\n");
> > > +
> > > + it6263_lvds_config(it);
> > > + it6263_hdmi_config(it);
> > > +
> > > + i2c_set_clientdata(client, it);
> > > +
> > > + it->bridge.funcs = &it6263_bridge_funcs;
> > > + it->bridge.of_node = dev->of_node;
> > > + it->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT;
> >
> > | DRM_BRIDGE_OP_HDMI
> >
> > BTW: No HPD IRQ support?
>
> Renesas SMARC RZ/G3E this signal is internal. No dedicted IRQ line
> Populated for this signal. I don't know about NXP and any other platforms
> has HPD wired to test the HPD IRQ support.
>
> Maybe go with poll method now and add hot plug support,
> when we have platform with HPD to test.
I'm fine with this. According to the datasheet it doesn't seem to have
the IRQ pin at all. It's just surprising to me. It's be nice to mention
that HW doesn't support HPD IRQ either before setting it->bridge.ops or
in the commit message.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-13 23:45 ` Dmitry Baryshkov
@ 2024-10-14 5:33 ` Liu Ying
2024-10-14 5:54 ` Liu Ying
` (3 more replies)
0 siblings, 4 replies; 49+ messages in thread
From: Liu Ying @ 2024-10-14 5:33 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel,
andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
arnd, nfraprado, o.rempel, y.moog, marex, isaac.scott,
biju.das.jz
On 10/14/2024, Dmitry Baryshkov wrote:
> On Sat, Oct 12, 2024 at 05:14:13PM +0800, Liu Ying wrote:
>> On 10/12/2024, Dmitry Baryshkov wrote:
>>> On Sat, Oct 12, 2024 at 03:35:39PM +0800, Liu Ying wrote:
>>>> Document ITE IT6263 LVDS to HDMI converter.
>>>>
>>>> Product link:
>>>> https://www.ite.com.tw/en/product/cate1/IT6263
>>>>
>>>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
>>>> ---
>>>> v2:
>>>> * Document number of LVDS link data lanes. (Biju)
>>>> * Simplify ports property by dropping "oneOf". (Rob)
>>>>
>>>> .../bindings/display/bridge/ite,it6263.yaml | 276 ++++++++++++++++++
>>>> 1 file changed, 276 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
>>>> new file mode 100644
>>>> index 000000000000..bc2bbec07623
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
>>>> @@ -0,0 +1,276 @@
>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>> +%YAML 1.2
>>>> +---
>>>> +$id: http://devicetree.org/schemas/display/bridge/ite,it6263.yaml#
>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: ITE IT6263 LVDS to HDMI converter
>>>> +
>>>> +maintainers:
>>>> + - Liu Ying <victor.liu@nxp.com>
>>>> +
>>>> +description: |
>>>> + The IT6263 is a high-performance single-chip De-SSC(De-Spread Spectrum) LVDS
>>>> + to HDMI converter. Combined with LVDS receiver and HDMI 1.4a transmitter,
>>>> + the IT6263 supports LVDS input and HDMI 1.4 output by conversion function.
>>>> + The built-in LVDS receiver can support single-link and dual-link LVDS inputs,
>>>> + and the built-in HDMI transmitter is fully compliant with HDMI 1.4a/3D, HDCP
>>>> + 1.2 and backward compatible with DVI 1.0 specification.
>>>> +
>>>> + The IT6263 also encodes and transmits up to 8 channels of I2S digital audio,
>>>> + with sampling rate up to 192KHz and sample size up to 24 bits. In addition,
>>>> + an S/PDIF input port takes in compressed audio of up to 192KHz frame rate.
>>>> +
>>>> + The newly supported High-Bit Rate(HBR) audio by HDMI specifications v1.3 is
>>>> + provided by the IT6263 in two interfaces: the four I2S input ports or the
>>>> + S/PDIF input port. With both interfaces the highest possible HBR frame rate
>>>> + is supported at up to 768KHz.
>>>> +
>>>> +properties:
>>>
>>> No LVDS data-mapping support?
>>
>> It is enough to document number of LVDS link data lanes
>> because OS should be able to determine the data-mapping
>> by looking at the number and the data-mapping capability
>> of the other side of the LVDS link.
>
> From what I can see, data-mapping is specified on the consumer sink side
> of the LVDS link. This means it should go to the bridge's device node.
Then, I won't define data-lanes, because data-mapping implies it,
e.g., jeida-24 implies data lanes 0/1/2/3, see lvds-data-mapping.yaml.
Please let me know which one you prefer.
>
>>
>>>
>>>> + compatible:
>>>> + const: ite,it6263
>>>> +
>>>> + reg:
>>>> + maxItems: 1
>>>> +
>>>> + clocks:
>>>> + maxItems: 1
>>>> + description: audio master clock
>>>> +
>>>> + clock-names:
>>>> + const: mclk
>>>> +
>>>> + reset-gpios:
>>>> + maxItems: 1
>>>> +
>>>> + ivdd-supply:
>>>> + description: 1.8V digital logic power
>>>> +
>>>> + ovdd-supply:
>>>> + description: 3.3V I/O pin power
>>>> +
>>>> + txavcc18-supply:
>>>> + description: 1.8V HDMI analog frontend power
>>>> +
>>>> + txavcc33-supply:
>>>> + description: 3.3V HDMI analog frontend power
>>>> +
>>>> + pvcc1-supply:
>>>> + description: 1.8V HDMI frontend core PLL power
>>>> +
>>>> + pvcc2-supply:
>>>> + description: 1.8V HDMI frontend filter PLL power
>>>> +
>>>> + avcc-supply:
>>>> + description: 3.3V LVDS frontend power
>>>> +
>>>> + anvdd-supply:
>>>> + description: 1.8V LVDS frontend analog power
>>>> +
>>>> + apvdd-supply:
>>>> + description: 1.8V LVDS frontend PLL power
>>>> +
>>>> + "#sound-dai-cells":
>>>> + const: 0
>>>> +
>>>> + ite,lvds-link-num-data-lanes:
>>>> + $ref: /schemas/types.yaml#/definitions/uint8
>>>> + enum: [3, 4, 5]
>>>> + description: number of data lanes per LVDS link
>>>
>>> Please use data-lanes property inside the OF graph.
>>
>> In both port@0 and port@1?
>
> Yes
I'm assuming if data-mapping is defined, then no need to
define data-lanes.
>
>>
>>>
>>>> +
>>>> + ite,i2s-audio-fifo-sources:
>>>> + $ref: /schemas/types.yaml#/definitions/uint32-array
>>>> + minItems: 1
>>>> + maxItems: 4
>>>> + items:
>>>> + enum: [0, 1, 2, 3]
>>>> + description:
>>>> + Each array element indicates the pin number of an I2S serial data input
>>>> + line which is connected to an audio FIFO, from audio FIFO0 to FIFO3.
>>>
>>> What does that mean from the board point of view? Routed audio links for
>>> the multichannel audio?
>>
>> Yes, also for single channel audio.
>>
>>>
>>>> +
>>>> + ite,rl-channel-swap-audio-sources:
>>>> + $ref: /schemas/types.yaml#/definitions/uint32-array
>>>> + minItems: 1
>>>> + maxItems: 4
>>>> + uniqueItems: true
>>>> + items:
>>>> + enum: [0, 1, 2, 3]
>>>> + description:
>>>> + Each array element indicates an audio source whose right channel and left
>>>> + channel are swapped by this converter. For I2S, the element is the pin
>>>> + number of an I2S serial data input line. For S/PDIF, the element is always
>>>> + 0.
>>>
>>> Why?
>>
>> Because this converter has the capability to swap right channel
>> and left channel and S/PDIF always uses audio source0.
>>
>>>
>>>> +
>>>> + ports:
>>>> + $ref: /schemas/graph.yaml#/properties/ports
>>>> +
>>>> + properties:
>>>> + port@0:
>>>> + $ref: /schemas/graph.yaml#/$defs/port-base
>>>> + unevaluatedProperties: false
>>>> + description:
>>>> + The first LVDS input link.
>>>> + In dual-link LVDS mode, this link works together with the second LVDS
>>>> + input link, and one link receives odd pixels while the other receives
>>>> + even pixels. Specify the pixels with one of the dual-lvds-odd-pixels
>>>> + and dual-lvds-even-pixels properties when and only when dual-link LVDS
>>>> + mode is used.
>>>> +
>>>> + properties:
>>>> + dual-lvds-odd-pixels:
>>>> + type: boolean
>>>> + description: the first sink port for odd pixels
>>>> +
>>>> + dual-lvds-even-pixels:
>>>> + type: boolean
>>>> + description: the first sink port for even pixels
>>>> +
>>>> + port@1:
>>>> + $ref: /schemas/graph.yaml#/$defs/port-base
>>>> + unevaluatedProperties: false
>>>> + description: the second LVDS input link
>>>> +
>>>> + properties:
>>>> + dual-lvds-even-pixels:
>>>> + type: boolean
>>>> + description: the second sink port for even pixels
>>>> +
>>>> + dual-lvds-odd-pixels:
>>>> + type: boolean
>>>> + description: the second sink port for odd pixels
>>>> +
>>>> + oneOf:
>>>> + - required: [dual-lvds-even-pixels]
>>>> + - required: [dual-lvds-odd-pixels]
>>>
>>> This still allows one to specify that both ports provide odd pixels. Is
>>> that expected? Also why do you need two properties which specify the
>>> same option.
>>
>> No, that is not expected. Description for port@0 already mentions
>> one link receives odd pixels while the other receives even pixels.
>
> That's not expected, but permitted by the bindings.
It is not permitted by port@1. If "dual-lvds-odd-pixels;" is added
to port@1 in the dual-link LVDS example, the below warning will be
generated by dt_binding_check.
Documentation/devicetree/bindings/display/bridge/ite,it6263.example.dtb: hdmi@4c: ports:port@1: {'reg': [[1]], 'dual-lvds-even-pixels': True, 'dual-lvds-odd-pixels': True, 'endpoint': {'remote-endpoint': [[4294967295]]}} is valid under each of {'required': ['dual-lvds-odd-pixels']}, {'required': ['dual-lvds-even-pixels']}
from schema $id: http://devicetree.org/schemas/display/bridge/ite,it6263.yaml#
However, the binding for port@0 does allow DT writers to specify
both even and odd pixels. I raised similar concerns in v1 discussion.
According to Rob's comment in #devicetree IRC, the ports property
is simplified to this form and more description for port@0 is added
to tell when to specify the even/odd pixels. If you know any better
way to indicate the constraints, please shout.
>
>>
>> Two options are supported for dual-link LVDS, not the same option:
>> 1) LVDS link1(port@0) gets odd pixels
>> and
>> LVDS link2(port@1) gets even pixels.
>>
>> 2) LVDS link1(port@0) gets even pixels
>> and
>> LVDS link2(port@1) gets odd pixels.
>> That's the reason why each port needs two properties to define
>> odd/even pixels.
>>
>>>
>>> My suggestion would be to add a single root-level property which
>>> specifies which port provides even pixel data.
>>
>> That won't work. The LVDS source side expects the ports of
>> the sink side specify dual-lvds-{odd,even}-pixels properties.
>
> I didn't notice that these properties are already defined.
>
> As these properties are common between several schema files, please
> extract them to a common schema file (like lvds.yaml).
I'm not sure how to do that. Is it obvious?
Please shed some light.
Only two panel schema files are defining even/odd pixels now -
advantech,idk-2121wr.yaml and panel-simple-lvds-dual-ports.yaml.
Maybe, extract them later when more schema files(especially for
bridges) try to define the same? I'd like to keep a low profile
for now.
>
>>
>>>
>>>> +
>>>> + port@2:
>>>> + $ref: /schemas/graph.yaml#/properties/port
>>>> + description: video port for the HDMI output
>>>> +
>>>> + port@3:
>>>> + $ref: /schemas/graph.yaml#/properties/port
>>>> + description: sound input port
>>>> +
>>>> + required:
>>>> + - port@0
>>>> + - port@2
>>>> +
>>>> +required:
>>>> + - compatible
>>>> + - reg
>>>> + - ivdd-supply
>>>> + - ovdd-supply
>>>> + - txavcc18-supply
>>>> + - txavcc33-supply
>>>> + - pvcc1-supply
>>>> + - pvcc2-supply
>>>> + - avcc-supply
>>>> + - anvdd-supply
>>>> + - apvdd-supply
>>>> + - ite,lvds-link-num-data-lanes
>>>> + - ports
>>>> +
>>>> +additionalProperties: false
>>>> +
>>>> +examples:
>>>> + - |
>>>> + /* single-link LVDS input */
>>>> + #include <dt-bindings/gpio/gpio.h>
>>>> +
>>>> + i2c {
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> +
>>>> + hdmi@4c {
>>>> + compatible = "ite,it6263";
>>>> + reg = <0x4c>;
>>>> + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
>>>> + ivdd-supply = <®_buck5>;
>>>> + ovdd-supply = <®_vext_3v3>;
>>>> + txavcc18-supply = <®_buck5>;
>>>> + txavcc33-supply = <®_vext_3v3>;
>>>> + pvcc1-supply = <®_buck5>;
>>>> + pvcc2-supply = <®_buck5>;
>>>> + avcc-supply = <®_vext_3v3>;
>>>> + anvdd-supply = <®_buck5>;
>>>> + apvdd-supply = <®_buck5>;
>>>> + ite,lvds-link-num-data-lanes = /bits/ 8 <4>;
>>>> +
>>>> + ports {
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> +
>>>> + port@0 {
>>>> + reg = <0>;
>>>> +
>>>> + it6263_lvds_link1: endpoint {
>>>> + remote-endpoint = <&ldb_lvds_ch0>;
>>>> + };
>>>> + };
>>>> +
>>>> + port@2 {
>>>> + reg = <2>;
>>>> +
>>>> + it6263_out: endpoint {
>>>> + remote-endpoint = <&hdmi_in>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + - |
>>>> + /* dual-link LVDS input */
>>>> + #include <dt-bindings/gpio/gpio.h>
>>>> +
>>>> + i2c {
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> +
>>>> + hdmi@4c {
>>>> + compatible = "ite,it6263";
>>>> + reg = <0x4c>;
>>>> + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
>>>> + ivdd-supply = <®_buck5>;
>>>> + ovdd-supply = <®_vext_3v3>;
>>>> + txavcc18-supply = <®_buck5>;
>>>> + txavcc33-supply = <®_vext_3v3>;
>>>> + pvcc1-supply = <®_buck5>;
>>>> + pvcc2-supply = <®_buck5>;
>>>> + avcc-supply = <®_vext_3v3>;
>>>> + anvdd-supply = <®_buck5>;
>>>> + apvdd-supply = <®_buck5>;
>>>> + ite,lvds-link-num-data-lanes = /bits/ 8 <4>;
>>>> +
>>>> + ports {
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> +
>>>> + port@0 {
>>>> + reg = <0>;
>>>> + dual-lvds-odd-pixels;
>>>> +
>>>> + it6263_lvds_link1_dual: endpoint {
>>>> + remote-endpoint = <&ldb_lvds_ch0>;
>>>> + };
>>>> + };
>>>> +
>>>> + port@1 {
>>>> + reg = <1>;
>>>> + dual-lvds-even-pixels;
>>>> +
>>>> + it6263_lvds_link2_dual: endpoint {
>>>> + remote-endpoint = <&ldb_lvds_ch1>;
>>>> + };
>>>> + };
>>>> +
>>>> + port@2 {
>>>> + reg = <2>;
>>>> +
>>>> + it6263_out_dual: endpoint {
>>>> + remote-endpoint = <&hdmi_in>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> --
>>>> 2.34.1
>>>>
>>>
>>
>> --
>> Regards,
>> Liu Ying
>>
>
--
Regards,
Liu Ying
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-14 5:33 ` Liu Ying
@ 2024-10-14 5:54 ` Liu Ying
2024-10-14 7:07 ` Dmitry Baryshkov
` (2 subsequent siblings)
3 siblings, 0 replies; 49+ messages in thread
From: Liu Ying @ 2024-10-14 5:54 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel,
andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
arnd, nfraprado, o.rempel, y.moog, marex, isaac.scott,
biju.das.jz
On 10/14/2024, Liu Ying wrote:
> On 10/14/2024, Dmitry Baryshkov wrote:
>> On Sat, Oct 12, 2024 at 05:14:13PM +0800, Liu Ying wrote:
>>> On 10/12/2024, Dmitry Baryshkov wrote:
>>>> On Sat, Oct 12, 2024 at 03:35:39PM +0800, Liu Ying wrote:
>>>>> Document ITE IT6263 LVDS to HDMI converter.
>>>>>
>>>>> Product link:
>>>>> https://www.ite.com.tw/en/product/cate1/IT6263
>>>>>
>>>>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
>>>>> ---
>>>>> v2:
>>>>> * Document number of LVDS link data lanes. (Biju)
>>>>> * Simplify ports property by dropping "oneOf". (Rob)
>>>>>
>>>>> .../bindings/display/bridge/ite,it6263.yaml | 276 ++++++++++++++++++
>>>>> 1 file changed, 276 insertions(+)
>>>>> create mode 100644 Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
>>>>> new file mode 100644
>>>>> index 000000000000..bc2bbec07623
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
>>>>> @@ -0,0 +1,276 @@
>>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>>> +%YAML 1.2
>>>>> +---
>>>>> +$id: http://devicetree.org/schemas/display/bridge/ite,it6263.yaml#
>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>> +
>>>>> +title: ITE IT6263 LVDS to HDMI converter
>>>>> +
>>>>> +maintainers:
>>>>> + - Liu Ying <victor.liu@nxp.com>
>>>>> +
>>>>> +description: |
>>>>> + The IT6263 is a high-performance single-chip De-SSC(De-Spread Spectrum) LVDS
>>>>> + to HDMI converter. Combined with LVDS receiver and HDMI 1.4a transmitter,
>>>>> + the IT6263 supports LVDS input and HDMI 1.4 output by conversion function.
>>>>> + The built-in LVDS receiver can support single-link and dual-link LVDS inputs,
>>>>> + and the built-in HDMI transmitter is fully compliant with HDMI 1.4a/3D, HDCP
>>>>> + 1.2 and backward compatible with DVI 1.0 specification.
>>>>> +
>>>>> + The IT6263 also encodes and transmits up to 8 channels of I2S digital audio,
>>>>> + with sampling rate up to 192KHz and sample size up to 24 bits. In addition,
>>>>> + an S/PDIF input port takes in compressed audio of up to 192KHz frame rate.
>>>>> +
>>>>> + The newly supported High-Bit Rate(HBR) audio by HDMI specifications v1.3 is
>>>>> + provided by the IT6263 in two interfaces: the four I2S input ports or the
>>>>> + S/PDIF input port. With both interfaces the highest possible HBR frame rate
>>>>> + is supported at up to 768KHz.
>>>>> +
>>>>> +properties:
>>>>
>>>> No LVDS data-mapping support?
>>>
>>> It is enough to document number of LVDS link data lanes
>>> because OS should be able to determine the data-mapping
>>> by looking at the number and the data-mapping capability
>>> of the other side of the LVDS link.
>>
>> From what I can see, data-mapping is specified on the consumer sink side
>> of the LVDS link. This means it should go to the bridge's device node.
>
> Then, I won't define data-lanes, because data-mapping implies it,
> e.g., jeida-24 implies data lanes 0/1/2/3, see lvds-data-mapping.yaml.
>
> Please let me know which one you prefer.
>
>>
>>>
>>>>
>>>>> + compatible:
>>>>> + const: ite,it6263
>>>>> +
>>>>> + reg:
>>>>> + maxItems: 1
>>>>> +
>>>>> + clocks:
>>>>> + maxItems: 1
>>>>> + description: audio master clock
>>>>> +
>>>>> + clock-names:
>>>>> + const: mclk
>>>>> +
>>>>> + reset-gpios:
>>>>> + maxItems: 1
>>>>> +
>>>>> + ivdd-supply:
>>>>> + description: 1.8V digital logic power
>>>>> +
>>>>> + ovdd-supply:
>>>>> + description: 3.3V I/O pin power
>>>>> +
>>>>> + txavcc18-supply:
>>>>> + description: 1.8V HDMI analog frontend power
>>>>> +
>>>>> + txavcc33-supply:
>>>>> + description: 3.3V HDMI analog frontend power
>>>>> +
>>>>> + pvcc1-supply:
>>>>> + description: 1.8V HDMI frontend core PLL power
>>>>> +
>>>>> + pvcc2-supply:
>>>>> + description: 1.8V HDMI frontend filter PLL power
>>>>> +
>>>>> + avcc-supply:
>>>>> + description: 3.3V LVDS frontend power
>>>>> +
>>>>> + anvdd-supply:
>>>>> + description: 1.8V LVDS frontend analog power
>>>>> +
>>>>> + apvdd-supply:
>>>>> + description: 1.8V LVDS frontend PLL power
>>>>> +
>>>>> + "#sound-dai-cells":
>>>>> + const: 0
>>>>> +
>>>>> + ite,lvds-link-num-data-lanes:
>>>>> + $ref: /schemas/types.yaml#/definitions/uint8
>>>>> + enum: [3, 4, 5]
>>>>> + description: number of data lanes per LVDS link
>>>>
>>>> Please use data-lanes property inside the OF graph.
>>>
>>> In both port@0 and port@1?
>>
>> Yes
>
> I'm assuming if data-mapping is defined, then no need to
> define data-lanes.
>
>>
>>>
>>>>
>>>>> +
>>>>> + ite,i2s-audio-fifo-sources:
>>>>> + $ref: /schemas/types.yaml#/definitions/uint32-array
>>>>> + minItems: 1
>>>>> + maxItems: 4
>>>>> + items:
>>>>> + enum: [0, 1, 2, 3]
>>>>> + description:
>>>>> + Each array element indicates the pin number of an I2S serial data input
>>>>> + line which is connected to an audio FIFO, from audio FIFO0 to FIFO3.
>>>>
>>>> What does that mean from the board point of view? Routed audio links for
>>>> the multichannel audio?
>>>
>>> Yes, also for single channel audio.
>>>
>>>>
>>>>> +
>>>>> + ite,rl-channel-swap-audio-sources:
>>>>> + $ref: /schemas/types.yaml#/definitions/uint32-array
>>>>> + minItems: 1
>>>>> + maxItems: 4
>>>>> + uniqueItems: true
>>>>> + items:
>>>>> + enum: [0, 1, 2, 3]
>>>>> + description:
>>>>> + Each array element indicates an audio source whose right channel and left
>>>>> + channel are swapped by this converter. For I2S, the element is the pin
>>>>> + number of an I2S serial data input line. For S/PDIF, the element is always
>>>>> + 0.
>>>>
>>>> Why?
>>>
>>> Because this converter has the capability to swap right channel
>>> and left channel and S/PDIF always uses audio source0.
>>>
>>>>
>>>>> +
>>>>> + ports:
>>>>> + $ref: /schemas/graph.yaml#/properties/ports
>>>>> +
>>>>> + properties:
>>>>> + port@0:
>>>>> + $ref: /schemas/graph.yaml#/$defs/port-base
>>>>> + unevaluatedProperties: false
>>>>> + description:
>>>>> + The first LVDS input link.
>>>>> + In dual-link LVDS mode, this link works together with the second LVDS
>>>>> + input link, and one link receives odd pixels while the other receives
>>>>> + even pixels. Specify the pixels with one of the dual-lvds-odd-pixels
>>>>> + and dual-lvds-even-pixels properties when and only when dual-link LVDS
>>>>> + mode is used.
>>>>> +
>>>>> + properties:
>>>>> + dual-lvds-odd-pixels:
>>>>> + type: boolean
>>>>> + description: the first sink port for odd pixels
>>>>> +
>>>>> + dual-lvds-even-pixels:
>>>>> + type: boolean
>>>>> + description: the first sink port for even pixels
>>>>> +
>>>>> + port@1:
>>>>> + $ref: /schemas/graph.yaml#/$defs/port-base
>>>>> + unevaluatedProperties: false
>>>>> + description: the second LVDS input link
>>>>> +
>>>>> + properties:
>>>>> + dual-lvds-even-pixels:
>>>>> + type: boolean
>>>>> + description: the second sink port for even pixels
>>>>> +
>>>>> + dual-lvds-odd-pixels:
>>>>> + type: boolean
>>>>> + description: the second sink port for odd pixels
>>>>> +
>>>>> + oneOf:
>>>>> + - required: [dual-lvds-even-pixels]
>>>>> + - required: [dual-lvds-odd-pixels]
>>>>
>>>> This still allows one to specify that both ports provide odd pixels. Is
>>>> that expected? Also why do you need two properties which specify the
>>>> same option.
>>>
>>> No, that is not expected. Description for port@0 already mentions
>>> one link receives odd pixels while the other receives even pixels.
>>
>> That's not expected, but permitted by the bindings.
>
> It is not permitted by port@1. If "dual-lvds-odd-pixels;" is added
> to port@1 in the dual-link LVDS example, the below warning will be
> generated by dt_binding_check.
>
> Documentation/devicetree/bindings/display/bridge/ite,it6263.example.dtb: hdmi@4c: ports:port@1: {'reg': [[1]], 'dual-lvds-even-pixels': True, 'dual-lvds-odd-pixels': True, 'endpoint': {'remote-endpoint': [[4294967295]]}} is valid under each of {'required': ['dual-lvds-odd-pixels']}, {'required': ['dual-lvds-even-pixels']}
> from schema $id: http://devicetree.org/schemas/display/bridge/ite,it6263.yaml#
>
> However, the binding for port@0 does allow DT writers to specify
> both even and odd pixels. I raised similar concerns in v1 discussion.
> According to Rob's comment in #devicetree IRC, the ports property
> is simplified to this form and more description for port@0 is added
> to tell when to specify the even/odd pixels. If you know any better
> way to indicate the constraints, please shout.
Dmitry, if the binding in v1 may pass dt_binding_check against
dtschema-2024.9, then it looks like all constraints are implemented.
But, it can't pass.
>
>>
>>>
>>> Two options are supported for dual-link LVDS, not the same option:
>>> 1) LVDS link1(port@0) gets odd pixels
>>> and
>>> LVDS link2(port@1) gets even pixels.
>>>
>>> 2) LVDS link1(port@0) gets even pixels
>>> and
>>> LVDS link2(port@1) gets odd pixels.
>>> That's the reason why each port needs two properties to define
>>> odd/even pixels.
>>>
>>>>
>>>> My suggestion would be to add a single root-level property which
>>>> specifies which port provides even pixel data.
>>>
>>> That won't work. The LVDS source side expects the ports of
>>> the sink side specify dual-lvds-{odd,even}-pixels properties.
>>
>> I didn't notice that these properties are already defined.
>>
>> As these properties are common between several schema files, please
>> extract them to a common schema file (like lvds.yaml).
>
> I'm not sure how to do that. Is it obvious?
> Please shed some light.
>
> Only two panel schema files are defining even/odd pixels now -
> advantech,idk-2121wr.yaml and panel-simple-lvds-dual-ports.yaml.
> Maybe, extract them later when more schema files(especially for
> bridges) try to define the same? I'd like to keep a low profile
> for now.
>
>>
>>>
>>>>
>>>>> +
>>>>> + port@2:
>>>>> + $ref: /schemas/graph.yaml#/properties/port
>>>>> + description: video port for the HDMI output
>>>>> +
>>>>> + port@3:
>>>>> + $ref: /schemas/graph.yaml#/properties/port
>>>>> + description: sound input port
>>>>> +
>>>>> + required:
>>>>> + - port@0
>>>>> + - port@2
>>>>> +
>>>>> +required:
>>>>> + - compatible
>>>>> + - reg
>>>>> + - ivdd-supply
>>>>> + - ovdd-supply
>>>>> + - txavcc18-supply
>>>>> + - txavcc33-supply
>>>>> + - pvcc1-supply
>>>>> + - pvcc2-supply
>>>>> + - avcc-supply
>>>>> + - anvdd-supply
>>>>> + - apvdd-supply
>>>>> + - ite,lvds-link-num-data-lanes
>>>>> + - ports
>>>>> +
>>>>> +additionalProperties: false
>>>>> +
>>>>> +examples:
>>>>> + - |
>>>>> + /* single-link LVDS input */
>>>>> + #include <dt-bindings/gpio/gpio.h>
>>>>> +
>>>>> + i2c {
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> +
>>>>> + hdmi@4c {
>>>>> + compatible = "ite,it6263";
>>>>> + reg = <0x4c>;
>>>>> + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
>>>>> + ivdd-supply = <®_buck5>;
>>>>> + ovdd-supply = <®_vext_3v3>;
>>>>> + txavcc18-supply = <®_buck5>;
>>>>> + txavcc33-supply = <®_vext_3v3>;
>>>>> + pvcc1-supply = <®_buck5>;
>>>>> + pvcc2-supply = <®_buck5>;
>>>>> + avcc-supply = <®_vext_3v3>;
>>>>> + anvdd-supply = <®_buck5>;
>>>>> + apvdd-supply = <®_buck5>;
>>>>> + ite,lvds-link-num-data-lanes = /bits/ 8 <4>;
>>>>> +
>>>>> + ports {
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> +
>>>>> + port@0 {
>>>>> + reg = <0>;
>>>>> +
>>>>> + it6263_lvds_link1: endpoint {
>>>>> + remote-endpoint = <&ldb_lvds_ch0>;
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + port@2 {
>>>>> + reg = <2>;
>>>>> +
>>>>> + it6263_out: endpoint {
>>>>> + remote-endpoint = <&hdmi_in>;
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + - |
>>>>> + /* dual-link LVDS input */
>>>>> + #include <dt-bindings/gpio/gpio.h>
>>>>> +
>>>>> + i2c {
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> +
>>>>> + hdmi@4c {
>>>>> + compatible = "ite,it6263";
>>>>> + reg = <0x4c>;
>>>>> + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
>>>>> + ivdd-supply = <®_buck5>;
>>>>> + ovdd-supply = <®_vext_3v3>;
>>>>> + txavcc18-supply = <®_buck5>;
>>>>> + txavcc33-supply = <®_vext_3v3>;
>>>>> + pvcc1-supply = <®_buck5>;
>>>>> + pvcc2-supply = <®_buck5>;
>>>>> + avcc-supply = <®_vext_3v3>;
>>>>> + anvdd-supply = <®_buck5>;
>>>>> + apvdd-supply = <®_buck5>;
>>>>> + ite,lvds-link-num-data-lanes = /bits/ 8 <4>;
>>>>> +
>>>>> + ports {
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> +
>>>>> + port@0 {
>>>>> + reg = <0>;
>>>>> + dual-lvds-odd-pixels;
>>>>> +
>>>>> + it6263_lvds_link1_dual: endpoint {
>>>>> + remote-endpoint = <&ldb_lvds_ch0>;
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + port@1 {
>>>>> + reg = <1>;
>>>>> + dual-lvds-even-pixels;
>>>>> +
>>>>> + it6263_lvds_link2_dual: endpoint {
>>>>> + remote-endpoint = <&ldb_lvds_ch1>;
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + port@2 {
>>>>> + reg = <2>;
>>>>> +
>>>>> + it6263_out_dual: endpoint {
>>>>> + remote-endpoint = <&hdmi_in>;
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> --
>>>>> 2.34.1
>>>>>
>>>>
>>>
>>> --
>>> Regards,
>>> Liu Ying
>>>
>>
>
--
Regards,
Liu Ying
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-14 5:33 ` Liu Ying
2024-10-14 5:54 ` Liu Ying
@ 2024-10-14 7:07 ` Dmitry Baryshkov
2024-10-14 10:01 ` Liu Ying
2024-10-15 6:28 ` Liu Ying
2024-10-14 7:39 ` Biju Das
2024-10-14 8:30 ` Biju Das
3 siblings, 2 replies; 49+ messages in thread
From: Dmitry Baryshkov @ 2024-10-14 7:07 UTC (permalink / raw)
To: Liu Ying
Cc: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel,
andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
arnd, nfraprado, o.rempel, y.moog, marex, isaac.scott,
biju.das.jz
On Mon, Oct 14, 2024 at 01:33:44PM +0800, Liu Ying wrote:
> On 10/14/2024, Dmitry Baryshkov wrote:
> > On Sat, Oct 12, 2024 at 05:14:13PM +0800, Liu Ying wrote:
> >> On 10/12/2024, Dmitry Baryshkov wrote:
> >>> On Sat, Oct 12, 2024 at 03:35:39PM +0800, Liu Ying wrote:
> >>>> Document ITE IT6263 LVDS to HDMI converter.
> >>>>
> >>>> Product link:
> >>>> https://www.ite.com.tw/en/product/cate1/IT6263
> >>>>
> >>>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> >>>> ---
> >>>> v2:
> >>>> * Document number of LVDS link data lanes. (Biju)
> >>>> * Simplify ports property by dropping "oneOf". (Rob)
> >>>>
> >>>> .../bindings/display/bridge/ite,it6263.yaml | 276 ++++++++++++++++++
> >>>> 1 file changed, 276 insertions(+)
> >>>> create mode 100644 Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
> >>>>
> >>>> diff --git a/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
> >>>> new file mode 100644
> >>>> index 000000000000..bc2bbec07623
> >>>> --- /dev/null
> >>>> +++ b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
> >>>> @@ -0,0 +1,276 @@
> >>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >>>> +%YAML 1.2
> >>>> +---
> >>>> +$id: http://devicetree.org/schemas/display/bridge/ite,it6263.yaml#
> >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>>> +
> >>>> +title: ITE IT6263 LVDS to HDMI converter
> >>>> +
> >>>> +maintainers:
> >>>> + - Liu Ying <victor.liu@nxp.com>
> >>>> +
> >>>> +description: |
> >>>> + The IT6263 is a high-performance single-chip De-SSC(De-Spread Spectrum) LVDS
> >>>> + to HDMI converter. Combined with LVDS receiver and HDMI 1.4a transmitter,
> >>>> + the IT6263 supports LVDS input and HDMI 1.4 output by conversion function.
> >>>> + The built-in LVDS receiver can support single-link and dual-link LVDS inputs,
> >>>> + and the built-in HDMI transmitter is fully compliant with HDMI 1.4a/3D, HDCP
> >>>> + 1.2 and backward compatible with DVI 1.0 specification.
> >>>> +
> >>>> + The IT6263 also encodes and transmits up to 8 channels of I2S digital audio,
> >>>> + with sampling rate up to 192KHz and sample size up to 24 bits. In addition,
> >>>> + an S/PDIF input port takes in compressed audio of up to 192KHz frame rate.
> >>>> +
> >>>> + The newly supported High-Bit Rate(HBR) audio by HDMI specifications v1.3 is
> >>>> + provided by the IT6263 in two interfaces: the four I2S input ports or the
> >>>> + S/PDIF input port. With both interfaces the highest possible HBR frame rate
> >>>> + is supported at up to 768KHz.
> >>>> +
> >>>> +properties:
> >>>
> >>> No LVDS data-mapping support?
> >>
> >> It is enough to document number of LVDS link data lanes
> >> because OS should be able to determine the data-mapping
> >> by looking at the number and the data-mapping capability
> >> of the other side of the LVDS link.
> >
> > From what I can see, data-mapping is specified on the consumer sink side
> > of the LVDS link. This means it should go to the bridge's device node.
>
> Then, I won't define data-lanes, because data-mapping implies it,
> e.g., jeida-24 implies data lanes 0/1/2/3, see lvds-data-mapping.yaml.
>
> Please let me know which one you prefer.
I'd prefer data-mapping.
>
> >
> >>
> >>>
> >>>> + compatible:
> >>>> + const: ite,it6263
> >>>> +
> >>>> + reg:
> >>>> + maxItems: 1
> >>>> +
> >>>> + clocks:
> >>>> + maxItems: 1
> >>>> + description: audio master clock
> >>>> +
> >>>> + clock-names:
> >>>> + const: mclk
> >>>> +
> >>>> + reset-gpios:
> >>>> + maxItems: 1
> >>>> +
> >>>> + ivdd-supply:
> >>>> + description: 1.8V digital logic power
> >>>> +
> >>>> + ovdd-supply:
> >>>> + description: 3.3V I/O pin power
> >>>> +
> >>>> + txavcc18-supply:
> >>>> + description: 1.8V HDMI analog frontend power
> >>>> +
> >>>> + txavcc33-supply:
> >>>> + description: 3.3V HDMI analog frontend power
> >>>> +
> >>>> + pvcc1-supply:
> >>>> + description: 1.8V HDMI frontend core PLL power
> >>>> +
> >>>> + pvcc2-supply:
> >>>> + description: 1.8V HDMI frontend filter PLL power
> >>>> +
> >>>> + avcc-supply:
> >>>> + description: 3.3V LVDS frontend power
> >>>> +
> >>>> + anvdd-supply:
> >>>> + description: 1.8V LVDS frontend analog power
> >>>> +
> >>>> + apvdd-supply:
> >>>> + description: 1.8V LVDS frontend PLL power
> >>>> +
> >>>> + "#sound-dai-cells":
> >>>> + const: 0
> >>>> +
> >>>> + ite,lvds-link-num-data-lanes:
> >>>> + $ref: /schemas/types.yaml#/definitions/uint8
> >>>> + enum: [3, 4, 5]
> >>>> + description: number of data lanes per LVDS link
> >>>
> >>> Please use data-lanes property inside the OF graph.
> >>
> >> In both port@0 and port@1?
> >
> > Yes
>
> I'm assuming if data-mapping is defined, then no need to
> define data-lanes.
Yes
>
> >
> >>
> >>>
> >>>> +
> >>>> + ite,i2s-audio-fifo-sources:
> >>>> + $ref: /schemas/types.yaml#/definitions/uint32-array
> >>>> + minItems: 1
> >>>> + maxItems: 4
> >>>> + items:
> >>>> + enum: [0, 1, 2, 3]
> >>>> + description:
> >>>> + Each array element indicates the pin number of an I2S serial data input
> >>>> + line which is connected to an audio FIFO, from audio FIFO0 to FIFO3.
> >>>
> >>> What does that mean from the board point of view? Routed audio links for
> >>> the multichannel audio?
> >>
> >> Yes, also for single channel audio.
> >>
> >>>
> >>>> +
> >>>> + ite,rl-channel-swap-audio-sources:
> >>>> + $ref: /schemas/types.yaml#/definitions/uint32-array
> >>>> + minItems: 1
> >>>> + maxItems: 4
> >>>> + uniqueItems: true
> >>>> + items:
> >>>> + enum: [0, 1, 2, 3]
> >>>> + description:
> >>>> + Each array element indicates an audio source whose right channel and left
> >>>> + channel are swapped by this converter. For I2S, the element is the pin
> >>>> + number of an I2S serial data input line. For S/PDIF, the element is always
> >>>> + 0.
> >>>
> >>> Why?
> >>
> >> Because this converter has the capability to swap right channel
> >> and left channel and S/PDIF always uses audio source0.
> >>
> >>>
> >>>> +
> >>>> + ports:
> >>>> + $ref: /schemas/graph.yaml#/properties/ports
> >>>> +
> >>>> + properties:
> >>>> + port@0:
> >>>> + $ref: /schemas/graph.yaml#/$defs/port-base
> >>>> + unevaluatedProperties: false
> >>>> + description:
> >>>> + The first LVDS input link.
> >>>> + In dual-link LVDS mode, this link works together with the second LVDS
> >>>> + input link, and one link receives odd pixels while the other receives
> >>>> + even pixels. Specify the pixels with one of the dual-lvds-odd-pixels
> >>>> + and dual-lvds-even-pixels properties when and only when dual-link LVDS
> >>>> + mode is used.
> >>>> +
> >>>> + properties:
> >>>> + dual-lvds-odd-pixels:
> >>>> + type: boolean
> >>>> + description: the first sink port for odd pixels
> >>>> +
> >>>> + dual-lvds-even-pixels:
> >>>> + type: boolean
> >>>> + description: the first sink port for even pixels
> >>>> +
> >>>> + port@1:
> >>>> + $ref: /schemas/graph.yaml#/$defs/port-base
> >>>> + unevaluatedProperties: false
> >>>> + description: the second LVDS input link
> >>>> +
> >>>> + properties:
> >>>> + dual-lvds-even-pixels:
> >>>> + type: boolean
> >>>> + description: the second sink port for even pixels
> >>>> +
> >>>> + dual-lvds-odd-pixels:
> >>>> + type: boolean
> >>>> + description: the second sink port for odd pixels
> >>>> +
> >>>> + oneOf:
> >>>> + - required: [dual-lvds-even-pixels]
> >>>> + - required: [dual-lvds-odd-pixels]
> >>>
> >>> This still allows one to specify that both ports provide odd pixels. Is
> >>> that expected? Also why do you need two properties which specify the
> >>> same option.
> >>
> >> No, that is not expected. Description for port@0 already mentions
> >> one link receives odd pixels while the other receives even pixels.
> >
> > That's not expected, but permitted by the bindings.
>
> It is not permitted by port@1. If "dual-lvds-odd-pixels;" is added
> to port@1 in the dual-link LVDS example, the below warning will be
> generated by dt_binding_check.
It is permitted for both ports to have the same value (e.g. mark both
ports as odd or even).
>
> Documentation/devicetree/bindings/display/bridge/ite,it6263.example.dtb: hdmi@4c: ports:port@1: {'reg': [[1]], 'dual-lvds-even-pixels': True, 'dual-lvds-odd-pixels': True, 'endpoint': {'remote-endpoint': [[4294967295]]}} is valid under each of {'required': ['dual-lvds-odd-pixels']}, {'required': ['dual-lvds-even-pixels']}
> from schema $id: http://devicetree.org/schemas/display/bridge/ite,it6263.yaml#
>
> However, the binding for port@0 does allow DT writers to specify
> both even and odd pixels. I raised similar concerns in v1 discussion.
> According to Rob's comment in #devicetree IRC, the ports property
> is simplified to this form and more description for port@0 is added
> to tell when to specify the even/odd pixels. If you know any better
> way to indicate the constraints, please shout.
I don't think we can express that in schema. I don't like the bindings
(and would have preferred a single property instead), but as the
bindings are already defined, let's use them.
>
> >
> >>
> >> Two options are supported for dual-link LVDS, not the same option:
> >> 1) LVDS link1(port@0) gets odd pixels
> >> and
> >> LVDS link2(port@1) gets even pixels.
> >>
> >> 2) LVDS link1(port@0) gets even pixels
> >> and
> >> LVDS link2(port@1) gets odd pixels.
> >> That's the reason why each port needs two properties to define
> >> odd/even pixels.
> >>
> >>>
> >>> My suggestion would be to add a single root-level property which
> >>> specifies which port provides even pixel data.
> >>
> >> That won't work. The LVDS source side expects the ports of
> >> the sink side specify dual-lvds-{odd,even}-pixels properties.
> >
> > I didn't notice that these properties are already defined.
> >
> > As these properties are common between several schema files, please
> > extract them to a common schema file (like lvds.yaml).
>
> I'm not sure how to do that. Is it obvious?
> Please shed some light.
>
> Only two panel schema files are defining even/odd pixels now -
> advantech,idk-2121wr.yaml and panel-simple-lvds-dual-ports.yaml.
> Maybe, extract them later when more schema files(especially for
> bridges) try to define the same? I'd like to keep a low profile
> for now.
I'd say, please extract those now. Adding third is more than enough and
should be avoided. Extracting is pretty simple. One patch to move the
definition and descriptions from panel-simple-lvds-dual-ports to a
common location (e.g. lvds-dual-ports.yaml). Leave the required
constrains in place. Second patch is to add oneOf constraints to the
ports. port@0 might get the same oneOf + the
dual-lvds-{odd,even}-pixels:false case, allowing a single-port
definition.
>
> >
> >>
> >>>
> >>>> +
> >>>> + port@2:
> >>>> + $ref: /schemas/graph.yaml#/properties/port
> >>>> + description: video port for the HDMI output
> >>>> +
> >>>> + port@3:
> >>>> + $ref: /schemas/graph.yaml#/properties/port
> >>>> + description: sound input port
> >>>> +
> >>>> + required:
> >>>> + - port@0
> >>>> + - port@2
> >>>> +
> >>>> +required:
> >>>> + - compatible
> >>>> + - reg
> >>>> + - ivdd-supply
> >>>> + - ovdd-supply
> >>>> + - txavcc18-supply
> >>>> + - txavcc33-supply
> >>>> + - pvcc1-supply
> >>>> + - pvcc2-supply
> >>>> + - avcc-supply
> >>>> + - anvdd-supply
> >>>> + - apvdd-supply
> >>>> + - ite,lvds-link-num-data-lanes
> >>>> + - ports
> >>>> +
> >>>> +additionalProperties: false
> >>>> +
> >>>> +examples:
> >>>> + - |
> >>>> + /* single-link LVDS input */
> >>>> + #include <dt-bindings/gpio/gpio.h>
> >>>> +
> >>>> + i2c {
> >>>> + #address-cells = <1>;
> >>>> + #size-cells = <0>;
> >>>> +
> >>>> + hdmi@4c {
> >>>> + compatible = "ite,it6263";
> >>>> + reg = <0x4c>;
> >>>> + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
> >>>> + ivdd-supply = <®_buck5>;
> >>>> + ovdd-supply = <®_vext_3v3>;
> >>>> + txavcc18-supply = <®_buck5>;
> >>>> + txavcc33-supply = <®_vext_3v3>;
> >>>> + pvcc1-supply = <®_buck5>;
> >>>> + pvcc2-supply = <®_buck5>;
> >>>> + avcc-supply = <®_vext_3v3>;
> >>>> + anvdd-supply = <®_buck5>;
> >>>> + apvdd-supply = <®_buck5>;
> >>>> + ite,lvds-link-num-data-lanes = /bits/ 8 <4>;
> >>>> +
> >>>> + ports {
> >>>> + #address-cells = <1>;
> >>>> + #size-cells = <0>;
> >>>> +
> >>>> + port@0 {
> >>>> + reg = <0>;
> >>>> +
> >>>> + it6263_lvds_link1: endpoint {
> >>>> + remote-endpoint = <&ldb_lvds_ch0>;
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + port@2 {
> >>>> + reg = <2>;
> >>>> +
> >>>> + it6263_out: endpoint {
> >>>> + remote-endpoint = <&hdmi_in>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + - |
> >>>> + /* dual-link LVDS input */
> >>>> + #include <dt-bindings/gpio/gpio.h>
> >>>> +
> >>>> + i2c {
> >>>> + #address-cells = <1>;
> >>>> + #size-cells = <0>;
> >>>> +
> >>>> + hdmi@4c {
> >>>> + compatible = "ite,it6263";
> >>>> + reg = <0x4c>;
> >>>> + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
> >>>> + ivdd-supply = <®_buck5>;
> >>>> + ovdd-supply = <®_vext_3v3>;
> >>>> + txavcc18-supply = <®_buck5>;
> >>>> + txavcc33-supply = <®_vext_3v3>;
> >>>> + pvcc1-supply = <®_buck5>;
> >>>> + pvcc2-supply = <®_buck5>;
> >>>> + avcc-supply = <®_vext_3v3>;
> >>>> + anvdd-supply = <®_buck5>;
> >>>> + apvdd-supply = <®_buck5>;
> >>>> + ite,lvds-link-num-data-lanes = /bits/ 8 <4>;
> >>>> +
> >>>> + ports {
> >>>> + #address-cells = <1>;
> >>>> + #size-cells = <0>;
> >>>> +
> >>>> + port@0 {
> >>>> + reg = <0>;
> >>>> + dual-lvds-odd-pixels;
> >>>> +
> >>>> + it6263_lvds_link1_dual: endpoint {
> >>>> + remote-endpoint = <&ldb_lvds_ch0>;
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + port@1 {
> >>>> + reg = <1>;
> >>>> + dual-lvds-even-pixels;
> >>>> +
> >>>> + it6263_lvds_link2_dual: endpoint {
> >>>> + remote-endpoint = <&ldb_lvds_ch1>;
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + port@2 {
> >>>> + reg = <2>;
> >>>> +
> >>>> + it6263_out_dual: endpoint {
> >>>> + remote-endpoint = <&hdmi_in>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> --
> >>>> 2.34.1
> >>>>
> >>>
> >>
> >> --
> >> Regards,
> >> Liu Ying
> >>
> >
>
> --
> Regards,
> Liu Ying
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-12 7:35 ` [PATCH v2 6/9] drm/bridge: " Liu Ying
2024-10-12 8:45 ` Dmitry Baryshkov
@ 2024-10-14 7:10 ` Dmitry Baryshkov
2024-10-14 7:18 ` Liu Ying
2024-10-15 4:54 ` kernel test robot
2 siblings, 1 reply; 49+ messages in thread
From: Dmitry Baryshkov @ 2024-10-14 7:10 UTC (permalink / raw)
To: Liu Ying
Cc: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel,
andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
arnd, nfraprado, o.rempel, y.moog, marex, isaac.scott,
biju.das.jz
On Sat, Oct 12, 2024 at 03:35:40PM +0800, Liu Ying wrote:
> Add basic HDMI video output support. Currently, only RGB888 output
> pixel format is supported. At the LVDS input side, the driver
> supports single LVDS link and dual LVDS links with "jeida-24" LVDS
> mapping.
>
> Product link:
> https://www.ite.com.tw/en/product/cate1/IT6263
>
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> ---
> v2:
> * Add AVI inforframe support. (Maxime)
> * Add DRM_MODE_CONNECTOR_HDMIA. (Biju)
> * Rename it6263_reset() to it6263_hw_reset(). (Biju)
> * Check number of LVDS link data lanes. (Biju)
>
> drivers/gpu/drm/bridge/Kconfig | 8 +
> drivers/gpu/drm/bridge/Makefile | 1 +
> drivers/gpu/drm/bridge/ite-it6263.c | 919 ++++++++++++++++++++++++++++
> 3 files changed, 928 insertions(+)
> create mode 100644 drivers/gpu/drm/bridge/ite-it6263.c
>
[...]
> +static int it6263_parse_dt(struct it6263 *it)
> +{
> + struct device *dev = it->dev;
> + struct device_node *port0, *port1;
> + int ret;
> +
> + ret = of_property_read_u8(dev->of_node, "ite,lvds-link-num-data-lanes",
> + &it->lvds_link_num_dlanes);
> + if (ret) {
> + dev_err(dev, "failed to get LVDS link number of data lanes: %d\n",
> + ret);
> + return ret;
> + }
> +
> + it->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0);
> + if (IS_ERR(it->next_bridge))
> + return dev_err_probe(dev, PTR_ERR(it->next_bridge),
> + "failed to get next bridge\n");
> +
> + port0 = of_graph_get_port_by_id(dev->of_node, 0);
> + port1 = of_graph_get_port_by_id(dev->of_node, 1);
> + if (port0 && port1) {
> + if (of_property_read_bool(port0, "dual-lvds-even-pixels") &&
> + of_property_read_bool(port1, "dual-lvds-odd-pixels")) {
> + it->lvds_dual_link = true;
> + it->lvds_link12_swap = true;
> + } else if (of_property_read_bool(port0, "dual-lvds-odd-pixels") &&
> + of_property_read_bool(port1, "dual-lvds-even-pixels")) {
> + it->lvds_dual_link = true;
> + }
> +
> + if (!it->lvds_dual_link) {
> + dev_err(dev,
> + "failed to get LVDS dual link pixel order\n");
> + ret = -EINVAL;
> + }
Please use drm_of_lvds_get_dual_link_pixel_order(), it validates that
the DT definition is sound: one port for odd pixels, one port for even
pixels.
> + } else if (port1) {
> + ret = -EINVAL;
> + dev_err(dev, "single input LVDS port1 is not supported\n");
> + } else if (!port0) {
> + ret = -EINVAL;
> + dev_err(dev, "no input LVDS port\n");
> + }
> +
> + of_node_put(port0);
> + of_node_put(port1);
> +
> + return ret;
> +}
> +
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-14 7:10 ` Dmitry Baryshkov
@ 2024-10-14 7:18 ` Liu Ying
2024-10-14 7:32 ` Dmitry Baryshkov
2024-10-14 8:14 ` Biju Das
0 siblings, 2 replies; 49+ messages in thread
From: Liu Ying @ 2024-10-14 7:18 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel,
andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
arnd, nfraprado, o.rempel, y.moog, marex, isaac.scott,
biju.das.jz
On 10/14/2024, Dmitry Baryshkov wrote:
> On Sat, Oct 12, 2024 at 03:35:40PM +0800, Liu Ying wrote:
>> Add basic HDMI video output support. Currently, only RGB888 output
>> pixel format is supported. At the LVDS input side, the driver
>> supports single LVDS link and dual LVDS links with "jeida-24" LVDS
>> mapping.
>>
>> Product link:
>> https://www.ite.com.tw/en/product/cate1/IT6263
>>
>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
>> ---
>> v2:
>> * Add AVI inforframe support. (Maxime)
>> * Add DRM_MODE_CONNECTOR_HDMIA. (Biju)
>> * Rename it6263_reset() to it6263_hw_reset(). (Biju)
>> * Check number of LVDS link data lanes. (Biju)
>>
>> drivers/gpu/drm/bridge/Kconfig | 8 +
>> drivers/gpu/drm/bridge/Makefile | 1 +
>> drivers/gpu/drm/bridge/ite-it6263.c | 919 ++++++++++++++++++++++++++++
>> 3 files changed, 928 insertions(+)
>> create mode 100644 drivers/gpu/drm/bridge/ite-it6263.c
>>
>
> [...]
>
>> +static int it6263_parse_dt(struct it6263 *it)
>> +{
>> + struct device *dev = it->dev;
>> + struct device_node *port0, *port1;
>> + int ret;
>> +
>> + ret = of_property_read_u8(dev->of_node, "ite,lvds-link-num-data-lanes",
>> + &it->lvds_link_num_dlanes);
>> + if (ret) {
>> + dev_err(dev, "failed to get LVDS link number of data lanes: %d\n",
>> + ret);
>> + return ret;
>> + }
>> +
>> + it->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0);
>> + if (IS_ERR(it->next_bridge))
>> + return dev_err_probe(dev, PTR_ERR(it->next_bridge),
>> + "failed to get next bridge\n");
>> +
>> + port0 = of_graph_get_port_by_id(dev->of_node, 0);
>> + port1 = of_graph_get_port_by_id(dev->of_node, 1);
>> + if (port0 && port1) {
>> + if (of_property_read_bool(port0, "dual-lvds-even-pixels") &&
>> + of_property_read_bool(port1, "dual-lvds-odd-pixels")) {
>> + it->lvds_dual_link = true;
>> + it->lvds_link12_swap = true;
>> + } else if (of_property_read_bool(port0, "dual-lvds-odd-pixels") &&
>> + of_property_read_bool(port1, "dual-lvds-even-pixels")) {
>> + it->lvds_dual_link = true;
>> + }
>> +
>> + if (!it->lvds_dual_link) {
>> + dev_err(dev,
>> + "failed to get LVDS dual link pixel order\n");
>> + ret = -EINVAL;
>> + }
>
> Please use drm_of_lvds_get_dual_link_pixel_order(), it validates that
> the DT definition is sound: one port for odd pixels, one port for even
> pixels.
It cannot be used, because it get the pixel order for the LVDS
source not sink. IT6263 is the LVDS sink.
* drm_of_lvds_get_dual_link_pixel_order - Get LVDS dual-link pixel order
* @port1: First DT port node of the Dual-link LVDS source
* @port2: Second DT port node of the Dual-link LVDS source
>
>> + } else if (port1) {
>> + ret = -EINVAL;
>> + dev_err(dev, "single input LVDS port1 is not supported\n");
>> + } else if (!port0) {
>> + ret = -EINVAL;
>> + dev_err(dev, "no input LVDS port\n");
>> + }
>> +
>> + of_node_put(port0);
>> + of_node_put(port1);
>> +
>> + return ret;
>> +}
>> +
>
--
Regards,
Liu Ying
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-14 7:18 ` Liu Ying
@ 2024-10-14 7:32 ` Dmitry Baryshkov
2024-10-14 8:28 ` Liu Ying
2024-10-14 8:14 ` Biju Das
1 sibling, 1 reply; 49+ messages in thread
From: Dmitry Baryshkov @ 2024-10-14 7:32 UTC (permalink / raw)
To: Liu Ying
Cc: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel,
andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
arnd, nfraprado, o.rempel, y.moog, marex, isaac.scott,
biju.das.jz
On Mon, Oct 14, 2024 at 03:18:15PM +0800, Liu Ying wrote:
> On 10/14/2024, Dmitry Baryshkov wrote:
> > On Sat, Oct 12, 2024 at 03:35:40PM +0800, Liu Ying wrote:
> >> Add basic HDMI video output support. Currently, only RGB888 output
> >> pixel format is supported. At the LVDS input side, the driver
> >> supports single LVDS link and dual LVDS links with "jeida-24" LVDS
> >> mapping.
> >>
> >> Product link:
> >> https://www.ite.com.tw/en/product/cate1/IT6263
> >>
> >> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> >> ---
> >> v2:
> >> * Add AVI inforframe support. (Maxime)
> >> * Add DRM_MODE_CONNECTOR_HDMIA. (Biju)
> >> * Rename it6263_reset() to it6263_hw_reset(). (Biju)
> >> * Check number of LVDS link data lanes. (Biju)
> >>
> >> drivers/gpu/drm/bridge/Kconfig | 8 +
> >> drivers/gpu/drm/bridge/Makefile | 1 +
> >> drivers/gpu/drm/bridge/ite-it6263.c | 919 ++++++++++++++++++++++++++++
> >> 3 files changed, 928 insertions(+)
> >> create mode 100644 drivers/gpu/drm/bridge/ite-it6263.c
> >>
> >
> > [...]
> >
> >> +static int it6263_parse_dt(struct it6263 *it)
> >> +{
> >> + struct device *dev = it->dev;
> >> + struct device_node *port0, *port1;
> >> + int ret;
> >> +
> >> + ret = of_property_read_u8(dev->of_node, "ite,lvds-link-num-data-lanes",
> >> + &it->lvds_link_num_dlanes);
> >> + if (ret) {
> >> + dev_err(dev, "failed to get LVDS link number of data lanes: %d\n",
> >> + ret);
> >> + return ret;
> >> + }
> >> +
> >> + it->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0);
> >> + if (IS_ERR(it->next_bridge))
> >> + return dev_err_probe(dev, PTR_ERR(it->next_bridge),
> >> + "failed to get next bridge\n");
> >> +
> >> + port0 = of_graph_get_port_by_id(dev->of_node, 0);
> >> + port1 = of_graph_get_port_by_id(dev->of_node, 1);
> >> + if (port0 && port1) {
> >> + if (of_property_read_bool(port0, "dual-lvds-even-pixels") &&
> >> + of_property_read_bool(port1, "dual-lvds-odd-pixels")) {
> >> + it->lvds_dual_link = true;
> >> + it->lvds_link12_swap = true;
> >> + } else if (of_property_read_bool(port0, "dual-lvds-odd-pixels") &&
> >> + of_property_read_bool(port1, "dual-lvds-even-pixels")) {
> >> + it->lvds_dual_link = true;
> >> + }
> >> +
> >> + if (!it->lvds_dual_link) {
> >> + dev_err(dev,
> >> + "failed to get LVDS dual link pixel order\n");
> >> + ret = -EINVAL;
> >> + }
> >
> > Please use drm_of_lvds_get_dual_link_pixel_order(), it validates that
> > the DT definition is sound: one port for odd pixels, one port for even
> > pixels.
>
> It cannot be used, because it get the pixel order for the LVDS
> source not sink. IT6263 is the LVDS sink.
Then you need a similar function for the sink side. Add it to the
drm_of.c
>
> * drm_of_lvds_get_dual_link_pixel_order - Get LVDS dual-link pixel order
> * @port1: First DT port node of the Dual-link LVDS source
> * @port2: Second DT port node of the Dual-link LVDS source
>
> >
> >> + } else if (port1) {
> >> + ret = -EINVAL;
> >> + dev_err(dev, "single input LVDS port1 is not supported\n");
> >> + } else if (!port0) {
> >> + ret = -EINVAL;
> >> + dev_err(dev, "no input LVDS port\n");
> >> + }
> >> +
> >> + of_node_put(port0);
> >> + of_node_put(port1);
> >> +
> >> + return ret;
> >> +}
> >> +
> >
>
> --
> Regards,
> Liu Ying
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 49+ messages in thread
* RE: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-14 5:33 ` Liu Ying
2024-10-14 5:54 ` Liu Ying
2024-10-14 7:07 ` Dmitry Baryshkov
@ 2024-10-14 7:39 ` Biju Das
2024-10-14 7:58 ` Biju Das
2024-10-14 8:04 ` Dmitry Baryshkov
2024-10-14 8:30 ` Biju Das
3 siblings, 2 replies; 49+ messages in thread
From: Biju Das @ 2024-10-14 7:39 UTC (permalink / raw)
To: Liu Ying, Dmitry Baryshkov
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org, andrzej.hajda@intel.com,
neil.armstrong@linaro.org, rfoss@kernel.org, laurent.pinchart,
jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com,
simona@ffwll.ch, maarten.lankhorst@linux.intel.com,
mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com,
catalin.marinas@arm.com, will@kernel.org,
quic_bjorande@quicinc.com, geert+renesas@glider.be, arnd@arndb.de,
nfraprado@collabora.com, o.rempel@pengutronix.de,
y.moog@phytec.de, marex@denx.de, isaac.scott@ideasonboard.com
Hi Liu and Dmitry,
> -----Original Message-----
> From: Liu Ying <victor.liu@nxp.com>
> Sent: Monday, October 14, 2024 6:34 AM
> Subject: Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
>
> On 10/14/2024, Dmitry Baryshkov wrote:
> > On Sat, Oct 12, 2024 at 05:14:13PM +0800, Liu Ying wrote:
> >> On 10/12/2024, Dmitry Baryshkov wrote:
> >>> On Sat, Oct 12, 2024 at 03:35:39PM +0800, Liu Ying wrote:
> >>>> Document ITE IT6263 LVDS to HDMI converter.
> >>>>
> >>>> Product link:
> >>>> https://www.ite.com.tw/en/product/cate1/IT6263
> >>>>
> >>>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> >>>> ---
> >>>> v2:
> >>>> * Document number of LVDS link data lanes. (Biju)
> >>>> * Simplify ports property by dropping "oneOf". (Rob)
> >>>>
> >>>> .../bindings/display/bridge/ite,it6263.yaml | 276 ++++++++++++++++++
> >>>> 1 file changed, 276 insertions(+)
> >>>> create mode 100644
> >>>> Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
> >>>>
> >>>> diff --git
> >>>> a/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
> >>>> b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
> >>>> new file mode 100644
> >>>> index 000000000000..bc2bbec07623
> >>>> --- /dev/null
> >>>> +++ b/Documentation/devicetree/bindings/display/bridge/ite,it6263.y
> >>>> +++ aml
> >>>> @@ -0,0 +1,276 @@
> >>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> >>>> +1.2
> >>>> +---
> >>>> +$id: http://devicetree.org/schemas/display/bridge/ite,it6263.yaml#
> >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>>> +
> >>>> +title: ITE IT6263 LVDS to HDMI converter
> >>>> +
> >>>> +maintainers:
> >>>> + - Liu Ying <victor.liu@nxp.com>
> >>>> +
> >>>> +description: |
> >>>> + The IT6263 is a high-performance single-chip De-SSC(De-Spread
> >>>> +Spectrum) LVDS
> >>>> + to HDMI converter. Combined with LVDS receiver and HDMI 1.4a
> >>>> +transmitter,
> >>>> + the IT6263 supports LVDS input and HDMI 1.4 output by conversion function.
> >>>> + The built-in LVDS receiver can support single-link and dual-link
> >>>> +LVDS inputs,
> >>>> + and the built-in HDMI transmitter is fully compliant with HDMI
> >>>> +1.4a/3D, HDCP
> >>>> + 1.2 and backward compatible with DVI 1.0 specification.
> >>>> +
> >>>> + The IT6263 also encodes and transmits up to 8 channels of I2S
> >>>> + digital audio, with sampling rate up to 192KHz and sample size
> >>>> + up to 24 bits. In addition, an S/PDIF input port takes in compressed audio of up to 192KHz
> frame rate.
> >>>> +
> >>>> + The newly supported High-Bit Rate(HBR) audio by HDMI
> >>>> + specifications v1.3 is provided by the IT6263 in two interfaces:
> >>>> + the four I2S input ports or the S/PDIF input port. With both
> >>>> + interfaces the highest possible HBR frame rate is supported at up to 768KHz.
> >>>> +
> >>>> +properties:
> >>>
> >>> No LVDS data-mapping support?
> >>
> >> It is enough to document number of LVDS link data lanes because OS
> >> should be able to determine the data-mapping by looking at the number
> >> and the data-mapping capability of the other side of the LVDS link.
> >
> > From what I can see, data-mapping is specified on the consumer sink
> > side of the LVDS link. This means it should go to the bridge's device node.
>
> Then, I won't define data-lanes, because data-mapping implies it, e.g., jeida-24 implies data lanes
> 0/1/2/3, see lvds-data-mapping.yaml.
>
> Please let me know which one you prefer.
Assume a top level use case where a user changes the format from JEDAI to VESA using On screen
display or modetest(if some one adds support for lvds-mapping) then setting of the lvds data mapping
should be dynamic.
Maybe for initial version hardcode with JEDAI or VESA as default and provide a way to override
the host driver and bridge with requested lvds-data mapping dynamically later??
Cheers,
Biju
^ permalink raw reply [flat|nested] 49+ messages in thread
* RE: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-14 7:39 ` Biju Das
@ 2024-10-14 7:58 ` Biju Das
2024-10-14 8:04 ` Dmitry Baryshkov
1 sibling, 0 replies; 49+ messages in thread
From: Biju Das @ 2024-10-14 7:58 UTC (permalink / raw)
To: Liu Ying, Dmitry Baryshkov
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org, andrzej.hajda@intel.com,
neil.armstrong@linaro.org, rfoss@kernel.org, laurent.pinchart,
jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com,
simona@ffwll.ch, maarten.lankhorst@linux.intel.com,
mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com,
catalin.marinas@arm.com, will@kernel.org,
quic_bjorande@quicinc.com, geert+renesas@glider.be, arnd@arndb.de,
nfraprado@collabora.com, o.rempel@pengutronix.de,
y.moog@phytec.de, marex@denx.de, isaac.scott@ideasonboard.com
> -----Original Message-----
> From: Biju Das
> Sent: Monday, October 14, 2024 8:39 AM
> To: Liu Ying <victor.liu@nxp.com>; Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Cc: dri-devel@lists.freedesktop.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> imx@lists.linux.dev; linux-arm-kernel@lists.infradead.org; andrzej.hajda@intel.com;
> neil.armstrong@linaro.org; rfoss@kernel.org; laurent.pinchart <laurent.pinchart@ideasonboard.com>;
> jonas@kwiboo.se; jernej.skrabec@gmail.com; airlied@gmail.com; simona@ffwll.ch;
> maarten.lankhorst@linux.intel.com; mripard@kernel.org; tzimmermann@suse.de; robh@kernel.org;
> krzk+dt@kernel.org; conor+dt@kernel.org; shawnguo@kernel.org; s.hauer@pengutronix.de;
> kernel@pengutronix.de; festevam@gmail.com; catalin.marinas@arm.com; will@kernel.org;
> quic_bjorande@quicinc.com; geert+renesas@glider.be; arnd@arndb.de; nfraprado@collabora.com;
> o.rempel@pengutronix.de; y.moog@phytec.de; marex@denx.de; isaac.scott@ideasonboard.com
> Subject: RE: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
>
> Hi Liu and Dmitry,
>
> > -----Original Message-----
> > From: Liu Ying <victor.liu@nxp.com>
> > Sent: Monday, October 14, 2024 6:34 AM
> > Subject: Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE
> > IT6263 LVDS to HDMI converter
> >
> > On 10/14/2024, Dmitry Baryshkov wrote:
> > > On Sat, Oct 12, 2024 at 05:14:13PM +0800, Liu Ying wrote:
> > >> On 10/12/2024, Dmitry Baryshkov wrote:
> > >>> On Sat, Oct 12, 2024 at 03:35:39PM +0800, Liu Ying wrote:
> > >>>> Document ITE IT6263 LVDS to HDMI converter.
> > >>>>
> > >>>> Product link:
> > >>>> https://www.ite.com.tw/en/product/cate1/IT6263
> > >>>>
> > >>>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> > >>>> ---
> > >>>> v2:
> > >>>> * Document number of LVDS link data lanes. (Biju)
> > >>>> * Simplify ports property by dropping "oneOf". (Rob)
> > >>>>
> > >>>> .../bindings/display/bridge/ite,it6263.yaml | 276 ++++++++++++++++++
> > >>>> 1 file changed, 276 insertions(+) create mode 100644
> > >>>> Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
> > >>>>
> > >>>> diff --git
> > >>>> a/Documentation/devicetree/bindings/display/bridge/ite,it6263.yam
> > >>>> l
> > >>>> b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yam
> > >>>> l
> > >>>> new file mode 100644
> > >>>> index 000000000000..bc2bbec07623
> > >>>> --- /dev/null
> > >>>> +++ b/Documentation/devicetree/bindings/display/bridge/ite,it6263
> > >>>> +++ .y
> > >>>> +++ aml
> > >>>> @@ -0,0 +1,276 @@
> > >>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> > >>>> +1.2
> > >>>> +---
> > >>>> +$id:
> > >>>> +http://devicetree.org/schemas/display/bridge/ite,it6263.yaml#
> > >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > >>>> +
> > >>>> +title: ITE IT6263 LVDS to HDMI converter
> > >>>> +
> > >>>> +maintainers:
> > >>>> + - Liu Ying <victor.liu@nxp.com>
> > >>>> +
> > >>>> +description: |
> > >>>> + The IT6263 is a high-performance single-chip De-SSC(De-Spread
> > >>>> +Spectrum) LVDS
> > >>>> + to HDMI converter. Combined with LVDS receiver and HDMI 1.4a
> > >>>> +transmitter,
> > >>>> + the IT6263 supports LVDS input and HDMI 1.4 output by conversion function.
> > >>>> + The built-in LVDS receiver can support single-link and
> > >>>> +dual-link LVDS inputs,
> > >>>> + and the built-in HDMI transmitter is fully compliant with HDMI
> > >>>> +1.4a/3D, HDCP
> > >>>> + 1.2 and backward compatible with DVI 1.0 specification.
> > >>>> +
> > >>>> + The IT6263 also encodes and transmits up to 8 channels of I2S
> > >>>> + digital audio, with sampling rate up to 192KHz and sample size
> > >>>> + up to 24 bits. In addition, an S/PDIF input port takes in
> > >>>> + compressed audio of up to 192KHz
> > frame rate.
> > >>>> +
> > >>>> + The newly supported High-Bit Rate(HBR) audio by HDMI
> > >>>> + specifications v1.3 is provided by the IT6263 in two interfaces:
> > >>>> + the four I2S input ports or the S/PDIF input port. With both
> > >>>> + interfaces the highest possible HBR frame rate is supported at up to 768KHz.
> > >>>> +
> > >>>> +properties:
> > >>>
> > >>> No LVDS data-mapping support?
> > >>
> > >> It is enough to document number of LVDS link data lanes because OS
> > >> should be able to determine the data-mapping by looking at the
> > >> number and the data-mapping capability of the other side of the LVDS link.
> > >
> > > From what I can see, data-mapping is specified on the consumer sink
> > > side of the LVDS link. This means it should go to the bridge's device node.
> >
> > Then, I won't define data-lanes, because data-mapping implies it,
> > e.g., jeida-24 implies data lanes 0/1/2/3, see lvds-data-mapping.yaml.
> >
> > Please let me know which one you prefer.
>
> Assume a top level use case where a user changes the format from JEDAI to VESA using On screen display
> or modetest(if some one adds support for lvds-mapping) then setting of the lvds data mapping should be
> dynamic.
>
> Maybe for initial version hardcode with JEDAI or VESA as default and provide a way to override the
> host driver and bridge with requested lvds-data mapping dynamically later??
>
Maybe use ret = drm_of_lvds_get_data_mapping(bus_node); to get LVDS data mapping see LVDS panel driver??
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/gpu/drm/bridge/lvds-codec.c?h=next-20241011#n173
Cheeers,
Biju
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-14 7:39 ` Biju Das
2024-10-14 7:58 ` Biju Das
@ 2024-10-14 8:04 ` Dmitry Baryshkov
2024-10-14 8:09 ` Biju Das
1 sibling, 1 reply; 49+ messages in thread
From: Dmitry Baryshkov @ 2024-10-14 8:04 UTC (permalink / raw)
To: Biju Das
Cc: Liu Ying, dri-devel@lists.freedesktop.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
andrzej.hajda@intel.com, neil.armstrong@linaro.org,
rfoss@kernel.org, laurent.pinchart, jonas@kwiboo.se,
jernej.skrabec@gmail.com, airlied@gmail.com, simona@ffwll.ch,
maarten.lankhorst@linux.intel.com, mripard@kernel.org,
tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com,
catalin.marinas@arm.com, will@kernel.org,
quic_bjorande@quicinc.com, geert+renesas@glider.be, arnd@arndb.de,
nfraprado@collabora.com, o.rempel@pengutronix.de,
y.moog@phytec.de, marex@denx.de, isaac.scott@ideasonboard.com
On Mon, Oct 14, 2024 at 07:39:16AM +0000, Biju Das wrote:
> Hi Liu and Dmitry,
>
> > -----Original Message-----
> > From: Liu Ying <victor.liu@nxp.com>
> > Sent: Monday, October 14, 2024 6:34 AM
> > Subject: Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
> >
> > On 10/14/2024, Dmitry Baryshkov wrote:
> > > On Sat, Oct 12, 2024 at 05:14:13PM +0800, Liu Ying wrote:
> > >> On 10/12/2024, Dmitry Baryshkov wrote:
> > >>> On Sat, Oct 12, 2024 at 03:35:39PM +0800, Liu Ying wrote:
> > >>>> Document ITE IT6263 LVDS to HDMI converter.
> > >>>>
> > >>>> Product link:
> > >>>> https://www.ite.com.tw/en/product/cate1/IT6263
> > >>>>
> > >>>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> > >>>> ---
> > >>>> v2:
> > >>>> * Document number of LVDS link data lanes. (Biju)
> > >>>> * Simplify ports property by dropping "oneOf". (Rob)
> > >>>>
> > >>>> .../bindings/display/bridge/ite,it6263.yaml | 276 ++++++++++++++++++
> > >>>> 1 file changed, 276 insertions(+)
> > >>>> create mode 100644
> > >>>> Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
> > >>>>
> > >>>> diff --git
> > >>>> a/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
> > >>>> b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
> > >>>> new file mode 100644
> > >>>> index 000000000000..bc2bbec07623
> > >>>> --- /dev/null
> > >>>> +++ b/Documentation/devicetree/bindings/display/bridge/ite,it6263.y
> > >>>> +++ aml
> > >>>> @@ -0,0 +1,276 @@
> > >>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> > >>>> +1.2
> > >>>> +---
> > >>>> +$id: http://devicetree.org/schemas/display/bridge/ite,it6263.yaml#
> > >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > >>>> +
> > >>>> +title: ITE IT6263 LVDS to HDMI converter
> > >>>> +
> > >>>> +maintainers:
> > >>>> + - Liu Ying <victor.liu@nxp.com>
> > >>>> +
> > >>>> +description: |
> > >>>> + The IT6263 is a high-performance single-chip De-SSC(De-Spread
> > >>>> +Spectrum) LVDS
> > >>>> + to HDMI converter. Combined with LVDS receiver and HDMI 1.4a
> > >>>> +transmitter,
> > >>>> + the IT6263 supports LVDS input and HDMI 1.4 output by conversion function.
> > >>>> + The built-in LVDS receiver can support single-link and dual-link
> > >>>> +LVDS inputs,
> > >>>> + and the built-in HDMI transmitter is fully compliant with HDMI
> > >>>> +1.4a/3D, HDCP
> > >>>> + 1.2 and backward compatible with DVI 1.0 specification.
> > >>>> +
> > >>>> + The IT6263 also encodes and transmits up to 8 channels of I2S
> > >>>> + digital audio, with sampling rate up to 192KHz and sample size
> > >>>> + up to 24 bits. In addition, an S/PDIF input port takes in compressed audio of up to 192KHz
> > frame rate.
> > >>>> +
> > >>>> + The newly supported High-Bit Rate(HBR) audio by HDMI
> > >>>> + specifications v1.3 is provided by the IT6263 in two interfaces:
> > >>>> + the four I2S input ports or the S/PDIF input port. With both
> > >>>> + interfaces the highest possible HBR frame rate is supported at up to 768KHz.
> > >>>> +
> > >>>> +properties:
> > >>>
> > >>> No LVDS data-mapping support?
> > >>
> > >> It is enough to document number of LVDS link data lanes because OS
> > >> should be able to determine the data-mapping by looking at the number
> > >> and the data-mapping capability of the other side of the LVDS link.
> > >
> > > From what I can see, data-mapping is specified on the consumer sink
> > > side of the LVDS link. This means it should go to the bridge's device node.
> >
> > Then, I won't define data-lanes, because data-mapping implies it, e.g., jeida-24 implies data lanes
> > 0/1/2/3, see lvds-data-mapping.yaml.
> >
> > Please let me know which one you prefer.
>
> Assume a top level use case where a user changes the format from JEDAI to VESA using On screen
> display or modetest(if some one adds support for lvds-mapping) then setting of the lvds data mapping
> should be dynamic.
>
> Maybe for initial version hardcode with JEDAI or VESA as default and provide a way to override
> the host driver and bridge with requested lvds-data mapping dynamically later??
The ite,lvds-link-num-data-lanes property should be removed, it is not
standard. I foresee two ways to specify the number of lanes used: either
the data-lanes property or the data-mapping property. Granted that
data-mapping replaces the data-lanes functionality for LVDS links, I
think it's better to use it from the start.
Frankly speaking, what is the usecase for specifying the data mapping
dynamically? What kind of uAPI do you have in mind and what is the
usecase for it?
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 49+ messages in thread
* RE: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-14 8:04 ` Dmitry Baryshkov
@ 2024-10-14 8:09 ` Biju Das
2024-10-14 11:16 ` Dmitry Baryshkov
0 siblings, 1 reply; 49+ messages in thread
From: Biju Das @ 2024-10-14 8:09 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Liu Ying, dri-devel@lists.freedesktop.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
andrzej.hajda@intel.com, neil.armstrong@linaro.org,
rfoss@kernel.org, laurent.pinchart, jonas@kwiboo.se,
jernej.skrabec@gmail.com, airlied@gmail.com, simona@ffwll.ch,
maarten.lankhorst@linux.intel.com, mripard@kernel.org,
tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com,
catalin.marinas@arm.com, will@kernel.org,
quic_bjorande@quicinc.com, geert+renesas@glider.be, arnd@arndb.de,
nfraprado@collabora.com, o.rempel@pengutronix.de,
y.moog@phytec.de, marex@denx.de, isaac.scott@ideasonboard.com
Hi Dmitry,
> -----Original Message-----
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Sent: Monday, October 14, 2024 9:04 AM
> Subject: Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
>
> On Mon, Oct 14, 2024 at 07:39:16AM +0000, Biju Das wrote:
> > Hi Liu and Dmitry,
> >
> > > -----Original Message-----
> > > From: Liu Ying <victor.liu@nxp.com>
> > > Sent: Monday, October 14, 2024 6:34 AM
> > > Subject: Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE
> > > IT6263 LVDS to HDMI converter
> > >
> > > On 10/14/2024, Dmitry Baryshkov wrote:
> > > > On Sat, Oct 12, 2024 at 05:14:13PM +0800, Liu Ying wrote:
> > > >> On 10/12/2024, Dmitry Baryshkov wrote:
> > > >>> On Sat, Oct 12, 2024 at 03:35:39PM +0800, Liu Ying wrote:
> > > >>>> Document ITE IT6263 LVDS to HDMI converter.
> > > >>>>
> > > >>>> Product link:
> > > >>>> https://www.ite.com.tw/en/product/cate1/IT6263
> > > >>>>
> > > >>>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> > > >>>> ---
> > > >>>> v2:
> > > >>>> * Document number of LVDS link data lanes. (Biju)
> > > >>>> * Simplify ports property by dropping "oneOf". (Rob)
> > > >>>>
> > > >>>> .../bindings/display/bridge/ite,it6263.yaml | 276 ++++++++++++++++++
> > > >>>> 1 file changed, 276 insertions(+) create mode 100644
> > > >>>> Documentation/devicetree/bindings/display/bridge/ite,it6263.yam
> > > >>>> l
> > > >>>>
> > > >>>> diff --git
> > > >>>> a/Documentation/devicetree/bindings/display/bridge/ite,it6263.y
> > > >>>> aml
> > > >>>> b/Documentation/devicetree/bindings/display/bridge/ite,it6263.y
> > > >>>> aml
> > > >>>> new file mode 100644
> > > >>>> index 000000000000..bc2bbec07623
> > > >>>> --- /dev/null
> > > >>>> +++ b/Documentation/devicetree/bindings/display/bridge/ite,it62
> > > >>>> +++ 63.y
> > > >>>> +++ aml
> > > >>>> @@ -0,0 +1,276 @@
> > > >>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > >>>> +%YAML
> > > >>>> +1.2
> > > >>>> +---
> > > >>>> +$id:
> > > >>>> +http://devicetree.org/schemas/display/bridge/ite,it6263.yaml#
> > > >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > >>>> +
> > > >>>> +title: ITE IT6263 LVDS to HDMI converter
> > > >>>> +
> > > >>>> +maintainers:
> > > >>>> + - Liu Ying <victor.liu@nxp.com>
> > > >>>> +
> > > >>>> +description: |
> > > >>>> + The IT6263 is a high-performance single-chip
> > > >>>> +De-SSC(De-Spread
> > > >>>> +Spectrum) LVDS
> > > >>>> + to HDMI converter. Combined with LVDS receiver and HDMI
> > > >>>> +1.4a transmitter,
> > > >>>> + the IT6263 supports LVDS input and HDMI 1.4 output by conversion function.
> > > >>>> + The built-in LVDS receiver can support single-link and
> > > >>>> +dual-link LVDS inputs,
> > > >>>> + and the built-in HDMI transmitter is fully compliant with
> > > >>>> +HDMI 1.4a/3D, HDCP
> > > >>>> + 1.2 and backward compatible with DVI 1.0 specification.
> > > >>>> +
> > > >>>> + The IT6263 also encodes and transmits up to 8 channels of
> > > >>>> + I2S digital audio, with sampling rate up to 192KHz and
> > > >>>> + sample size up to 24 bits. In addition, an S/PDIF input port
> > > >>>> + takes in compressed audio of up to 192KHz
> > > frame rate.
> > > >>>> +
> > > >>>> + The newly supported High-Bit Rate(HBR) audio by HDMI
> > > >>>> + specifications v1.3 is provided by the IT6263 in two interfaces:
> > > >>>> + the four I2S input ports or the S/PDIF input port. With
> > > >>>> + both interfaces the highest possible HBR frame rate is supported at up to 768KHz.
> > > >>>> +
> > > >>>> +properties:
> > > >>>
> > > >>> No LVDS data-mapping support?
> > > >>
> > > >> It is enough to document number of LVDS link data lanes because
> > > >> OS should be able to determine the data-mapping by looking at the
> > > >> number and the data-mapping capability of the other side of the LVDS link.
> > > >
> > > > From what I can see, data-mapping is specified on the consumer
> > > > sink side of the LVDS link. This means it should go to the bridge's device node.
> > >
> > > Then, I won't define data-lanes, because data-mapping implies it,
> > > e.g., jeida-24 implies data lanes 0/1/2/3, see lvds-data-mapping.yaml.
> > >
> > > Please let me know which one you prefer.
> >
> > Assume a top level use case where a user changes the format from JEDAI
> > to VESA using On screen display or modetest(if some one adds support
> > for lvds-mapping) then setting of the lvds data mapping should be dynamic.
> >
> > Maybe for initial version hardcode with JEDAI or VESA as default and
> > provide a way to override the host driver and bridge with requested lvds-data mapping dynamically
> later??
>
> The ite,lvds-link-num-data-lanes property should be removed, it is not standard. I foresee two ways to
> specify the number of lanes used: either the data-lanes property or the data-mapping property. Granted
> that data-mapping replaces the data-lanes functionality for LVDS links, I think it's better to use it
> from the start.
>
> Frankly speaking, what is the usecase for specifying the data mapping dynamically? What kind of uAPI
> do you have in mind and what is the usecase for it?
It simple just want to change from VESA to JEDAI, how do you change it with existing DRM framework?
Currently I see LVDS panel driver use drm_of_lvds_get_data_mapping(bus_node) to get this info.
IT6263 bridge device can use that API to get that info.
Some vendors use VESA as default LVDS data mapping whereas some others use JEDAI.
Cheers,
Biju
^ permalink raw reply [flat|nested] 49+ messages in thread
* RE: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-14 7:18 ` Liu Ying
2024-10-14 7:32 ` Dmitry Baryshkov
@ 2024-10-14 8:14 ` Biju Das
2024-10-14 8:37 ` Liu Ying
1 sibling, 1 reply; 49+ messages in thread
From: Biju Das @ 2024-10-14 8:14 UTC (permalink / raw)
To: Liu Ying, Dmitry Baryshkov
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org, andrzej.hajda@intel.com,
neil.armstrong@linaro.org, rfoss@kernel.org, laurent.pinchart,
jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com,
simona@ffwll.ch, maarten.lankhorst@linux.intel.com,
mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com,
catalin.marinas@arm.com, will@kernel.org,
quic_bjorande@quicinc.com, geert+renesas@glider.be, arnd@arndb.de,
nfraprado@collabora.com, o.rempel@pengutronix.de,
y.moog@phytec.de, marex@denx.de, isaac.scott@ideasonboard.com
Hi Liu Ying,
> -----Original Message-----
> From: Liu Ying <victor.liu@nxp.com>
> Sent: Monday, October 14, 2024 8:18 AM
> Subject: Re: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
>
> On 10/14/2024, Dmitry Baryshkov wrote:
> > On Sat, Oct 12, 2024 at 03:35:40PM +0800, Liu Ying wrote:
> >> Add basic HDMI video output support. Currently, only RGB888 output
> >> pixel format is supported. At the LVDS input side, the driver
> >> supports single LVDS link and dual LVDS links with "jeida-24" LVDS
> >> mapping.
> >>
> >> Product link:
> >> https://www.ite.com.tw/en/product/cate1/IT6263
> >>
> >> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> >> ---
> >> v2:
> >> * Add AVI inforframe support. (Maxime)
> >> * Add DRM_MODE_CONNECTOR_HDMIA. (Biju)
> >> * Rename it6263_reset() to it6263_hw_reset(). (Biju)
> >> * Check number of LVDS link data lanes. (Biju)
> >>
> >> drivers/gpu/drm/bridge/Kconfig | 8 +
> >> drivers/gpu/drm/bridge/Makefile | 1 +
> >> drivers/gpu/drm/bridge/ite-it6263.c | 919
> >> ++++++++++++++++++++++++++++
> >> 3 files changed, 928 insertions(+)
> >> create mode 100644 drivers/gpu/drm/bridge/ite-it6263.c
> >>
> >
> > [...]
> >
> >> +static int it6263_parse_dt(struct it6263 *it) {
> >> + struct device *dev = it->dev;
> >> + struct device_node *port0, *port1;
> >> + int ret;
> >> +
> >> + ret = of_property_read_u8(dev->of_node, "ite,lvds-link-num-data-lanes",
> >> + &it->lvds_link_num_dlanes);
> >> + if (ret) {
> >> + dev_err(dev, "failed to get LVDS link number of data lanes: %d\n",
> >> + ret);
> >> + return ret;
> >> + }
> >> +
> >> + it->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0);
> >> + if (IS_ERR(it->next_bridge))
> >> + return dev_err_probe(dev, PTR_ERR(it->next_bridge),
> >> + "failed to get next bridge\n");
> >> +
> >> + port0 = of_graph_get_port_by_id(dev->of_node, 0);
> >> + port1 = of_graph_get_port_by_id(dev->of_node, 1);
> >> + if (port0 && port1) {
> >> + if (of_property_read_bool(port0, "dual-lvds-even-pixels") &&
> >> + of_property_read_bool(port1, "dual-lvds-odd-pixels")) {
> >> + it->lvds_dual_link = true;
> >> + it->lvds_link12_swap = true;
> >> + } else if (of_property_read_bool(port0, "dual-lvds-odd-pixels") &&
> >> + of_property_read_bool(port1, "dual-lvds-even-pixels")) {
> >> + it->lvds_dual_link = true;
> >> + }
> >> +
> >> + if (!it->lvds_dual_link) {
> >> + dev_err(dev,
> >> + "failed to get LVDS dual link pixel order\n");
> >> + ret = -EINVAL;
> >> + }
> >
> > Please use drm_of_lvds_get_dual_link_pixel_order(), it validates that
> > the DT definition is sound: one port for odd pixels, one port for even
> > pixels.
>
> It cannot be used, because it get the pixel order for the LVDS source not sink. IT6263 is the LVDS
> sink.
>
> * drm_of_lvds_get_dual_link_pixel_order - Get LVDS dual-link pixel order
> * @port1: First DT port node of the Dual-link LVDS source
> * @port2: Second DT port node of the Dual-link LVDS source
Can't you use drm_of_lvds_get_dual_link_pixel_order() from host for the same use case. See [1]?
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c?h=next-20241011
lvds_bridge0: lvds-to-hdmi-bridge@4c {
compatible = "ite,it6263";
reg = <0x4c>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dual-lvds-odd-pixels;
lvds0_in0: endpoint@0 {
remote-endpoint = <&lvds0_out>;
};
};
port@1 {
reg = <1>;
dual-lvds-even-pixels;
lvds0_in1: endpoint@1 {
remote-endpoint = <&lvds1_out>;
};
};
port@2 {
reg = <2>;
it6263_out: endpoint@2 {
remote-endpoint = <&lvds_to_hdmi_con_out>;
};
};
};
};
};
Cheers,
Biju
>
> >
> >> + } else if (port1) {
> >> + ret = -EINVAL;
> >> + dev_err(dev, "single input LVDS port1 is not supported\n");
> >> + } else if (!port0) {
> >> + ret = -EINVAL;
> >> + dev_err(dev, "no input LVDS port\n");
> >> + }
> >> +
> >> + of_node_put(port0);
> >> + of_node_put(port1);
> >> +
> >> + return ret;
> >> +}
> >> +
> >
>
> --
> Regards,
> Liu Ying
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-14 7:32 ` Dmitry Baryshkov
@ 2024-10-14 8:28 ` Liu Ying
2024-10-14 11:22 ` Dmitry Baryshkov
0 siblings, 1 reply; 49+ messages in thread
From: Liu Ying @ 2024-10-14 8:28 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel,
andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
arnd, nfraprado, o.rempel, y.moog, marex, isaac.scott,
biju.das.jz
On 10/14/2024, Dmitry Baryshkov wrote:
> On Mon, Oct 14, 2024 at 03:18:15PM +0800, Liu Ying wrote:
>> On 10/14/2024, Dmitry Baryshkov wrote:
>>> On Sat, Oct 12, 2024 at 03:35:40PM +0800, Liu Ying wrote:
>>>> Add basic HDMI video output support. Currently, only RGB888 output
>>>> pixel format is supported. At the LVDS input side, the driver
>>>> supports single LVDS link and dual LVDS links with "jeida-24" LVDS
>>>> mapping.
>>>>
>>>> Product link:
>>>> https://www.ite.com.tw/en/product/cate1/IT6263
>>>>
>>>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
>>>> ---
>>>> v2:
>>>> * Add AVI inforframe support. (Maxime)
>>>> * Add DRM_MODE_CONNECTOR_HDMIA. (Biju)
>>>> * Rename it6263_reset() to it6263_hw_reset(). (Biju)
>>>> * Check number of LVDS link data lanes. (Biju)
>>>>
>>>> drivers/gpu/drm/bridge/Kconfig | 8 +
>>>> drivers/gpu/drm/bridge/Makefile | 1 +
>>>> drivers/gpu/drm/bridge/ite-it6263.c | 919 ++++++++++++++++++++++++++++
>>>> 3 files changed, 928 insertions(+)
>>>> create mode 100644 drivers/gpu/drm/bridge/ite-it6263.c
>>>>
>>>
>>> [...]
>>>
>>>> +static int it6263_parse_dt(struct it6263 *it)
>>>> +{
>>>> + struct device *dev = it->dev;
>>>> + struct device_node *port0, *port1;
>>>> + int ret;
>>>> +
>>>> + ret = of_property_read_u8(dev->of_node, "ite,lvds-link-num-data-lanes",
>>>> + &it->lvds_link_num_dlanes);
>>>> + if (ret) {
>>>> + dev_err(dev, "failed to get LVDS link number of data lanes: %d\n",
>>>> + ret);
>>>> + return ret;
>>>> + }
>>>> +
>>>> + it->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0);
>>>> + if (IS_ERR(it->next_bridge))
>>>> + return dev_err_probe(dev, PTR_ERR(it->next_bridge),
>>>> + "failed to get next bridge\n");
>>>> +
>>>> + port0 = of_graph_get_port_by_id(dev->of_node, 0);
>>>> + port1 = of_graph_get_port_by_id(dev->of_node, 1);
>>>> + if (port0 && port1) {
>>>> + if (of_property_read_bool(port0, "dual-lvds-even-pixels") &&
>>>> + of_property_read_bool(port1, "dual-lvds-odd-pixels")) {
>>>> + it->lvds_dual_link = true;
>>>> + it->lvds_link12_swap = true;
>>>> + } else if (of_property_read_bool(port0, "dual-lvds-odd-pixels") &&
>>>> + of_property_read_bool(port1, "dual-lvds-even-pixels")) {
>>>> + it->lvds_dual_link = true;
>>>> + }
>>>> +
>>>> + if (!it->lvds_dual_link) {
>>>> + dev_err(dev,
>>>> + "failed to get LVDS dual link pixel order\n");
>>>> + ret = -EINVAL;
>>>> + }
>>>
>>> Please use drm_of_lvds_get_dual_link_pixel_order(), it validates that
>>> the DT definition is sound: one port for odd pixels, one port for even
>>> pixels.
>>
>> It cannot be used, because it get the pixel order for the LVDS
>> source not sink. IT6263 is the LVDS sink.
>
> Then you need a similar function for the sink side. Add it to the
> drm_of.c
How about getting remote LVDS source ports first and use
drm_of_lvds_get_dual_link_pixel_order() like the snippet below?
This way, no need to add a similar function or modify
drm_of_lvds_get_dual_link_pixel_order() implementation.
If you don't like this, can you please suggest a similar function
name or maybe an additional parameter(with type and name) for
drm_of_lvds_get_dual_link_pixel_order()?
---8<---
port0_ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
if (port0_ep) {
remote_port0 = of_graph_get_remote_port(port0_ep);
of_node_put(port0_ep);
}
port1_ep = of_graph_get_endpoint_by_regs(dev->of_node, 1, -1);
if (port1_ep) {
remote_port1 = of_graph_get_remote_port(port1_ep);
of_node_put(port1_ep);
}
if (remote_port0 && remote_port1) {
order = drm_of_lvds_get_dual_link_pixel_order(remote_port0,
remote_port1);
if (order < 0) {
dev_err(dev,
"failed to get dual link pixel order: %d\n",
order);
ret = order;
} else if (order == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) {
it->lvds_dual_link = true;
} else if (order == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) {
it->lvds_dual_link = true;
it->lvds_link12_swap = true;
}
} else if (remote_port1) {
ret = -EINVAL;
dev_err(dev, "single input LVDS port1 is not supported\n");
} else if (!remote_port0) {
ret = -EINVAL;
dev_err(dev, "no input LVDS port\n");
}
of_node_put(remote_port0);
of_node_put(remote_port1);
---8<---
>
>>
>> * drm_of_lvds_get_dual_link_pixel_order - Get LVDS dual-link pixel order
>> * @port1: First DT port node of the Dual-link LVDS source
>> * @port2: Second DT port node of the Dual-link LVDS source
>>
>>>
>>>> + } else if (port1) {
>>>> + ret = -EINVAL;
>>>> + dev_err(dev, "single input LVDS port1 is not supported\n");
>>>> + } else if (!port0) {
>>>> + ret = -EINVAL;
>>>> + dev_err(dev, "no input LVDS port\n");
>>>> + }
>>>> +
>>>> + of_node_put(port0);
>>>> + of_node_put(port1);
>>>> +
>>>> + return ret;
>>>> +}
>>>> +
>>>
>>
>> --
>> Regards,
>> Liu Ying
>>
>
--
Regards,
Liu Ying
^ permalink raw reply [flat|nested] 49+ messages in thread
* RE: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-14 5:33 ` Liu Ying
` (2 preceding siblings ...)
2024-10-14 7:39 ` Biju Das
@ 2024-10-14 8:30 ` Biju Das
3 siblings, 0 replies; 49+ messages in thread
From: Biju Das @ 2024-10-14 8:30 UTC (permalink / raw)
To: Liu Ying, Dmitry Baryshkov
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org, andrzej.hajda@intel.com,
neil.armstrong@linaro.org, rfoss@kernel.org, laurent.pinchart,
jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com,
simona@ffwll.ch, maarten.lankhorst@linux.intel.com,
mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com,
catalin.marinas@arm.com, will@kernel.org,
quic_bjorande@quicinc.com, geert+renesas@glider.be, arnd@arndb.de,
nfraprado@collabora.com, o.rempel@pengutronix.de,
y.moog@phytec.de, marex@denx.de, isaac.scott@ideasonboard.com
Hi Liu,
> -----Original Message-----
> From: Liu Ying <victor.liu@nxp.com>
> Sent: Monday, October 14, 2024 6:34 AM
> Subject: Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
>
> On 10/14/2024, Dmitry Baryshkov wrote:
> > On Sat, Oct 12, 2024 at 05:14:13PM +0800, Liu Ying wrote:
> >> On 10/12/2024, Dmitry Baryshkov wrote:
> >>> On Sat, Oct 12, 2024 at 03:35:39PM +0800, Liu Ying wrote:
> >>>> Document ITE IT6263 LVDS to HDMI converter.
> >>>>
> >>>> Product link:
> >>>> https://www.ite.com.tw/en/product/cate1/IT6263
> >>>>
> >>>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> >>>> ---
> >>>> v2:
> >>>> * Document number of LVDS link data lanes. (Biju)
> >>>> * Simplify ports property by dropping "oneOf". (Rob)
> >>>>
> >>>> .../bindings/display/bridge/ite,it6263.yaml | 276 ++++++++++++++++++
> >>>> 1 file changed, 276 insertions(+)
> >>>> create mode 100644
> >>>> Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
> >>>>
> >>>> diff --git
> >>>> a/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
> >>>> b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
> >>>> new file mode 100644
> >>>> index 000000000000..bc2bbec07623
> >>>> --- /dev/null
> >>>> +++ b/Documentation/devicetree/bindings/display/bridge/ite,it6263.y
> >>>> +++ aml
> >>>> @@ -0,0 +1,276 @@
> >>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> >>>> +1.2
> >>>> +---
> >>>> +$id: http://devicetree.org/schemas/display/bridge/ite,it6263.yaml#
> >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>>> +
> >>>> +title: ITE IT6263 LVDS to HDMI converter
> >>>> +
> >>>> +maintainers:
> >>>> + - Liu Ying <victor.liu@nxp.com>
> >>>> +
> >>>> +description: |
> >>>> + The IT6263 is a high-performance single-chip De-SSC(De-Spread
> >>>> +Spectrum) LVDS
> >>>> + to HDMI converter. Combined with LVDS receiver and HDMI 1.4a
> >>>> +transmitter,
> >>>> + the IT6263 supports LVDS input and HDMI 1.4 output by conversion function.
> >>>> + The built-in LVDS receiver can support single-link and dual-link
> >>>> +LVDS inputs,
> >>>> + and the built-in HDMI transmitter is fully compliant with HDMI
> >>>> +1.4a/3D, HDCP
> >>>> + 1.2 and backward compatible with DVI 1.0 specification.
> >>>> +
> >>>> + The IT6263 also encodes and transmits up to 8 channels of I2S
> >>>> + digital audio, with sampling rate up to 192KHz and sample size
> >>>> + up to 24 bits. In addition, an S/PDIF input port takes in compressed audio of up to 192KHz
> frame rate.
> >>>> +
> >>>> + The newly supported High-Bit Rate(HBR) audio by HDMI
> >>>> + specifications v1.3 is provided by the IT6263 in two interfaces:
> >>>> + the four I2S input ports or the S/PDIF input port. With both
> >>>> + interfaces the highest possible HBR frame rate is supported at up to 768KHz.
> >>>> +
> >>>> +properties:
> >>>
> >>> No LVDS data-mapping support?
> >>
> >> It is enough to document number of LVDS link data lanes because OS
> >> should be able to determine the data-mapping by looking at the number
> >> and the data-mapping capability of the other side of the LVDS link.
> >
> > From what I can see, data-mapping is specified on the consumer sink
> > side of the LVDS link. This means it should go to the bridge's device node.
>
> Then, I won't define data-lanes, because data-mapping implies it, e.g., jeida-24 implies data lanes
> 0/1/2/3, see lvds-data-mapping.yaml.
>
> Please let me know which one you prefer.
For consistency, maybe use data-mapping. See [1]
[1]
https://elixir.bootlin.com/linux/v6.0-rc4/source/Documentation/devicetree/bindings/display/panel/advantech,idk-2121wr.yaml#L26
Cheers,
Biju
>
> >
> >>
> >>>
> >>>> + compatible:
> >>>> + const: ite,it6263
> >>>> +
> >>>> + reg:
> >>>> + maxItems: 1
> >>>> +
> >>>> + clocks:
> >>>> + maxItems: 1
> >>>> + description: audio master clock
> >>>> +
> >>>> + clock-names:
> >>>> + const: mclk
> >>>> +
> >>>> + reset-gpios:
> >>>> + maxItems: 1
> >>>> +
> >>>> + ivdd-supply:
> >>>> + description: 1.8V digital logic power
> >>>> +
> >>>> + ovdd-supply:
> >>>> + description: 3.3V I/O pin power
> >>>> +
> >>>> + txavcc18-supply:
> >>>> + description: 1.8V HDMI analog frontend power
> >>>> +
> >>>> + txavcc33-supply:
> >>>> + description: 3.3V HDMI analog frontend power
> >>>> +
> >>>> + pvcc1-supply:
> >>>> + description: 1.8V HDMI frontend core PLL power
> >>>> +
> >>>> + pvcc2-supply:
> >>>> + description: 1.8V HDMI frontend filter PLL power
> >>>> +
> >>>> + avcc-supply:
> >>>> + description: 3.3V LVDS frontend power
> >>>> +
> >>>> + anvdd-supply:
> >>>> + description: 1.8V LVDS frontend analog power
> >>>> +
> >>>> + apvdd-supply:
> >>>> + description: 1.8V LVDS frontend PLL power
> >>>> +
> >>>> + "#sound-dai-cells":
> >>>> + const: 0
> >>>> +
> >>>> + ite,lvds-link-num-data-lanes:
> >>>> + $ref: /schemas/types.yaml#/definitions/uint8
> >>>> + enum: [3, 4, 5]
> >>>> + description: number of data lanes per LVDS link
> >>>
> >>> Please use data-lanes property inside the OF graph.
> >>
> >> In both port@0 and port@1?
> >
> > Yes
>
> I'm assuming if data-mapping is defined, then no need to define data-lanes.
>
> >
> >>
> >>>
> >>>> +
> >>>> + ite,i2s-audio-fifo-sources:
> >>>> + $ref: /schemas/types.yaml#/definitions/uint32-array
> >>>> + minItems: 1
> >>>> + maxItems: 4
> >>>> + items:
> >>>> + enum: [0, 1, 2, 3]
> >>>> + description:
> >>>> + Each array element indicates the pin number of an I2S serial data input
> >>>> + line which is connected to an audio FIFO, from audio FIFO0 to FIFO3.
> >>>
> >>> What does that mean from the board point of view? Routed audio links
> >>> for the multichannel audio?
> >>
> >> Yes, also for single channel audio.
> >>
> >>>
> >>>> +
> >>>> + ite,rl-channel-swap-audio-sources:
> >>>> + $ref: /schemas/types.yaml#/definitions/uint32-array
> >>>> + minItems: 1
> >>>> + maxItems: 4
> >>>> + uniqueItems: true
> >>>> + items:
> >>>> + enum: [0, 1, 2, 3]
> >>>> + description:
> >>>> + Each array element indicates an audio source whose right channel and left
> >>>> + channel are swapped by this converter. For I2S, the element is the pin
> >>>> + number of an I2S serial data input line. For S/PDIF, the element is always
> >>>> + 0.
> >>>
> >>> Why?
> >>
> >> Because this converter has the capability to swap right channel and
> >> left channel and S/PDIF always uses audio source0.
> >>
> >>>
> >>>> +
> >>>> + ports:
> >>>> + $ref: /schemas/graph.yaml#/properties/ports
> >>>> +
> >>>> + properties:
> >>>> + port@0:
> >>>> + $ref: /schemas/graph.yaml#/$defs/port-base
> >>>> + unevaluatedProperties: false
> >>>> + description:
> >>>> + The first LVDS input link.
> >>>> + In dual-link LVDS mode, this link works together with the second LVDS
> >>>> + input link, and one link receives odd pixels while the other receives
> >>>> + even pixels. Specify the pixels with one of the dual-lvds-odd-pixels
> >>>> + and dual-lvds-even-pixels properties when and only when dual-link LVDS
> >>>> + mode is used.
> >>>> +
> >>>> + properties:
> >>>> + dual-lvds-odd-pixels:
> >>>> + type: boolean
> >>>> + description: the first sink port for odd pixels
> >>>> +
> >>>> + dual-lvds-even-pixels:
> >>>> + type: boolean
> >>>> + description: the first sink port for even pixels
> >>>> +
> >>>> + port@1:
> >>>> + $ref: /schemas/graph.yaml#/$defs/port-base
> >>>> + unevaluatedProperties: false
> >>>> + description: the second LVDS input link
> >>>> +
> >>>> + properties:
> >>>> + dual-lvds-even-pixels:
> >>>> + type: boolean
> >>>> + description: the second sink port for even pixels
> >>>> +
> >>>> + dual-lvds-odd-pixels:
> >>>> + type: boolean
> >>>> + description: the second sink port for odd pixels
> >>>> +
> >>>> + oneOf:
> >>>> + - required: [dual-lvds-even-pixels]
> >>>> + - required: [dual-lvds-odd-pixels]
> >>>
> >>> This still allows one to specify that both ports provide odd pixels.
> >>> Is that expected? Also why do you need two properties which specify
> >>> the same option.
> >>
> >> No, that is not expected. Description for port@0 already mentions one
> >> link receives odd pixels while the other receives even pixels.
> >
> > That's not expected, but permitted by the bindings.
>
> It is not permitted by port@1. If "dual-lvds-odd-pixels;" is added to port@1 in the dual-link LVDS
> example, the below warning will be generated by dt_binding_check.
>
> Documentation/devicetree/bindings/display/bridge/ite,it6263.example.dtb: hdmi@4c: ports:port@1:
> {'reg': [[1]], 'dual-lvds-even-pixels': True, 'dual-lvds-odd-pixels': True, 'endpoint': {'remote-
> endpoint': [[4294967295]]}} is valid under each of {'required': ['dual-lvds-odd-pixels']},
> {'required': ['dual-lvds-even-pixels']}
> from schema $id: http://devicetree.org/schemas/display/bridge/ite,it6263.yaml#
>
> However, the binding for port@0 does allow DT writers to specify both even and odd pixels. I raised
> similar concerns in v1 discussion.
> According to Rob's comment in #devicetree IRC, the ports property is simplified to this form and more
> description for port@0 is added to tell when to specify the even/odd pixels. If you know any better
> way to indicate the constraints, please shout.
>
> >
> >>
> >> Two options are supported for dual-link LVDS, not the same option:
> >> 1) LVDS link1(port@0) gets odd pixels
> >> and
> >> LVDS link2(port@1) gets even pixels.
> >>
> >> 2) LVDS link1(port@0) gets even pixels
> >> and
> >> LVDS link2(port@1) gets odd pixels.
> >> That's the reason why each port needs two properties to define
> >> odd/even pixels.
> >>
> >>>
> >>> My suggestion would be to add a single root-level property which
> >>> specifies which port provides even pixel data.
> >>
> >> That won't work. The LVDS source side expects the ports of the sink
> >> side specify dual-lvds-{odd,even}-pixels properties.
> >
> > I didn't notice that these properties are already defined.
> >
> > As these properties are common between several schema files, please
> > extract them to a common schema file (like lvds.yaml).
>
> I'm not sure how to do that. Is it obvious?
> Please shed some light.
>
> Only two panel schema files are defining even/odd pixels now - advantech,idk-2121wr.yaml and panel-
> simple-lvds-dual-ports.yaml.
> Maybe, extract them later when more schema files(especially for
> bridges) try to define the same? I'd like to keep a low profile for now.
>
> >
> >>
> >>>
> >>>> +
> >>>> + port@2:
> >>>> + $ref: /schemas/graph.yaml#/properties/port
> >>>> + description: video port for the HDMI output
> >>>> +
> >>>> + port@3:
> >>>> + $ref: /schemas/graph.yaml#/properties/port
> >>>> + description: sound input port
> >>>> +
> >>>> + required:
> >>>> + - port@0
> >>>> + - port@2
> >>>> +
> >>>> +required:
> >>>> + - compatible
> >>>> + - reg
> >>>> + - ivdd-supply
> >>>> + - ovdd-supply
> >>>> + - txavcc18-supply
> >>>> + - txavcc33-supply
> >>>> + - pvcc1-supply
> >>>> + - pvcc2-supply
> >>>> + - avcc-supply
> >>>> + - anvdd-supply
> >>>> + - apvdd-supply
> >>>> + - ite,lvds-link-num-data-lanes
> >>>> + - ports
> >>>> +
> >>>> +additionalProperties: false
> >>>> +
> >>>> +examples:
> >>>> + - |
> >>>> + /* single-link LVDS input */
> >>>> + #include <dt-bindings/gpio/gpio.h>
> >>>> +
> >>>> + i2c {
> >>>> + #address-cells = <1>;
> >>>> + #size-cells = <0>;
> >>>> +
> >>>> + hdmi@4c {
> >>>> + compatible = "ite,it6263";
> >>>> + reg = <0x4c>;
> >>>> + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
> >>>> + ivdd-supply = <®_buck5>;
> >>>> + ovdd-supply = <®_vext_3v3>;
> >>>> + txavcc18-supply = <®_buck5>;
> >>>> + txavcc33-supply = <®_vext_3v3>;
> >>>> + pvcc1-supply = <®_buck5>;
> >>>> + pvcc2-supply = <®_buck5>;
> >>>> + avcc-supply = <®_vext_3v3>;
> >>>> + anvdd-supply = <®_buck5>;
> >>>> + apvdd-supply = <®_buck5>;
> >>>> + ite,lvds-link-num-data-lanes = /bits/ 8 <4>;
> >>>> +
> >>>> + ports {
> >>>> + #address-cells = <1>;
> >>>> + #size-cells = <0>;
> >>>> +
> >>>> + port@0 {
> >>>> + reg = <0>;
> >>>> +
> >>>> + it6263_lvds_link1: endpoint {
> >>>> + remote-endpoint = <&ldb_lvds_ch0>;
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + port@2 {
> >>>> + reg = <2>;
> >>>> +
> >>>> + it6263_out: endpoint {
> >>>> + remote-endpoint = <&hdmi_in>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + - |
> >>>> + /* dual-link LVDS input */
> >>>> + #include <dt-bindings/gpio/gpio.h>
> >>>> +
> >>>> + i2c {
> >>>> + #address-cells = <1>;
> >>>> + #size-cells = <0>;
> >>>> +
> >>>> + hdmi@4c {
> >>>> + compatible = "ite,it6263";
> >>>> + reg = <0x4c>;
> >>>> + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
> >>>> + ivdd-supply = <®_buck5>;
> >>>> + ovdd-supply = <®_vext_3v3>;
> >>>> + txavcc18-supply = <®_buck5>;
> >>>> + txavcc33-supply = <®_vext_3v3>;
> >>>> + pvcc1-supply = <®_buck5>;
> >>>> + pvcc2-supply = <®_buck5>;
> >>>> + avcc-supply = <®_vext_3v3>;
> >>>> + anvdd-supply = <®_buck5>;
> >>>> + apvdd-supply = <®_buck5>;
> >>>> + ite,lvds-link-num-data-lanes = /bits/ 8 <4>;
> >>>> +
> >>>> + ports {
> >>>> + #address-cells = <1>;
> >>>> + #size-cells = <0>;
> >>>> +
> >>>> + port@0 {
> >>>> + reg = <0>;
> >>>> + dual-lvds-odd-pixels;
> >>>> +
> >>>> + it6263_lvds_link1_dual: endpoint {
> >>>> + remote-endpoint = <&ldb_lvds_ch0>;
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + port@1 {
> >>>> + reg = <1>;
> >>>> + dual-lvds-even-pixels;
> >>>> +
> >>>> + it6263_lvds_link2_dual: endpoint {
> >>>> + remote-endpoint = <&ldb_lvds_ch1>;
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + port@2 {
> >>>> + reg = <2>;
> >>>> +
> >>>> + it6263_out_dual: endpoint {
> >>>> + remote-endpoint = <&hdmi_in>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> --
> >>>> 2.34.1
> >>>>
> >>>
> >>
> >> --
> >> Regards,
> >> Liu Ying
> >>
> >
>
> --
> Regards,
> Liu Ying
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-14 8:14 ` Biju Das
@ 2024-10-14 8:37 ` Liu Ying
0 siblings, 0 replies; 49+ messages in thread
From: Liu Ying @ 2024-10-14 8:37 UTC (permalink / raw)
To: Biju Das, Dmitry Baryshkov
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org, andrzej.hajda@intel.com,
neil.armstrong@linaro.org, rfoss@kernel.org, laurent.pinchart,
jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com,
simona@ffwll.ch, maarten.lankhorst@linux.intel.com,
mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com,
catalin.marinas@arm.com, will@kernel.org,
quic_bjorande@quicinc.com, geert+renesas@glider.be, arnd@arndb.de,
nfraprado@collabora.com, o.rempel@pengutronix.de,
y.moog@phytec.de, marex@denx.de, isaac.scott@ideasonboard.com
On 10/14/2024, Biju Das wrote:
> Hi Liu Ying,
Hi Biju,
>
>> -----Original Message-----
>> From: Liu Ying <victor.liu@nxp.com>
>> Sent: Monday, October 14, 2024 8:18 AM
>> Subject: Re: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
>>
>> On 10/14/2024, Dmitry Baryshkov wrote:
>>> On Sat, Oct 12, 2024 at 03:35:40PM +0800, Liu Ying wrote:
>>>> Add basic HDMI video output support. Currently, only RGB888 output
>>>> pixel format is supported. At the LVDS input side, the driver
>>>> supports single LVDS link and dual LVDS links with "jeida-24" LVDS
>>>> mapping.
>>>>
>>>> Product link:
>>>> https://www.ite.com.tw/en/product/cate1/IT6263
>>>>
>>>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
>>>> ---
>>>> v2:
>>>> * Add AVI inforframe support. (Maxime)
>>>> * Add DRM_MODE_CONNECTOR_HDMIA. (Biju)
>>>> * Rename it6263_reset() to it6263_hw_reset(). (Biju)
>>>> * Check number of LVDS link data lanes. (Biju)
>>>>
>>>> drivers/gpu/drm/bridge/Kconfig | 8 +
>>>> drivers/gpu/drm/bridge/Makefile | 1 +
>>>> drivers/gpu/drm/bridge/ite-it6263.c | 919
>>>> ++++++++++++++++++++++++++++
>>>> 3 files changed, 928 insertions(+)
>>>> create mode 100644 drivers/gpu/drm/bridge/ite-it6263.c
>>>>
>>>
>>> [...]
>>>
>>>> +static int it6263_parse_dt(struct it6263 *it) {
>>>> + struct device *dev = it->dev;
>>>> + struct device_node *port0, *port1;
>>>> + int ret;
>>>> +
>>>> + ret = of_property_read_u8(dev->of_node, "ite,lvds-link-num-data-lanes",
>>>> + &it->lvds_link_num_dlanes);
>>>> + if (ret) {
>>>> + dev_err(dev, "failed to get LVDS link number of data lanes: %d\n",
>>>> + ret);
>>>> + return ret;
>>>> + }
>>>> +
>>>> + it->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0);
>>>> + if (IS_ERR(it->next_bridge))
>>>> + return dev_err_probe(dev, PTR_ERR(it->next_bridge),
>>>> + "failed to get next bridge\n");
>>>> +
>>>> + port0 = of_graph_get_port_by_id(dev->of_node, 0);
>>>> + port1 = of_graph_get_port_by_id(dev->of_node, 1);
>>>> + if (port0 && port1) {
>>>> + if (of_property_read_bool(port0, "dual-lvds-even-pixels") &&
>>>> + of_property_read_bool(port1, "dual-lvds-odd-pixels")) {
>>>> + it->lvds_dual_link = true;
>>>> + it->lvds_link12_swap = true;
>>>> + } else if (of_property_read_bool(port0, "dual-lvds-odd-pixels") &&
>>>> + of_property_read_bool(port1, "dual-lvds-even-pixels")) {
>>>> + it->lvds_dual_link = true;
>>>> + }
>>>> +
>>>> + if (!it->lvds_dual_link) {
>>>> + dev_err(dev,
>>>> + "failed to get LVDS dual link pixel order\n");
>>>> + ret = -EINVAL;
>>>> + }
>>>
>>> Please use drm_of_lvds_get_dual_link_pixel_order(), it validates that
>>> the DT definition is sound: one port for odd pixels, one port for even
>>> pixels.
>>
>> It cannot be used, because it get the pixel order for the LVDS source not sink. IT6263 is the LVDS
>> sink.
>>
>> * drm_of_lvds_get_dual_link_pixel_order - Get LVDS dual-link pixel order
>> * @port1: First DT port node of the Dual-link LVDS source
>> * @port2: Second DT port node of the Dual-link LVDS source
>
>
> Can't you use drm_of_lvds_get_dual_link_pixel_order() from host for the same use case. See [1]?
Yes, just need to get the remote LVDS source ports first.
I just proposed a snippet in a separate reply to use this function.
Let's see if Dmitry likes it or not.
>
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c?h=next-20241011
>
> lvds_bridge0: lvds-to-hdmi-bridge@4c {
> compatible = "ite,it6263";
> reg = <0x4c>;
> ports {
> #address-cells = <1>;
> #size-cells = <0>;
>
> port@0 {
> reg = <0>;
> dual-lvds-odd-pixels;
> lvds0_in0: endpoint@0 {
> remote-endpoint = <&lvds0_out>;
> };
> };
>
> port@1 {
> reg = <1>;
> dual-lvds-even-pixels;
> lvds0_in1: endpoint@1 {
> remote-endpoint = <&lvds1_out>;
> };
> };
>
> port@2 {
> reg = <2>;
> it6263_out: endpoint@2 {
> remote-endpoint = <&lvds_to_hdmi_con_out>;
> };
> };
> };
> };
> };
>
> Cheers,
> Biju
>
>
>>
>>>
>>>> + } else if (port1) {
>>>> + ret = -EINVAL;
>>>> + dev_err(dev, "single input LVDS port1 is not supported\n");
>>>> + } else if (!port0) {
>>>> + ret = -EINVAL;
>>>> + dev_err(dev, "no input LVDS port\n");
>>>> + }
>>>> +
>>>> + of_node_put(port0);
>>>> + of_node_put(port1);
>>>> +
>>>> + return ret;
>>>> +}
>>>> +
>>>
>>
>> --
>> Regards,
>> Liu Ying
>
--
Regards,
Liu Ying
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-14 7:07 ` Dmitry Baryshkov
@ 2024-10-14 10:01 ` Liu Ying
2024-10-14 11:15 ` Dmitry Baryshkov
2024-10-15 18:58 ` Rob Herring
2024-10-15 6:28 ` Liu Ying
1 sibling, 2 replies; 49+ messages in thread
From: Liu Ying @ 2024-10-14 10:01 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel,
andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
arnd, nfraprado, o.rempel, y.moog, marex, isaac.scott,
biju.das.jz
On 10/14/2024, Dmitry Baryshkov wrote:
[...]
>>>>> My suggestion would be to add a single root-level property which
>>>>> specifies which port provides even pixel data.
>>>>
>>>> That won't work. The LVDS source side expects the ports of
>>>> the sink side specify dual-lvds-{odd,even}-pixels properties.
>>>
>>> I didn't notice that these properties are already defined.
>>>
>>> As these properties are common between several schema files, please
>>> extract them to a common schema file (like lvds.yaml).
>>
>> I'm not sure how to do that. Is it obvious?
>> Please shed some light.
>>
>> Only two panel schema files are defining even/odd pixels now -
>> advantech,idk-2121wr.yaml and panel-simple-lvds-dual-ports.yaml.
>> Maybe, extract them later when more schema files(especially for
>> bridges) try to define the same? I'd like to keep a low profile
>> for now.
>
> I'd say, please extract those now. Adding third is more than enough and
> should be avoided. Extracting is pretty simple. One patch to move the
> definition and descriptions from panel-simple-lvds-dual-ports to a
> common location (e.g. lvds-dual-ports.yaml). Leave the required
> constrains in place. Second patch is to add oneOf constraints to the
> ports.
oneOf just sits below ports so that single-port and dual-port
are documented separately? That won't pass dt_binding_check
as the v1 binding has proved that warnings will be generated.
> port@0 might get the same oneOf + the
> dual-lvds-{odd,even}-pixels:false case, allowing a single-port
> definition.
I don't catch this.
Below snippet is a draft lvds-dual-port.yaml.
How can it be referenced in ite,it6263.yaml?
---8<---
allOf:
- $ref: lvds.yaml#
properties:
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: the first LVDS input link
properties:
dual-lvds-odd-pixels:
type: boolean
description: the first sink port for odd pixels
dual-lvds-even-pixels:
type: boolean
description: the first sink port for even pixels
oneOf:
- required: [dual-lvds-even-pixels]
- required: [dual-lvds-odd-pixels]
port@1:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: the second LVDS input link
properties:
dual-lvds-even-pixels:
type: boolean
description: the second sink port for even pixels
dual-lvds-odd-pixels:
type: boolean
description: the second sink port for odd pixels
oneOf:
- required: [dual-lvds-even-pixels]
- required: [dual-lvds-odd-pixels]
required:
- port@0
- port@1
unevaluatedProperties: false
---8<---
--
Regards,
Liu Ying
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-14 10:01 ` Liu Ying
@ 2024-10-14 11:15 ` Dmitry Baryshkov
2024-10-15 18:58 ` Rob Herring
1 sibling, 0 replies; 49+ messages in thread
From: Dmitry Baryshkov @ 2024-10-14 11:15 UTC (permalink / raw)
To: Liu Ying
Cc: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel,
andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
arnd, nfraprado, o.rempel, y.moog, marex, isaac.scott,
biju.das.jz
On Mon, Oct 14, 2024 at 06:01:49PM +0800, Liu Ying wrote:
> On 10/14/2024, Dmitry Baryshkov wrote:
>
> [...]
>
> >>>>> My suggestion would be to add a single root-level property which
> >>>>> specifies which port provides even pixel data.
> >>>>
> >>>> That won't work. The LVDS source side expects the ports of
> >>>> the sink side specify dual-lvds-{odd,even}-pixels properties.
> >>>
> >>> I didn't notice that these properties are already defined.
> >>>
> >>> As these properties are common between several schema files, please
> >>> extract them to a common schema file (like lvds.yaml).
> >>
> >> I'm not sure how to do that. Is it obvious?
> >> Please shed some light.
> >>
> >> Only two panel schema files are defining even/odd pixels now -
> >> advantech,idk-2121wr.yaml and panel-simple-lvds-dual-ports.yaml.
> >> Maybe, extract them later when more schema files(especially for
> >> bridges) try to define the same? I'd like to keep a low profile
> >> for now.
> >
> > I'd say, please extract those now. Adding third is more than enough and
> > should be avoided. Extracting is pretty simple. One patch to move the
> > definition and descriptions from panel-simple-lvds-dual-ports to a
> > common location (e.g. lvds-dual-ports.yaml). Leave the required
> > constrains in place. Second patch is to add oneOf constraints to the
> > ports.
>
> oneOf just sits below ports so that single-port and dual-port
> are documented separately? That won't pass dt_binding_check
> as the v1 binding has proved that warnings will be generated.
>
> > port@0 might get the same oneOf + the
> > dual-lvds-{odd,even}-pixels:false case, allowing a single-port
> > definition.
>
> I don't catch this.
> Below snippet is a draft lvds-dual-port.yaml.
> How can it be referenced in ite,it6263.yaml?
allOf:
- $ref: /schemas/display/lvds-dual-port.yaml
Another option might be to use $defs, define two combinations:
single-or-dual-port, dual-only-port. Reference them from the panel
bindings and from your bridge bindings by using:
ports:
port@0:
$ref: /schemas/display/lvds.yaml#/#defs/single-or-dual-port
port@1:
$ref: /schemas/display/lvds.yaml#/#defs/dual-only-port
(the names are just an example, feel free to come with better
suggestions).
>
> ---8<---
> allOf:
> - $ref: lvds.yaml#
>
> properties:
> ports:
> $ref: /schemas/graph.yaml#/properties/ports
>
> properties:
> port@0:
> $ref: /schemas/graph.yaml#/$defs/port-base
> unevaluatedProperties: false
> description: the first LVDS input link
>
> properties:
> dual-lvds-odd-pixels:
> type: boolean
> description: the first sink port for odd pixels
>
> dual-lvds-even-pixels:
> type: boolean
> description: the first sink port for even pixels
>
> oneOf:
> - required: [dual-lvds-even-pixels]
> - required: [dual-lvds-odd-pixels]
Also under oneOf:
- properties:
dual-lvds-odd-pixels: false
dual-lvds-even-pixels: false
>
> port@1:
> $ref: /schemas/graph.yaml#/$defs/port-base
> unevaluatedProperties: false
> description: the second LVDS input link
>
> properties:
> dual-lvds-even-pixels:
> type: boolean
> description: the second sink port for even pixels
>
> dual-lvds-odd-pixels:
> type: boolean
> description: the second sink port for odd pixels
>
> oneOf:
> - required: [dual-lvds-even-pixels]
> - required: [dual-lvds-odd-pixels]
>
> required:
> - port@0
> - port@1
You allow both single-port and dual-port configurations, so you can not
use this required statement. Please keep this part in the corresponding
panel bindings.
>
> unevaluatedProperties: false
> ---8<---
>
> --
> Regards,
> Liu Ying
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-14 8:09 ` Biju Das
@ 2024-10-14 11:16 ` Dmitry Baryshkov
2024-10-14 11:25 ` Biju Das
0 siblings, 1 reply; 49+ messages in thread
From: Dmitry Baryshkov @ 2024-10-14 11:16 UTC (permalink / raw)
To: Biju Das
Cc: Liu Ying, dri-devel@lists.freedesktop.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
andrzej.hajda@intel.com, neil.armstrong@linaro.org,
rfoss@kernel.org, laurent.pinchart, jonas@kwiboo.se,
jernej.skrabec@gmail.com, airlied@gmail.com, simona@ffwll.ch,
maarten.lankhorst@linux.intel.com, mripard@kernel.org,
tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com,
catalin.marinas@arm.com, will@kernel.org,
quic_bjorande@quicinc.com, geert+renesas@glider.be, arnd@arndb.de,
nfraprado@collabora.com, o.rempel@pengutronix.de,
y.moog@phytec.de, marex@denx.de, isaac.scott@ideasonboard.com
On Mon, Oct 14, 2024 at 08:09:44AM +0000, Biju Das wrote:
> Hi Dmitry,
>
> > -----Original Message-----
> > From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > Sent: Monday, October 14, 2024 9:04 AM
> > Subject: Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
> >
> > On Mon, Oct 14, 2024 at 07:39:16AM +0000, Biju Das wrote:
> > > Hi Liu and Dmitry,
> > >
> > > > -----Original Message-----
> > > > From: Liu Ying <victor.liu@nxp.com>
> > > > Sent: Monday, October 14, 2024 6:34 AM
> > > > Subject: Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE
> > > > IT6263 LVDS to HDMI converter
> > > >
> > > > On 10/14/2024, Dmitry Baryshkov wrote:
> > > > > On Sat, Oct 12, 2024 at 05:14:13PM +0800, Liu Ying wrote:
> > > > >> On 10/12/2024, Dmitry Baryshkov wrote:
> > > > >>> On Sat, Oct 12, 2024 at 03:35:39PM +0800, Liu Ying wrote:
> > > > >>>> Document ITE IT6263 LVDS to HDMI converter.
> > > > >>>>
> > > > >>>> Product link:
> > > > >>>> https://www.ite.com.tw/en/product/cate1/IT6263
> > > > >>>>
> > > > >>>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> > > > >>>> ---
> > > > >>>> v2:
> > > > >>>> * Document number of LVDS link data lanes. (Biju)
> > > > >>>> * Simplify ports property by dropping "oneOf". (Rob)
> > > > >>>>
> > > > >>>> .../bindings/display/bridge/ite,it6263.yaml | 276 ++++++++++++++++++
> > > > >>>> 1 file changed, 276 insertions(+) create mode 100644
> > > > >>>> Documentation/devicetree/bindings/display/bridge/ite,it6263.yam
> > > > >>>> l
> > > > >>>>
> > > > >>>> diff --git
> > > > >>>> a/Documentation/devicetree/bindings/display/bridge/ite,it6263.y
> > > > >>>> aml
> > > > >>>> b/Documentation/devicetree/bindings/display/bridge/ite,it6263.y
> > > > >>>> aml
> > > > >>>> new file mode 100644
> > > > >>>> index 000000000000..bc2bbec07623
> > > > >>>> --- /dev/null
> > > > >>>> +++ b/Documentation/devicetree/bindings/display/bridge/ite,it62
> > > > >>>> +++ 63.y
> > > > >>>> +++ aml
> > > > >>>> @@ -0,0 +1,276 @@
> > > > >>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > >>>> +%YAML
> > > > >>>> +1.2
> > > > >>>> +---
> > > > >>>> +$id:
> > > > >>>> +http://devicetree.org/schemas/display/bridge/ite,it6263.yaml#
> > > > >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > >>>> +
> > > > >>>> +title: ITE IT6263 LVDS to HDMI converter
> > > > >>>> +
> > > > >>>> +maintainers:
> > > > >>>> + - Liu Ying <victor.liu@nxp.com>
> > > > >>>> +
> > > > >>>> +description: |
> > > > >>>> + The IT6263 is a high-performance single-chip
> > > > >>>> +De-SSC(De-Spread
> > > > >>>> +Spectrum) LVDS
> > > > >>>> + to HDMI converter. Combined with LVDS receiver and HDMI
> > > > >>>> +1.4a transmitter,
> > > > >>>> + the IT6263 supports LVDS input and HDMI 1.4 output by conversion function.
> > > > >>>> + The built-in LVDS receiver can support single-link and
> > > > >>>> +dual-link LVDS inputs,
> > > > >>>> + and the built-in HDMI transmitter is fully compliant with
> > > > >>>> +HDMI 1.4a/3D, HDCP
> > > > >>>> + 1.2 and backward compatible with DVI 1.0 specification.
> > > > >>>> +
> > > > >>>> + The IT6263 also encodes and transmits up to 8 channels of
> > > > >>>> + I2S digital audio, with sampling rate up to 192KHz and
> > > > >>>> + sample size up to 24 bits. In addition, an S/PDIF input port
> > > > >>>> + takes in compressed audio of up to 192KHz
> > > > frame rate.
> > > > >>>> +
> > > > >>>> + The newly supported High-Bit Rate(HBR) audio by HDMI
> > > > >>>> + specifications v1.3 is provided by the IT6263 in two interfaces:
> > > > >>>> + the four I2S input ports or the S/PDIF input port. With
> > > > >>>> + both interfaces the highest possible HBR frame rate is supported at up to 768KHz.
> > > > >>>> +
> > > > >>>> +properties:
> > > > >>>
> > > > >>> No LVDS data-mapping support?
> > > > >>
> > > > >> It is enough to document number of LVDS link data lanes because
> > > > >> OS should be able to determine the data-mapping by looking at the
> > > > >> number and the data-mapping capability of the other side of the LVDS link.
> > > > >
> > > > > From what I can see, data-mapping is specified on the consumer
> > > > > sink side of the LVDS link. This means it should go to the bridge's device node.
> > > >
> > > > Then, I won't define data-lanes, because data-mapping implies it,
> > > > e.g., jeida-24 implies data lanes 0/1/2/3, see lvds-data-mapping.yaml.
> > > >
> > > > Please let me know which one you prefer.
> > >
> > > Assume a top level use case where a user changes the format from JEDAI
> > > to VESA using On screen display or modetest(if some one adds support
> > > for lvds-mapping) then setting of the lvds data mapping should be dynamic.
> > >
> > > Maybe for initial version hardcode with JEDAI or VESA as default and
> > > provide a way to override the host driver and bridge with requested lvds-data mapping dynamically
> > later??
> >
> > The ite,lvds-link-num-data-lanes property should be removed, it is not standard. I foresee two ways to
> > specify the number of lanes used: either the data-lanes property or the data-mapping property. Granted
> > that data-mapping replaces the data-lanes functionality for LVDS links, I think it's better to use it
> > from the start.
> >
> > Frankly speaking, what is the usecase for specifying the data mapping dynamically? What kind of uAPI
> > do you have in mind and what is the usecase for it?
>
> It simple just want to change from VESA to JEDAI, how do you change it with existing DRM framework?
Why do you want to change it on the fly?
> Currently I see LVDS panel driver use drm_of_lvds_get_data_mapping(bus_node) to get this info.
> IT6263 bridge device can use that API to get that info.
>
> Some vendors use VESA as default LVDS data mapping whereas some others use JEDAI.
I think this is logical. Bus format is set by the system design
constraints. In theory one can use buf format negotiation for the same
purpose.
>
> Cheers,
> Biju
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-14 8:28 ` Liu Ying
@ 2024-10-14 11:22 ` Dmitry Baryshkov
0 siblings, 0 replies; 49+ messages in thread
From: Dmitry Baryshkov @ 2024-10-14 11:22 UTC (permalink / raw)
To: Liu Ying
Cc: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel,
andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
arnd, nfraprado, o.rempel, y.moog, marex, isaac.scott,
biju.das.jz
On Mon, Oct 14, 2024 at 04:28:29PM +0800, Liu Ying wrote:
> On 10/14/2024, Dmitry Baryshkov wrote:
> > On Mon, Oct 14, 2024 at 03:18:15PM +0800, Liu Ying wrote:
> >> On 10/14/2024, Dmitry Baryshkov wrote:
> >>> On Sat, Oct 12, 2024 at 03:35:40PM +0800, Liu Ying wrote:
> >>>> Add basic HDMI video output support. Currently, only RGB888 output
> >>>> pixel format is supported. At the LVDS input side, the driver
> >>>> supports single LVDS link and dual LVDS links with "jeida-24" LVDS
> >>>> mapping.
> >>>>
> >>>> Product link:
> >>>> https://www.ite.com.tw/en/product/cate1/IT6263
> >>>>
> >>>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> >>>> ---
> >>>> v2:
> >>>> * Add AVI inforframe support. (Maxime)
> >>>> * Add DRM_MODE_CONNECTOR_HDMIA. (Biju)
> >>>> * Rename it6263_reset() to it6263_hw_reset(). (Biju)
> >>>> * Check number of LVDS link data lanes. (Biju)
> >>>>
> >>>> drivers/gpu/drm/bridge/Kconfig | 8 +
> >>>> drivers/gpu/drm/bridge/Makefile | 1 +
> >>>> drivers/gpu/drm/bridge/ite-it6263.c | 919 ++++++++++++++++++++++++++++
> >>>> 3 files changed, 928 insertions(+)
> >>>> create mode 100644 drivers/gpu/drm/bridge/ite-it6263.c
> >>>>
> >>>
> >>> [...]
> >>>
> >>>> +static int it6263_parse_dt(struct it6263 *it)
> >>>> +{
> >>>> + struct device *dev = it->dev;
> >>>> + struct device_node *port0, *port1;
> >>>> + int ret;
> >>>> +
> >>>> + ret = of_property_read_u8(dev->of_node, "ite,lvds-link-num-data-lanes",
> >>>> + &it->lvds_link_num_dlanes);
> >>>> + if (ret) {
> >>>> + dev_err(dev, "failed to get LVDS link number of data lanes: %d\n",
> >>>> + ret);
> >>>> + return ret;
> >>>> + }
> >>>> +
> >>>> + it->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0);
> >>>> + if (IS_ERR(it->next_bridge))
> >>>> + return dev_err_probe(dev, PTR_ERR(it->next_bridge),
> >>>> + "failed to get next bridge\n");
> >>>> +
> >>>> + port0 = of_graph_get_port_by_id(dev->of_node, 0);
> >>>> + port1 = of_graph_get_port_by_id(dev->of_node, 1);
> >>>> + if (port0 && port1) {
> >>>> + if (of_property_read_bool(port0, "dual-lvds-even-pixels") &&
> >>>> + of_property_read_bool(port1, "dual-lvds-odd-pixels")) {
> >>>> + it->lvds_dual_link = true;
> >>>> + it->lvds_link12_swap = true;
> >>>> + } else if (of_property_read_bool(port0, "dual-lvds-odd-pixels") &&
> >>>> + of_property_read_bool(port1, "dual-lvds-even-pixels")) {
> >>>> + it->lvds_dual_link = true;
> >>>> + }
> >>>> +
> >>>> + if (!it->lvds_dual_link) {
> >>>> + dev_err(dev,
> >>>> + "failed to get LVDS dual link pixel order\n");
> >>>> + ret = -EINVAL;
> >>>> + }
> >>>
> >>> Please use drm_of_lvds_get_dual_link_pixel_order(), it validates that
> >>> the DT definition is sound: one port for odd pixels, one port for even
> >>> pixels.
> >>
> >> It cannot be used, because it get the pixel order for the LVDS
> >> source not sink. IT6263 is the LVDS sink.
> >
> > Then you need a similar function for the sink side. Add it to the
> > drm_of.c
>
> How about getting remote LVDS source ports first and use
> drm_of_lvds_get_dual_link_pixel_order() like the snippet below?
> This way, no need to add a similar function or modify
> drm_of_lvds_get_dual_link_pixel_order() implementation.
>
> If you don't like this, can you please suggest a similar function
> name or maybe an additional parameter(with type and name) for
> drm_of_lvds_get_dual_link_pixel_order()?
>
> ---8<---
> port0_ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
> if (port0_ep) {
> remote_port0 = of_graph_get_remote_port(port0_ep);
> of_node_put(port0_ep);
> }
> port1_ep = of_graph_get_endpoint_by_regs(dev->of_node, 1, -1);
> if (port1_ep) {
> remote_port1 = of_graph_get_remote_port(port1_ep);
> of_node_put(port1_ep);
> }
I think getting remotes just to get remotes back is a little bit clumsy.
Adding drm_of_lvds_get_dual_link_pixel_order_sink() looks like a claner
solution.
>
> if (remote_port0 && remote_port1) {
> order = drm_of_lvds_get_dual_link_pixel_order(remote_port0,
> remote_port1);
> if (order < 0) {
> dev_err(dev,
> "failed to get dual link pixel order: %d\n",
> order);
> ret = order;
> } else if (order == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) {
> it->lvds_dual_link = true;
> } else if (order == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) {
> it->lvds_dual_link = true;
> it->lvds_link12_swap = true;
> }
it->lvds_dual_link = true;
order = drm_of_lvds_get_dual_link_pixel_order_sink(port0_ep,
port1_ep);
if (order < 0) {
dev_err(...);
ret = order;
} else if (order == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) {
it->lvds_link12_swap = true;
}
> } else if (remote_port1) {
> ret = -EINVAL;
> dev_err(dev, "single input LVDS port1 is not supported\n");
> } else if (!remote_port0) {
> ret = -EINVAL;
> dev_err(dev, "no input LVDS port\n");
> }
>
> of_node_put(remote_port0);
> of_node_put(remote_port1);
> ---8<---
>
> >
> >>
> >> * drm_of_lvds_get_dual_link_pixel_order - Get LVDS dual-link pixel order
> >> * @port1: First DT port node of the Dual-link LVDS source
> >> * @port2: Second DT port node of the Dual-link LVDS source
> >>
> >>>
> >>>> + } else if (port1) {
> >>>> + ret = -EINVAL;
> >>>> + dev_err(dev, "single input LVDS port1 is not supported\n");
> >>>> + } else if (!port0) {
> >>>> + ret = -EINVAL;
> >>>> + dev_err(dev, "no input LVDS port\n");
> >>>> + }
> >>>> +
> >>>> + of_node_put(port0);
> >>>> + of_node_put(port1);
> >>>> +
> >>>> + return ret;
> >>>> +}
> >>>> +
> >>>
> >>
> >> --
> >> Regards,
> >> Liu Ying
> >>
> >
>
> --
> Regards,
> Liu Ying
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 49+ messages in thread
* RE: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-14 11:16 ` Dmitry Baryshkov
@ 2024-10-14 11:25 ` Biju Das
2024-10-14 11:36 ` Dmitry Baryshkov
0 siblings, 1 reply; 49+ messages in thread
From: Biju Das @ 2024-10-14 11:25 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Liu Ying, dri-devel@lists.freedesktop.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
andrzej.hajda@intel.com, neil.armstrong@linaro.org,
rfoss@kernel.org, laurent.pinchart, jonas@kwiboo.se,
jernej.skrabec@gmail.com, airlied@gmail.com, simona@ffwll.ch,
maarten.lankhorst@linux.intel.com, mripard@kernel.org,
tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com,
catalin.marinas@arm.com, will@kernel.org,
quic_bjorande@quicinc.com, geert+renesas@glider.be, arnd@arndb.de,
nfraprado@collabora.com, o.rempel@pengutronix.de,
y.moog@phytec.de, marex@denx.de, isaac.scott@ideasonboard.com
Hi Dmitry,
> -----Original Message-----
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Sent: Monday, October 14, 2024 12:16 PM
> Subject: Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
>
> On Mon, Oct 14, 2024 at 08:09:44AM +0000, Biju Das wrote:
> > Hi Dmitry,
> >
> > > -----Original Message-----
> > > From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > > Sent: Monday, October 14, 2024 9:04 AM
> > > Subject: Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE
> > > IT6263 LVDS to HDMI converter
> > >
> > > On Mon, Oct 14, 2024 at 07:39:16AM +0000, Biju Das wrote:
> > > > Hi Liu and Dmitry,
> > > >
> > > > > -----Original Message-----
> > > > > From: Liu Ying <victor.liu@nxp.com>
> > > > > Sent: Monday, October 14, 2024 6:34 AM
> > > > > Subject: Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add
> > > > > ITE
> > > > > IT6263 LVDS to HDMI converter
> > > > >
> > > > > On 10/14/2024, Dmitry Baryshkov wrote:
> > > > > > On Sat, Oct 12, 2024 at 05:14:13PM +0800, Liu Ying wrote:
> > > > > >> On 10/12/2024, Dmitry Baryshkov wrote:
> > > > > >>> On Sat, Oct 12, 2024 at 03:35:39PM +0800, Liu Ying wrote:
> > > > > >>>> Document ITE IT6263 LVDS to HDMI converter.
> > > > > >>>>
> > > > > >>>> Product link:
> > > > > >>>> https://www.ite.com.tw/en/product/cate1/IT6263
> > > > > >>>>
> > > > > >>>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> > > > > >>>> ---
> > > > > >>>> v2:
> > > > > >>>> * Document number of LVDS link data lanes. (Biju)
> > > > > >>>> * Simplify ports property by dropping "oneOf". (Rob)
> > > > > >>>>
> > > > > >>>> .../bindings/display/bridge/ite,it6263.yaml | 276 ++++++++++++++++++
> > > > > >>>> 1 file changed, 276 insertions(+) create mode 100644
> > > > > >>>> Documentation/devicetree/bindings/display/bridge/ite,it6263
> > > > > >>>> .yam
> > > > > >>>> l
> > > > > >>>>
> > > > > >>>> diff --git
> > > > > >>>> a/Documentation/devicetree/bindings/display/bridge/ite,it62
> > > > > >>>> 63.y
> > > > > >>>> aml
> > > > > >>>> b/Documentation/devicetree/bindings/display/bridge/ite,it62
> > > > > >>>> 63.y
> > > > > >>>> aml
> > > > > >>>> new file mode 100644
> > > > > >>>> index 000000000000..bc2bbec07623
> > > > > >>>> --- /dev/null
> > > > > >>>> +++ b/Documentation/devicetree/bindings/display/bridge/ite,
> > > > > >>>> +++ it62
> > > > > >>>> +++ 63.y
> > > > > >>>> +++ aml
> > > > > >>>> @@ -0,0 +1,276 @@
> > > > > >>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > >>>> +%YAML
> > > > > >>>> +1.2
> > > > > >>>> +---
> > > > > >>>> +$id:
> > > > > >>>> +http://devicetree.org/schemas/display/bridge/ite,it6263.ya
> > > > > >>>> +ml#
> > > > > >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > > >>>> +
> > > > > >>>> +title: ITE IT6263 LVDS to HDMI converter
> > > > > >>>> +
> > > > > >>>> +maintainers:
> > > > > >>>> + - Liu Ying <victor.liu@nxp.com>
> > > > > >>>> +
> > > > > >>>> +description: |
> > > > > >>>> + The IT6263 is a high-performance single-chip
> > > > > >>>> +De-SSC(De-Spread
> > > > > >>>> +Spectrum) LVDS
> > > > > >>>> + to HDMI converter. Combined with LVDS receiver and HDMI
> > > > > >>>> +1.4a transmitter,
> > > > > >>>> + the IT6263 supports LVDS input and HDMI 1.4 output by conversion function.
> > > > > >>>> + The built-in LVDS receiver can support single-link and
> > > > > >>>> +dual-link LVDS inputs,
> > > > > >>>> + and the built-in HDMI transmitter is fully compliant
> > > > > >>>> +with HDMI 1.4a/3D, HDCP
> > > > > >>>> + 1.2 and backward compatible with DVI 1.0 specification.
> > > > > >>>> +
> > > > > >>>> + The IT6263 also encodes and transmits up to 8 channels
> > > > > >>>> + of I2S digital audio, with sampling rate up to 192KHz
> > > > > >>>> + and sample size up to 24 bits. In addition, an S/PDIF
> > > > > >>>> + input port takes in compressed audio of up to 192KHz
> > > > > frame rate.
> > > > > >>>> +
> > > > > >>>> + The newly supported High-Bit Rate(HBR) audio by HDMI
> > > > > >>>> + specifications v1.3 is provided by the IT6263 in two interfaces:
> > > > > >>>> + the four I2S input ports or the S/PDIF input port. With
> > > > > >>>> + both interfaces the highest possible HBR frame rate is supported at up to 768KHz.
> > > > > >>>> +
> > > > > >>>> +properties:
> > > > > >>>
> > > > > >>> No LVDS data-mapping support?
> > > > > >>
> > > > > >> It is enough to document number of LVDS link data lanes
> > > > > >> because OS should be able to determine the data-mapping by
> > > > > >> looking at the number and the data-mapping capability of the other side of the LVDS link.
> > > > > >
> > > > > > From what I can see, data-mapping is specified on the consumer
> > > > > > sink side of the LVDS link. This means it should go to the bridge's device node.
> > > > >
> > > > > Then, I won't define data-lanes, because data-mapping implies
> > > > > it, e.g., jeida-24 implies data lanes 0/1/2/3, see lvds-data-mapping.yaml.
> > > > >
> > > > > Please let me know which one you prefer.
> > > >
> > > > Assume a top level use case where a user changes the format from
> > > > JEDAI to VESA using On screen display or modetest(if some one adds
> > > > support for lvds-mapping) then setting of the lvds data mapping should be dynamic.
> > > >
> > > > Maybe for initial version hardcode with JEDAI or VESA as default
> > > > and provide a way to override the host driver and bridge with
> > > > requested lvds-data mapping dynamically
> > > later??
> > >
> > > The ite,lvds-link-num-data-lanes property should be removed, it is
> > > not standard. I foresee two ways to specify the number of lanes
> > > used: either the data-lanes property or the data-mapping property.
> > > Granted that data-mapping replaces the data-lanes functionality for LVDS links, I think it's
> better to use it from the start.
> > >
> > > Frankly speaking, what is the usecase for specifying the data
> > > mapping dynamically? What kind of uAPI do you have in mind and what is the usecase for it?
> >
> > It simple just want to change from VESA to JEDAI, how do you change it with existing DRM framework?
>
> Why do you want to change it on the fly?
It will reduce validation effort for LVDS and bridge driver for testing various bus formats.
By allowing on the fly, with single dtb, we can validate various bus formats.
Otherwise each dtb for testing each bus format.
From a product perspective, this use case is not valid.
Cheers,
Biju
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-14 11:25 ` Biju Das
@ 2024-10-14 11:36 ` Dmitry Baryshkov
0 siblings, 0 replies; 49+ messages in thread
From: Dmitry Baryshkov @ 2024-10-14 11:36 UTC (permalink / raw)
To: Biju Das
Cc: Liu Ying, dri-devel@lists.freedesktop.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
andrzej.hajda@intel.com, neil.armstrong@linaro.org,
rfoss@kernel.org, laurent.pinchart, jonas@kwiboo.se,
jernej.skrabec@gmail.com, airlied@gmail.com, simona@ffwll.ch,
maarten.lankhorst@linux.intel.com, mripard@kernel.org,
tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com,
catalin.marinas@arm.com, will@kernel.org,
quic_bjorande@quicinc.com, geert+renesas@glider.be, arnd@arndb.de,
nfraprado@collabora.com, o.rempel@pengutronix.de,
y.moog@phytec.de, marex@denx.de, isaac.scott@ideasonboard.com
On Mon, Oct 14, 2024 at 11:25:00AM +0000, Biju Das wrote:
> Hi Dmitry,
>
> > -----Original Message-----
> > From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > Sent: Monday, October 14, 2024 12:16 PM
> > Subject: Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
> >
> > On Mon, Oct 14, 2024 at 08:09:44AM +0000, Biju Das wrote:
> > > Hi Dmitry,
> > >
> > > > -----Original Message-----
> > > > From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > > > Sent: Monday, October 14, 2024 9:04 AM
> > > > Subject: Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE
> > > > IT6263 LVDS to HDMI converter
> > > >
> > > > On Mon, Oct 14, 2024 at 07:39:16AM +0000, Biju Das wrote:
> > > > > Hi Liu and Dmitry,
> > > > >
> > > > > > -----Original Message-----
> > > > > > From: Liu Ying <victor.liu@nxp.com>
> > > > > > Sent: Monday, October 14, 2024 6:34 AM
> > > > > > Subject: Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add
> > > > > > ITE
> > > > > > IT6263 LVDS to HDMI converter
> > > > > >
> > > > > > On 10/14/2024, Dmitry Baryshkov wrote:
> > > > > > > On Sat, Oct 12, 2024 at 05:14:13PM +0800, Liu Ying wrote:
> > > > > > >> On 10/12/2024, Dmitry Baryshkov wrote:
> > > > > > >>> On Sat, Oct 12, 2024 at 03:35:39PM +0800, Liu Ying wrote:
> > > > > > >>>> Document ITE IT6263 LVDS to HDMI converter.
> > > > > > >>>>
> > > > > > >>>> Product link:
> > > > > > >>>> https://www.ite.com.tw/en/product/cate1/IT6263
> > > > > > >>>>
> > > > > > >>>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> > > > > > >>>> ---
> > > > > > >>>> v2:
> > > > > > >>>> * Document number of LVDS link data lanes. (Biju)
> > > > > > >>>> * Simplify ports property by dropping "oneOf". (Rob)
> > > > > > >>>>
> > > > > > >>>> .../bindings/display/bridge/ite,it6263.yaml | 276 ++++++++++++++++++
> > > > > > >>>> 1 file changed, 276 insertions(+) create mode 100644
> > > > > > >>>> Documentation/devicetree/bindings/display/bridge/ite,it6263
> > > > > > >>>> .yam
> > > > > > >>>> l
> > > > > > >>>>
> > > > > > >>>> diff --git
> > > > > > >>>> a/Documentation/devicetree/bindings/display/bridge/ite,it62
> > > > > > >>>> 63.y
> > > > > > >>>> aml
> > > > > > >>>> b/Documentation/devicetree/bindings/display/bridge/ite,it62
> > > > > > >>>> 63.y
> > > > > > >>>> aml
> > > > > > >>>> new file mode 100644
> > > > > > >>>> index 000000000000..bc2bbec07623
> > > > > > >>>> --- /dev/null
> > > > > > >>>> +++ b/Documentation/devicetree/bindings/display/bridge/ite,
> > > > > > >>>> +++ it62
> > > > > > >>>> +++ 63.y
> > > > > > >>>> +++ aml
> > > > > > >>>> @@ -0,0 +1,276 @@
> > > > > > >>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > > >>>> +%YAML
> > > > > > >>>> +1.2
> > > > > > >>>> +---
> > > > > > >>>> +$id:
> > > > > > >>>> +http://devicetree.org/schemas/display/bridge/ite,it6263.ya
> > > > > > >>>> +ml#
> > > > > > >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > > > >>>> +
> > > > > > >>>> +title: ITE IT6263 LVDS to HDMI converter
> > > > > > >>>> +
> > > > > > >>>> +maintainers:
> > > > > > >>>> + - Liu Ying <victor.liu@nxp.com>
> > > > > > >>>> +
> > > > > > >>>> +description: |
> > > > > > >>>> + The IT6263 is a high-performance single-chip
> > > > > > >>>> +De-SSC(De-Spread
> > > > > > >>>> +Spectrum) LVDS
> > > > > > >>>> + to HDMI converter. Combined with LVDS receiver and HDMI
> > > > > > >>>> +1.4a transmitter,
> > > > > > >>>> + the IT6263 supports LVDS input and HDMI 1.4 output by conversion function.
> > > > > > >>>> + The built-in LVDS receiver can support single-link and
> > > > > > >>>> +dual-link LVDS inputs,
> > > > > > >>>> + and the built-in HDMI transmitter is fully compliant
> > > > > > >>>> +with HDMI 1.4a/3D, HDCP
> > > > > > >>>> + 1.2 and backward compatible with DVI 1.0 specification.
> > > > > > >>>> +
> > > > > > >>>> + The IT6263 also encodes and transmits up to 8 channels
> > > > > > >>>> + of I2S digital audio, with sampling rate up to 192KHz
> > > > > > >>>> + and sample size up to 24 bits. In addition, an S/PDIF
> > > > > > >>>> + input port takes in compressed audio of up to 192KHz
> > > > > > frame rate.
> > > > > > >>>> +
> > > > > > >>>> + The newly supported High-Bit Rate(HBR) audio by HDMI
> > > > > > >>>> + specifications v1.3 is provided by the IT6263 in two interfaces:
> > > > > > >>>> + the four I2S input ports or the S/PDIF input port. With
> > > > > > >>>> + both interfaces the highest possible HBR frame rate is supported at up to 768KHz.
> > > > > > >>>> +
> > > > > > >>>> +properties:
> > > > > > >>>
> > > > > > >>> No LVDS data-mapping support?
> > > > > > >>
> > > > > > >> It is enough to document number of LVDS link data lanes
> > > > > > >> because OS should be able to determine the data-mapping by
> > > > > > >> looking at the number and the data-mapping capability of the other side of the LVDS link.
> > > > > > >
> > > > > > > From what I can see, data-mapping is specified on the consumer
> > > > > > > sink side of the LVDS link. This means it should go to the bridge's device node.
> > > > > >
> > > > > > Then, I won't define data-lanes, because data-mapping implies
> > > > > > it, e.g., jeida-24 implies data lanes 0/1/2/3, see lvds-data-mapping.yaml.
> > > > > >
> > > > > > Please let me know which one you prefer.
> > > > >
> > > > > Assume a top level use case where a user changes the format from
> > > > > JEDAI to VESA using On screen display or modetest(if some one adds
> > > > > support for lvds-mapping) then setting of the lvds data mapping should be dynamic.
> > > > >
> > > > > Maybe for initial version hardcode with JEDAI or VESA as default
> > > > > and provide a way to override the host driver and bridge with
> > > > > requested lvds-data mapping dynamically
> > > > later??
> > > >
> > > > The ite,lvds-link-num-data-lanes property should be removed, it is
> > > > not standard. I foresee two ways to specify the number of lanes
> > > > used: either the data-lanes property or the data-mapping property.
> > > > Granted that data-mapping replaces the data-lanes functionality for LVDS links, I think it's
> > better to use it from the start.
> > > >
> > > > Frankly speaking, what is the usecase for specifying the data
> > > > mapping dynamically? What kind of uAPI do you have in mind and what is the usecase for it?
> > >
> > > It simple just want to change from VESA to JEDAI, how do you change it with existing DRM framework?
> >
> > Why do you want to change it on the fly?
>
> It will reduce validation effort for LVDS and bridge driver for testing various bus formats.
>
> By allowing on the fly, with single dtb, we can validate various bus formats.
> Otherwise each dtb for testing each bus format.
I see your point, but I don't think it falls into the uAPI area. Feel
free to propose a mechanism to change data-mapping through the debugfs
though. I think that's the best possible option.
>
> From a product perspective, this use case is not valid.
>
> Cheers,
> Biju
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-12 7:35 ` [PATCH v2 6/9] drm/bridge: " Liu Ying
2024-10-12 8:45 ` Dmitry Baryshkov
2024-10-14 7:10 ` Dmitry Baryshkov
@ 2024-10-15 4:54 ` kernel test robot
2 siblings, 0 replies; 49+ messages in thread
From: kernel test robot @ 2024-10-15 4:54 UTC (permalink / raw)
To: Liu Ying, dri-devel, devicetree, linux-kernel, imx,
linux-arm-kernel
Cc: oe-kbuild-all, andrzej.hajda, neil.armstrong, rfoss,
Laurent.pinchart, jonas, jernej.skrabec, airlied, simona,
maarten.lankhorst, mripard, tzimmermann, robh, krzk+dt, conor+dt,
shawnguo, s.hauer, kernel, festevam, catalin.marinas, will,
quic_bjorande, geert+renesas, dmitry.baryshkov, arnd, nfraprado
Hi Liu,
kernel test robot noticed the following build warnings:
[auto build test WARNING on shawnguo/for-next]
[also build test WARNING on arm64/for-next/core drm/drm-next drm-exynos/exynos-drm-next drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm-misc/drm-misc-next drm-tip/drm-tip linus/master v6.12-rc3 next-20241014]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Liu-Ying/arm64-dts-imx8mp-skov-revb-mi1010ait-1cp1-Add-panel-timing-node-to-panel-node/20241012-154239
base: https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git for-next
patch link: https://lore.kernel.org/r/20241012073543.1388069-7-victor.liu%40nxp.com
patch subject: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
config: i386-randconfig-052-20241015 (https://download.01.org/0day-ci/archive/20241015/202410151230.DwfMNFO5-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202410151230.DwfMNFO5-lkp@intel.com/
cocci warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/bridge/ite-it6263.c:683:57-62: WARNING: conversion to bool not needed here
vim +683 drivers/gpu/drm/bridge/ite-it6263.c
655
656 static void
657 it6263_bridge_atomic_enable(struct drm_bridge *bridge,
658 struct drm_bridge_state *old_bridge_state)
659 {
660 struct drm_atomic_state *state = old_bridge_state->base.state;
661 struct it6263 *it = bridge_to_it6263(bridge);
662 const struct drm_crtc_state *crtc_state;
663 struct regmap *regmap = it->hdmi_regmap;
664 const struct drm_display_mode *mode;
665 struct drm_connector *connector;
666 bool is_stable = false;
667 struct drm_crtc *crtc;
668 unsigned int val;
669 bool pclk_high;
670 int i, ret;
671
672 connector = drm_atomic_get_new_connector_for_encoder(state,
673 bridge->encoder);
674 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
675 crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
676 mode = &crtc_state->adjusted_mode;
677
678 regmap_write(regmap, HDMI_REG_HDMI_MODE, TX_HDMI_MODE);
679
680 it6263_hdmi_avi_infoframe_configure(it, connector, mode);
681
682 /* HDMI AFE setup */
> 683 pclk_high = mode->clock > HIGH_PIXEL_CLOCK_KHZ ? true : false;
684 regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, AFE_DRV_RST);
685 if (pclk_high)
686 regmap_write(regmap, HDMI_REG_AFE_XP_CTRL,
687 AFE_XP_GAINBIT | AFE_XP_RESETB);
688 else
689 regmap_write(regmap, HDMI_REG_AFE_XP_CTRL,
690 AFE_XP_ER0 | AFE_XP_RESETB);
691 regmap_write(regmap, HDMI_REG_AFE_ISW_CTRL, 0x10);
692 if (pclk_high)
693 regmap_write(regmap, HDMI_REG_AFE_IP_CTRL,
694 AFE_IP_GAINBIT | AFE_IP_RESETB);
695 else
696 regmap_write(regmap, HDMI_REG_AFE_IP_CTRL,
697 AFE_IP_ER0 | AFE_IP_RESETB);
698
699 /* HDMI software video reset */
700 regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, SOFTV_RST);
701 fsleep(1000);
702 regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, 0);
703
704 /* reconfigure LVDS and retry several times in case video is instable */
705 for (i = 0; i < 3; i++) {
706 ret = regmap_read_poll_timeout(regmap, HDMI_REG_SYS_STATUS, val,
707 val & TXVIDSTABLE,
708 20000, 500000);
709 if (!ret) {
710 is_stable = true;
711 break;
712 }
713
714 it6263_lvds_config(it);
715 }
716
717 if (!is_stable)
718 dev_warn(it->dev, "failed to wait for video stable\n");
719
720 /* HDMI AFE reset release and power up */
721 regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, 0);
722
723 regmap_write_bits(regmap, HDMI_REG_GCP, AVMUTE, 0);
724
725 regmap_write(regmap, HDMI_REG_PKT_GENERAL_CTRL, ENABLE_PKT | REPEAT_PKT);
726 }
727
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-14 7:07 ` Dmitry Baryshkov
2024-10-14 10:01 ` Liu Ying
@ 2024-10-15 6:28 ` Liu Ying
2024-10-19 2:44 ` Dmitry Baryshkov
1 sibling, 1 reply; 49+ messages in thread
From: Liu Ying @ 2024-10-15 6:28 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel,
andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
arnd, nfraprado, o.rempel, y.moog, marex, isaac.scott,
biju.das.jz
On 10/14/2024, Dmitry Baryshkov wrote:
> On Mon, Oct 14, 2024 at 01:33:44PM +0800, Liu Ying wrote:
>> On 10/14/2024, Dmitry Baryshkov wrote:
>>> On Sat, Oct 12, 2024 at 05:14:13PM +0800, Liu Ying wrote:
>>>> On 10/12/2024, Dmitry Baryshkov wrote:
>>>>> On Sat, Oct 12, 2024 at 03:35:39PM +0800, Liu Ying wrote:
>>>>>> Document ITE IT6263 LVDS to HDMI converter.
>>>>>>
>>>>>> Product link:
>>>>>> https://www.ite.com.tw/en/product/cate1/IT6263
>>>>>>
>>>>>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
>>>>>> ---
>>>>>> v2:
>>>>>> * Document number of LVDS link data lanes. (Biju)
>>>>>> * Simplify ports property by dropping "oneOf". (Rob)
>>>>>>
>>>>>> .../bindings/display/bridge/ite,it6263.yaml | 276 ++++++++++++++++++
>>>>>> 1 file changed, 276 insertions(+)
>>>>>> create mode 100644 Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
>>>>>>
>>>>>> diff --git a/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
>>>>>> new file mode 100644
>>>>>> index 000000000000..bc2bbec07623
>>>>>> --- /dev/null
>>>>>> +++ b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
>>>>>> @@ -0,0 +1,276 @@
>>>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>>>> +%YAML 1.2
>>>>>> +---
>>>>>> +$id: http://devicetree.org/schemas/display/bridge/ite,it6263.yaml#
>>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>>> +
>>>>>> +title: ITE IT6263 LVDS to HDMI converter
>>>>>> +
>>>>>> +maintainers:
>>>>>> + - Liu Ying <victor.liu@nxp.com>
>>>>>> +
>>>>>> +description: |
>>>>>> + The IT6263 is a high-performance single-chip De-SSC(De-Spread Spectrum) LVDS
>>>>>> + to HDMI converter. Combined with LVDS receiver and HDMI 1.4a transmitter,
>>>>>> + the IT6263 supports LVDS input and HDMI 1.4 output by conversion function.
>>>>>> + The built-in LVDS receiver can support single-link and dual-link LVDS inputs,
>>>>>> + and the built-in HDMI transmitter is fully compliant with HDMI 1.4a/3D, HDCP
>>>>>> + 1.2 and backward compatible with DVI 1.0 specification.
>>>>>> +
>>>>>> + The IT6263 also encodes and transmits up to 8 channels of I2S digital audio,
>>>>>> + with sampling rate up to 192KHz and sample size up to 24 bits. In addition,
>>>>>> + an S/PDIF input port takes in compressed audio of up to 192KHz frame rate.
>>>>>> +
>>>>>> + The newly supported High-Bit Rate(HBR) audio by HDMI specifications v1.3 is
>>>>>> + provided by the IT6263 in two interfaces: the four I2S input ports or the
>>>>>> + S/PDIF input port. With both interfaces the highest possible HBR frame rate
>>>>>> + is supported at up to 768KHz.
>>>>>> +
>>>>>> +properties:
>>>>>
>>>>> No LVDS data-mapping support?
>>>>
>>>> It is enough to document number of LVDS link data lanes
>>>> because OS should be able to determine the data-mapping
>>>> by looking at the number and the data-mapping capability
>>>> of the other side of the LVDS link.
>>>
>>> From what I can see, data-mapping is specified on the consumer sink side
>>> of the LVDS link. This means it should go to the bridge's device node.
>>
>> Then, I won't define data-lanes, because data-mapping implies it,
>> e.g., jeida-24 implies data lanes 0/1/2/3, see lvds-data-mapping.yaml.
>>
>> Please let me know which one you prefer.
>
> I'd prefer data-mapping.
Before I go ahead to use it, I'd like to get confirmation that
it'll cover data mapping which supports 30-bit RGB pixel transmission,
because it is something supported by IT6263 as I mentioned in v1
dt-binding discussion. For now, data-mapping only supports jeida-18,
jeida-24 and vesa-24, see lvds-data-mapping.yaml. And, I'm not
sure the 30-bit data mappings specified in IT6263 datasheet are
standard or not.
Note that if we use data-lanes instead, then this is not a concern
from DT PoV, as data mapping can be inferred by OS.
--
Regards,
Liu Ying
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-14 10:01 ` Liu Ying
2024-10-14 11:15 ` Dmitry Baryshkov
@ 2024-10-15 18:58 ` Rob Herring
1 sibling, 0 replies; 49+ messages in thread
From: Rob Herring @ 2024-10-15 18:58 UTC (permalink / raw)
To: Liu Ying
Cc: Dmitry Baryshkov, dri-devel, devicetree, linux-kernel, imx,
linux-arm-kernel, andrzej.hajda, neil.armstrong, rfoss,
Laurent.pinchart, jonas, jernej.skrabec, airlied, simona,
maarten.lankhorst, mripard, tzimmermann, krzk+dt, conor+dt,
shawnguo, s.hauer, kernel, festevam, catalin.marinas, will,
quic_bjorande, geert+renesas, arnd, nfraprado, o.rempel, y.moog,
marex, isaac.scott, biju.das.jz
On Mon, Oct 14, 2024 at 5:01 AM Liu Ying <victor.liu@nxp.com> wrote:
>
> On 10/14/2024, Dmitry Baryshkov wrote:
>
> [...]
>
> >>>>> My suggestion would be to add a single root-level property which
> >>>>> specifies which port provides even pixel data.
> >>>>
> >>>> That won't work. The LVDS source side expects the ports of
> >>>> the sink side specify dual-lvds-{odd,even}-pixels properties.
> >>>
> >>> I didn't notice that these properties are already defined.
> >>>
> >>> As these properties are common between several schema files, please
> >>> extract them to a common schema file (like lvds.yaml).
> >>
> >> I'm not sure how to do that. Is it obvious?
> >> Please shed some light.
> >>
> >> Only two panel schema files are defining even/odd pixels now -
> >> advantech,idk-2121wr.yaml and panel-simple-lvds-dual-ports.yaml.
> >> Maybe, extract them later when more schema files(especially for
> >> bridges) try to define the same? I'd like to keep a low profile
> >> for now.
> >
> > I'd say, please extract those now. Adding third is more than enough and
> > should be avoided. Extracting is pretty simple. One patch to move the
> > definition and descriptions from panel-simple-lvds-dual-ports to a
> > common location (e.g. lvds-dual-ports.yaml). Leave the required
> > constrains in place. Second patch is to add oneOf constraints to the
> > ports.
>
> oneOf just sits below ports so that single-port and dual-port
> are documented separately? That won't pass dt_binding_check
> as the v1 binding has proved that warnings will be generated.
>
> > port@0 might get the same oneOf + the
> > dual-lvds-{odd,even}-pixels:false case, allowing a single-port
> > definition.
>
> I don't catch this.
> Below snippet is a draft lvds-dual-port.yaml.
Please make panel-simple-lvds-dual-ports.yaml use this.
> How can it be referenced in ite,it6263.yaml?
>
> ---8<---
> allOf:
> - $ref: lvds.yaml#
>
> properties:
> ports:
> $ref: /schemas/graph.yaml#/properties/ports
>
> properties:
> port@0:
> $ref: /schemas/graph.yaml#/$defs/port-base
> unevaluatedProperties: false
> description: the first LVDS input link
>
> properties:
> dual-lvds-odd-pixels:
> type: boolean
> description: the first sink port for odd pixels
>
> dual-lvds-even-pixels:
> type: boolean
> description: the first sink port for even pixels
>
> oneOf:
> - required: [dual-lvds-even-pixels]
> - required: [dual-lvds-odd-pixels]
>
> port@1:
> $ref: /schemas/graph.yaml#/$defs/port-base
> unevaluatedProperties: false
> description: the second LVDS input link
>
> properties:
> dual-lvds-even-pixels:
> type: boolean
> description: the second sink port for even pixels
>
> dual-lvds-odd-pixels:
> type: boolean
> description: the second sink port for odd pixels
>
> oneOf:
> - required: [dual-lvds-even-pixels]
> - required: [dual-lvds-odd-pixels]
>
> required:
> - port@0
> - port@1
>
> unevaluatedProperties: false
> ---8<---
>
> --
> Regards,
> Liu Ying
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-14 0:06 ` Dmitry Baryshkov
@ 2024-10-17 9:53 ` Liu Ying
0 siblings, 0 replies; 49+ messages in thread
From: Liu Ying @ 2024-10-17 9:53 UTC (permalink / raw)
To: Dmitry Baryshkov, Biju Das
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org, andrzej.hajda@intel.com,
neil.armstrong@linaro.org, rfoss@kernel.org, laurent.pinchart,
jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com,
simona@ffwll.ch, maarten.lankhorst@linux.intel.com,
mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com,
catalin.marinas@arm.com, will@kernel.org,
quic_bjorande@quicinc.com, geert+renesas@glider.be, arnd@arndb.de,
nfraprado@collabora.com, o.rempel@pengutronix.de,
y.moog@phytec.de, marex@denx.de, isaac.scott@ideasonboard.com
On 10/14/2024, Dmitry Baryshkov wrote:
[...]
>>>> +static int it6263_bridge_atomic_check(struct drm_bridge *bridge,
>>>> + struct drm_bridge_state *bridge_state,
>>>> + struct drm_crtc_state *crtc_state,
>>>> + struct drm_connector_state *conn_state) {
>>>> + struct drm_display_mode *mode = &crtc_state->adjusted_mode;
>>>
>>> Use drm_atomic_helper_connector_hdmi_check().
>>>
>>> Implement .hdmi_tmds_char_rate_valid(). Also, I think, single and dual link LVDS have different max
>>> clock rates. Please correct me if I'm wrong.
>>
>> I guess this rate will be same for both links in dual lvds mode.
>> For single link, it supports only link0.
>> We cannot operate link1 its Own.
>>
>> From ITE point the max rate is rate corresponding to 1080p(148-150MHz)
>>
>> single and dual link LVDS have different max clock rates, but that constraint is
>> in SoC side?? ITE HW manual does not mention about this.
>
> Huh? I checked the datasheet, version 0.8.
> It specifies LVDS clock rate (not the mode clock) up to 150 MHz and HDMI
The datasheet says "Features(LVDS RX) * Support input clock rate up to
150MHz". The 150MHz is the mode clock rate which kind of matches the
words "Features(Combined) * Support up to Full-HD/1080P and UXGA(1600x
1200) display format". LVDS serial clock rate is either x7 or x3.5
the mode clock rate, depending on single link or dual link.
> rate up to 225 MHz. Please check both constraints.
Will check both constraints.
[...]
>>>> + it->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT;
>>>
>>> | DRM_BRIDGE_OP_HDMI
>>>
>>> BTW: No HPD IRQ support?
>>
>> Renesas SMARC RZ/G3E this signal is internal. No dedicted IRQ line
>> Populated for this signal. I don't know about NXP and any other platforms
>> has HPD wired to test the HPD IRQ support.
>>
>> Maybe go with poll method now and add hot plug support,
>> when we have platform with HPD to test.
>
> I'm fine with this. According to the datasheet it doesn't seem to have
> the IRQ pin at all. It's just surprising to me. It's be nice to mention
> that HW doesn't support HPD IRQ either before setting it->bridge.ops or
> in the commit message.
Will mention this before setting it->bridge.ops.
--
Regards,
Liu Ying
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-14 0:00 ` Dmitry Baryshkov
@ 2024-10-18 6:58 ` Liu Ying
0 siblings, 0 replies; 49+ messages in thread
From: Liu Ying @ 2024-10-18 6:58 UTC (permalink / raw)
To: Dmitry Baryshkov, Biju Das
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org, andrzej.hajda@intel.com,
neil.armstrong@linaro.org, rfoss@kernel.org, laurent.pinchart,
jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com,
simona@ffwll.ch, maarten.lankhorst@linux.intel.com,
mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com,
catalin.marinas@arm.com, will@kernel.org,
quic_bjorande@quicinc.com, geert+renesas@glider.be, arnd@arndb.de,
nfraprado@collabora.com, o.rempel@pengutronix.de,
y.moog@phytec.de, marex@denx.de, isaac.scott@ideasonboard.com
On 10/14/2024, Dmitry Baryshkov wrote:
> On Sun, Oct 13, 2024 at 10:48:54AM +0000, Biju Das wrote:
[...]
>>>>> +static int it6263_bridge_attach(struct drm_bridge *bridge,
>>>>> + enum drm_bridge_attach_flags flags) {
>>>>> + struct it6263 *it = bridge_to_it6263(bridge);
>>>>> + int ret;
>>>>> +
>>>>> + ret = drm_bridge_attach(bridge->encoder, it->next_bridge, bridge,
>>>>> + flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
>>>>> + if (ret < 0)
>>>>> + return ret;
>>>>> +
>>>>> + if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
>>>>> + return 0;
>>>>> +
>>>>> + it->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
>>>>> + DRM_CONNECTOR_POLL_DISCONNECT;
>>>>> +
>>>>
>>>> Please strongly consider dropping this and using drm_bridge_connector
>>>> in the host driver.
>>>
>>> I can't afford to make i.MX8MP imx-lcdif KMS use drm_bridge_connector currently. Maybe the Renesas
>>> RZ/G3E SMARC EVK Biju tested v1 patch set with is also not using drm_bridge_connector. I hope we can
>>> leave it as-is for now.
>>
>> Renesas platform use the drm_bridge_connector_init() helper to create a drm_connector for
>> each output, instead of relying on the bridge drivers doing so. It attach
>> the bridges with the DRM_BRIDGE_ATTACH_NO_CONNECTOR flag to instruct
>> them not to create a connector.
>>
>> On Renesas platform, it exit from here
>> if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
>> return 0;
>>
>> Maybe it is good to have both cases to start with. Add support for both cases now,
>> Later when imx-lcdif KMS start using drm_bridge_connector,
>> we can start dropping bridge devices to create connector??
>
> Do we have a timeline for this?
I sent out a patch series to make i.MX LCDIF driver use
drm_bridge_connector just now.
https://patchwork.freedesktop.org/series/140148/
--
Regards,
Liu Ying
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
2024-10-15 6:28 ` Liu Ying
@ 2024-10-19 2:44 ` Dmitry Baryshkov
0 siblings, 0 replies; 49+ messages in thread
From: Dmitry Baryshkov @ 2024-10-19 2:44 UTC (permalink / raw)
To: Liu Ying
Cc: dri-devel, devicetree, linux-kernel, imx, linux-arm-kernel,
andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, airlied, simona, maarten.lankhorst, mripard,
tzimmermann, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, catalin.marinas, will, quic_bjorande, geert+renesas,
arnd, nfraprado, o.rempel, y.moog, marex, isaac.scott,
biju.das.jz
On Tue, 15 Oct 2024 at 09:27, Liu Ying <victor.liu@nxp.com> wrote:
>
> On 10/14/2024, Dmitry Baryshkov wrote:
> > On Mon, Oct 14, 2024 at 01:33:44PM +0800, Liu Ying wrote:
> >> On 10/14/2024, Dmitry Baryshkov wrote:
> >>> On Sat, Oct 12, 2024 at 05:14:13PM +0800, Liu Ying wrote:
> >>>> On 10/12/2024, Dmitry Baryshkov wrote:
> >>>>> On Sat, Oct 12, 2024 at 03:35:39PM +0800, Liu Ying wrote:
> >>>>>> Document ITE IT6263 LVDS to HDMI converter.
> >>>>>>
> >>>>>> Product link:
> >>>>>> https://www.ite.com.tw/en/product/cate1/IT6263
> >>>>>>
> >>>>>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> >>>>>> ---
> >>>>>> v2:
> >>>>>> * Document number of LVDS link data lanes. (Biju)
> >>>>>> * Simplify ports property by dropping "oneOf". (Rob)
> >>>>>>
> >>>>>> .../bindings/display/bridge/ite,it6263.yaml | 276 ++++++++++++++++++
> >>>>>> 1 file changed, 276 insertions(+)
> >>>>>> create mode 100644 Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
> >>>>>>
> >>>>>> diff --git a/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
> >>>>>> new file mode 100644
> >>>>>> index 000000000000..bc2bbec07623
> >>>>>> --- /dev/null
> >>>>>> +++ b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml
> >>>>>> @@ -0,0 +1,276 @@
> >>>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >>>>>> +%YAML 1.2
> >>>>>> +---
> >>>>>> +$id: http://devicetree.org/schemas/display/bridge/ite,it6263.yaml#
> >>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>>>>> +
> >>>>>> +title: ITE IT6263 LVDS to HDMI converter
> >>>>>> +
> >>>>>> +maintainers:
> >>>>>> + - Liu Ying <victor.liu@nxp.com>
> >>>>>> +
> >>>>>> +description: |
> >>>>>> + The IT6263 is a high-performance single-chip De-SSC(De-Spread Spectrum) LVDS
> >>>>>> + to HDMI converter. Combined with LVDS receiver and HDMI 1.4a transmitter,
> >>>>>> + the IT6263 supports LVDS input and HDMI 1.4 output by conversion function.
> >>>>>> + The built-in LVDS receiver can support single-link and dual-link LVDS inputs,
> >>>>>> + and the built-in HDMI transmitter is fully compliant with HDMI 1.4a/3D, HDCP
> >>>>>> + 1.2 and backward compatible with DVI 1.0 specification.
> >>>>>> +
> >>>>>> + The IT6263 also encodes and transmits up to 8 channels of I2S digital audio,
> >>>>>> + with sampling rate up to 192KHz and sample size up to 24 bits. In addition,
> >>>>>> + an S/PDIF input port takes in compressed audio of up to 192KHz frame rate.
> >>>>>> +
> >>>>>> + The newly supported High-Bit Rate(HBR) audio by HDMI specifications v1.3 is
> >>>>>> + provided by the IT6263 in two interfaces: the four I2S input ports or the
> >>>>>> + S/PDIF input port. With both interfaces the highest possible HBR frame rate
> >>>>>> + is supported at up to 768KHz.
> >>>>>> +
> >>>>>> +properties:
> >>>>>
> >>>>> No LVDS data-mapping support?
> >>>>
> >>>> It is enough to document number of LVDS link data lanes
> >>>> because OS should be able to determine the data-mapping
> >>>> by looking at the number and the data-mapping capability
> >>>> of the other side of the LVDS link.
> >>>
> >>> From what I can see, data-mapping is specified on the consumer sink side
> >>> of the LVDS link. This means it should go to the bridge's device node.
> >>
> >> Then, I won't define data-lanes, because data-mapping implies it,
> >> e.g., jeida-24 implies data lanes 0/1/2/3, see lvds-data-mapping.yaml.
> >>
> >> Please let me know which one you prefer.
> >
> > I'd prefer data-mapping.
>
> Before I go ahead to use it, I'd like to get confirmation that
> it'll cover data mapping which supports 30-bit RGB pixel transmission,
> because it is something supported by IT6263 as I mentioned in v1
> dt-binding discussion. For now, data-mapping only supports jeida-18,
> jeida-24 and vesa-24, see lvds-data-mapping.yaml. And, I'm not
> sure the 30-bit data mappings specified in IT6263 datasheet are
> standard or not.
It is not. At the time the standards were written, nobody was actually
thinking about the 30bpp panels.
> Note that if we use data-lanes instead, then this is not a concern
> from DT PoV, as data mapping can be inferred by OS.
It can not. There is no way to determine if JEIDA or VESA / SPWG
format is being used if it is not declared.
Moreover, <uapi/linux/media-bus-format.h> doesn't declare 1X7X5
formats. If you are to support 30bpp LVDS, you'd need to define two
corresponding constants, then extend data-mapping definition and code
by documenting 5-lane LVDS as standards extension to support 30bpp
transfers.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 49+ messages in thread
end of thread, other threads:[~2024-10-19 2:44 UTC | newest]
Thread overview: 49+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-10-12 7:35 [PATCH v2 0/9] Add ITE IT6263 LVDS to HDMI converter support Liu Ying
2024-10-12 7:35 ` [PATCH v2 1/9] arm64: dts: imx8mp-skov-revb-mi1010ait-1cp1: Add panel-timing node to panel node Liu Ying
2024-10-12 20:33 ` Marek Vasut
2024-10-12 7:35 ` [PATCH v2 2/9] arm64: dts: imx8mp-phyboard-pollux-rdk: Add panel-timing node to panel-lvds node Liu Ying
2024-10-12 20:34 ` Marek Vasut
2024-10-12 7:35 ` [PATCH v2 3/9] drm/bridge: fsl-ldb: Get the next non-panel bridge Liu Ying
2024-10-12 8:48 ` Dmitry Baryshkov
2024-10-12 7:35 ` [PATCH v2 4/9] drm/bridge: fsl-ldb: Use clk_round_rate() to validate "ldb" clock rate Liu Ying
2024-10-12 7:35 ` [PATCH v2 5/9] dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter Liu Ying
2024-10-12 8:30 ` Dmitry Baryshkov
2024-10-12 9:14 ` Liu Ying
2024-10-13 23:45 ` Dmitry Baryshkov
2024-10-14 5:33 ` Liu Ying
2024-10-14 5:54 ` Liu Ying
2024-10-14 7:07 ` Dmitry Baryshkov
2024-10-14 10:01 ` Liu Ying
2024-10-14 11:15 ` Dmitry Baryshkov
2024-10-15 18:58 ` Rob Herring
2024-10-15 6:28 ` Liu Ying
2024-10-19 2:44 ` Dmitry Baryshkov
2024-10-14 7:39 ` Biju Das
2024-10-14 7:58 ` Biju Das
2024-10-14 8:04 ` Dmitry Baryshkov
2024-10-14 8:09 ` Biju Das
2024-10-14 11:16 ` Dmitry Baryshkov
2024-10-14 11:25 ` Biju Das
2024-10-14 11:36 ` Dmitry Baryshkov
2024-10-14 8:30 ` Biju Das
2024-10-12 7:35 ` [PATCH v2 6/9] drm/bridge: " Liu Ying
2024-10-12 8:45 ` Dmitry Baryshkov
2024-10-12 10:01 ` Liu Ying
2024-10-13 10:48 ` Biju Das
2024-10-14 0:00 ` Dmitry Baryshkov
2024-10-18 6:58 ` Liu Ying
2024-10-13 23:58 ` Dmitry Baryshkov
2024-10-13 10:27 ` Biju Das
2024-10-14 0:06 ` Dmitry Baryshkov
2024-10-17 9:53 ` Liu Ying
2024-10-14 7:10 ` Dmitry Baryshkov
2024-10-14 7:18 ` Liu Ying
2024-10-14 7:32 ` Dmitry Baryshkov
2024-10-14 8:28 ` Liu Ying
2024-10-14 11:22 ` Dmitry Baryshkov
2024-10-14 8:14 ` Biju Das
2024-10-14 8:37 ` Liu Ying
2024-10-15 4:54 ` kernel test robot
2024-10-12 7:35 ` [PATCH v2 7/9] arm64: dts: imx8mp-evk: Add NXP LVDS to HDMI adapter cards Liu Ying
2024-10-12 7:35 ` [PATCH v2 8/9] arm64: defconfig: Enable ITE IT6263 driver Liu Ying
2024-10-12 7:35 ` [PATCH v2 9/9] MAINTAINERS: Add maintainer for " Liu Ying
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