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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id bx11-20020a05651c198b00b0026c15d60ad1sm37998ljb.132.2022.09.20.08.19.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 20 Sep 2022 08:19:56 -0700 (PDT) Message-ID: <07c118cb-4daf-8e82-2969-1cff072ec52a@linaro.org> Date: Tue, 20 Sep 2022 17:19:55 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 Subject: Re: [PATCH 2/2] mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase Content-Language: en-US To: Dinh Nguyen , Ulf Hansson Cc: jh80.chung@samsung.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20220919181309.286611-1-dinguyen@kernel.org> <20220919181309.286611-2-dinguyen@kernel.org> <50c7d35b-f395-6421-1422-56e30a580318@kernel.org> From: Krzysztof Kozlowski In-Reply-To: <50c7d35b-f395-6421-1422-56e30a580318@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 20/09/2022 15:24, Dinh Nguyen wrote: > > Hi Ulf, > > Thanks for the review! > > On 9/20/22 07:17, Ulf Hansson wrote: >> On Mon, 19 Sept 2022 at 20:13, Dinh Nguyen wrote: >>> >>> The clock-phase settings for the SDMMC controller in the SoCFPGA >>> Strarix10/Agilex/N5X platforms reside in a register in the System >>> Manager. Add a method to access that register through the syscon >>> interface. >>> >>> Signed-off-by: Dinh Nguyen >>> --- >>> drivers/mmc/host/dw_mmc-pltfm.c | 68 ++++++++++++++++++++++++++++++++- >>> 1 file changed, 67 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c >>> index 9901208be797..9e3237c18a9d 100644 >>> --- a/drivers/mmc/host/dw_mmc-pltfm.c >>> +++ b/drivers/mmc/host/dw_mmc-pltfm.c >>> @@ -17,10 +17,15 @@ >>> #include >>> #include >>> #include >>> +#include >>> +#include >>> >>> #include "dw_mmc.h" >>> #include "dw_mmc-pltfm.h" >>> >>> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ >>> + ((((smplsel) & 0x7) << 4) | (((drvsel) & 0x7) << 0)) >>> + >>> int dw_mci_pltfm_register(struct platform_device *pdev, >>> const struct dw_mci_drv_data *drv_data) >>> { >>> @@ -62,9 +67,70 @@ const struct dev_pm_ops dw_mci_pltfm_pmops = { >>> }; >>> EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops); >>> >>> +static int dw_mci_socfpga_priv_init(struct dw_mci *host) >>> +{ >>> + struct device_node *np = host->dev->of_node; >>> + struct regmap *sys_mgr_base_addr; >>> + u32 clk_phase[2] = {0}, reg_offset; >>> + int i, rc, hs_timing; >>> + >>> + rc = of_property_read_variable_u32_array(np, "clk-phase-sd-hs", &clk_phase[0], 2, 0); >> >> This needs to be documented through updated DT bindings. > > Ok, but it looks like clk-phase-sd-hs is already documented in > Documentation/devicetree/bindings/mmc/mmc-controller.yaml Not in next-20220919. > > Should I create a specific documentation just for > "altr,socfpga-dw-mshc" and document "clk-phase-sd-hs"? All properties must be documented. > >> >>> + if (rc) { >>> + sys_mgr_base_addr = >>> + altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon"); >> >> DT bindings? > > "altr,sysmgr-syscon" has already been documented in > Documentation/devicetree/bindings/net/socfpga-dwmac.txt This is not documentation of nodes you are changing here and in patch 1. You linked altr,socfpga-stmmac and here you have altr,socfpga-dw-mshc... Best regards, Krzysztof