From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: jsandom@axon.com, Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 1/5] arm64: dts: qcom: sm8550: add PCIe MHI register regions
Date: Tue, 14 Apr 2026 13:53:57 +0200 [thread overview]
Message-ID: <07ff689e-39dc-4f3d-b68f-3f3942916283@oss.qualcomm.com> (raw)
In-Reply-To: <20260409-rb5gen2-dts-v3-1-be736355d4b4@axon.com>
On 4/9/26 5:26 PM, Joe Sandom via B4 Relay wrote:
> From: Joe Sandom <jsandom@axon.com>
>
> Add the MHI register regions to the pcie0 and pcie1 controller nodes
> to expose link power state transition counters (L0s/L1/L1.1/L1.2/L2)
> via debugfs. The PCIe host driver uses this region to read the
> link_transition_count from the MHI registers.
>
> Signed-off-by: Joe Sandom <jsandom@axon.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
next prev parent reply other threads:[~2026-04-14 11:54 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-09 15:26 [PATCH v3 0/5] arm64: dts: qcom: add QCS8550 RB5Gen2 support Joe Sandom via B4 Relay
2026-04-09 15:26 ` [PATCH v3 1/5] arm64: dts: qcom: sm8550: add PCIe MHI register regions Joe Sandom via B4 Relay
2026-04-14 11:53 ` Konrad Dybcio [this message]
2026-04-09 15:26 ` [PATCH v3 2/5] arm64: dts: qcom: sm8550: add PCIe port labels Joe Sandom via B4 Relay
2026-04-09 15:26 ` [PATCH v3 3/5] arm64: dts: qcom: sm8550: move IPA properties to SoC device tree Joe Sandom via B4 Relay
2026-04-09 15:26 ` [PATCH v3 4/5] dt-bindings: arm: qcom: document QCS8550 RB5Gen2 board Joe Sandom via B4 Relay
2026-04-09 15:26 ` [PATCH v3 5/5] arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board support Joe Sandom via B4 Relay
2026-04-13 1:39 ` Dmitry Baryshkov
2026-04-13 9:09 ` Joe Sandom
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