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Tue, 16 Jul 2024 22:09:30 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46GM9TSt015181 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 16 Jul 2024 22:09:29 GMT Received: from [10.110.79.225] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 16 Jul 2024 15:09:28 -0700 Message-ID: <083e1e6f-714d-4a3e-a864-59e06bba0559@quicinc.com> Date: Tue, 16 Jul 2024 15:09:28 -0700 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V226/7] dt-bindings: PCI: host-generic-pci: Add snps,dw-pcie-ecam-msi binding To: Krzysztof Kozlowski , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , References: <1721067215-5832-1-git-send-email-quic_mrana@quicinc.com> <1721067215-5832-7-git-send-email-quic_mrana@quicinc.com> <5f029f16-2030-4e86-929b-0b2832958912@kernel.org> Content-Language: en-US From: Mayank Rana In-Reply-To: <5f029f16-2030-4e86-929b-0b2832958912@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: BGc8TP0-jGkacfrCs4tQktSRNW4QT3zS X-Proofpoint-GUID: BGc8TP0-jGkacfrCs4tQktSRNW4QT3zS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-16_01,2024-07-16_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 bulkscore=0 adultscore=0 suspectscore=0 phishscore=0 spamscore=0 mlxlogscore=999 mlxscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407160162 Hi Krzysztof On 7/16/2024 12:28 AM, Krzysztof Kozlowski wrote: > On 15/07/2024 20:13, Mayank Rana wrote: >> To support MSI functionality using Synopsys DesignWare PCIe controller >> based MSI controller with ECAM driver, add "snps,dw-pcie-ecam-msi >> compatible binding which uses provided SPIs to support MSI functionality. > > To support MSI, you add MSI support... That's a tautology. Describe > hardware instead. Ok. let me repharse it to provide more useful information. >> >> Signed-off-by: Mayank Rana >> --- >> .../devicetree/bindings/pci/host-generic-pci.yaml | 57 ++++++++++++++++++++++ >> 1 file changed, 57 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.yaml b/Documentation/devicetree/bindings/pci/host-generic-pci.yaml >> index 9c714fa..9e860d5 100644 >> --- a/Documentation/devicetree/bindings/pci/host-generic-pci.yaml >> +++ b/Documentation/devicetree/bindings/pci/host-generic-pci.yaml >> @@ -81,6 +81,12 @@ properties: >> - marvell,armada8k-pcie-ecam >> - socionext,synquacer-pcie-ecam >> - const: snps,dw-pcie-ecam >> + - description: | >> + Firmware is configuring Synopsys DesignWare PCIe controller in RC mode with >> + ECAM compatible fashion. To use MSI controller of Synopsys DesignWare PCIe >> + controller for MSI functionality, this compatible is used. >> + items: >> + - const: snps,dw-pcie-ecam-msi > > MSI is already present in the binding, isn't it? It is mentioning as msi-parent usage which could be different MSI controller (GIC or vendor specific one) not related to designware PCIe controller based MSI controller. >Anyway, aren't you > forgetting specific compatible? Please open your internal (quite > comprehensive) guideline on bindings and DTS. Here I am trying to define Designware based PCIe ECAM controller supporting MSIcontroller based device. Hence I am not mentioning vendor specific compatible usage and keeping generic compatible binding for such device. > >> - description: >> CAM or ECAM compliant PCI host controllers without any quirks >> enum: >> @@ -116,6 +122,20 @@ properties: >> A phandle to the node that controls power or/and system resource or interface to firmware >> to enable ECAM compliant PCIe root complex. >> >> + interrupts: >> + description: >> + DWC PCIe Root Port/Complex specific MSI interrupt/IRQs. >> + minItems: 1 >> + maxItems: 8 >> + >> + interrupt-names: >> + description: >> + MSI interrupt names >> + minItems: 1 >> + maxItems: 8 >> + items: >> + pattern: '^msi[0-9]+$' > > Why the same devices have variable numbers? Max supported MSI with designware PCIe controller is 8 Only, and it depends if those all are used or some of used on specific vendor based device. Hence I have kept it here variable names. Although here it should be [0 - 7] instead of [0 - 9]. >> + >> required: >> - compatible >> - reg >> @@ -146,11 +166,22 @@ allOf: >> reg: >> maxItems: 1 > > > Best regards, > Krzysztof >