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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT003.mail.protection.outlook.com (10.13.175.93) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6111.13 via Frontend Transport; Fri, 17 Feb 2023 09:34:45 +0000 Received: from [10.254.241.51] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Fri, 17 Feb 2023 03:34:42 -0600 Message-ID: <08839e77-5b0f-db13-ac7f-c9addc73b7a3@amd.com> Date: Fri, 17 Feb 2023 10:34:39 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.2 Subject: Re: [PATCH 1/2] i2c: cadence: Allow to specify the FIFO depth and maximum transfer length Content-Language: en-US To: Lars-Peter Clausen , Wolfram Sang CC: Shubhrajyoti Datta , Rob Herring , Krzysztof Kozlowski , , References: <20230205230208.58355-1-lars@metafoo.de> <813224a5-54c9-f6f1-4288-703a6388dab6@amd.com> From: Michal Simek In-Reply-To: Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Feb 2023 09:34:45.3401 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a6f01054-8e88-4421-688b-08db10ca3499 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT003.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8600 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 2/16/23 15:12, Lars-Peter Clausen wrote: > On 2/6/23 00:02, Michal Simek wrote: >> >> >> On 2/6/23 00:02, Lars-Peter Clausen wrote: >>> The FIFO depth and maximum transfer length are Synthesis configuration >>> parameters of the Cadence I2C IP. Different SoCs will use different values >>> for these parameters. >>> >>> Currently the driver has the FIFO depth hardcoded to 16 and the maximum >>> transfer length to 255. Trying to use the driver with an IP instance that >>> uses smaller values for these will work for short transfers. But longer >>> transfers will fail. >>> >>> The maximum transfer length can easily be detected at runtime since the >>> unused MSBs of the transfer length register are hardwired to 0. Writing >>> 0xff and then reading back the value will give the maximum transfer length. >> >> I think that these are pretty much two patches in one. >> The first should target transfer length part and second fifo depth part. > Hm, I'm not sure it is worth separating this out. These two are very tightly > related, but I can split it. thanks >> >>>   /** >>>    * cdns_i2c_probe - Platform registration call >>>    * @pdev:    Handle to the platform device structure >>> @@ -1242,6 +1274,7 @@ static int cdns_i2c_probe(struct platform_device *pdev) >>>       struct cdns_i2c *id; >>>       int ret, irq; >>>       const struct of_device_id *match; >>> +    u32 val; >>>         id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL); >>>       if (!id) >>> @@ -1317,6 +1350,12 @@ static int cdns_i2c_probe(struct platform_device *pdev) >>>   #endif >>>       id->ctrl_reg = CDNS_I2C_CR_ACK_EN | CDNS_I2C_CR_NEA | CDNS_I2C_CR_MS; >>>   +    val = CDNS_I2C_FIFO_DEPTH_DEFAULT; >> >> you can remove val completely. >> id->fifo_depth = CDNS_I2C_FIFO_DEPTH_DEFAULT; > But only if I make fifo_depth a u32. No problem for me. M