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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bcc57c12799sm492515666b.47.2026.05.12.03.01.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 May 2026 03:01:44 -0700 (PDT) Message-ID: <08d1fd7a-c782-4d8b-85ee-1b46868db343@oss.qualcomm.com> Date: Tue, 12 May 2026 12:01:40 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 5/8] clk: qcom: gcc-msm8939: mark Venus core GDSCs as hardware controlled To: Erikas Bitovtas , Bryan O'Donoghue , Vikash Garodia , Dikshita Agarwal , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?Q?Andr=C3=A9_Apitzsch?= , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Brian Masney Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org References: <20260510-msm8939-venus-rfc-v6-0-e69465375900@gmail.com> <20260510-msm8939-venus-rfc-v6-5-e69465375900@gmail.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260510-msm8939-venus-rfc-v6-5-e69465375900@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: aYjCHfEYebw1PP2vPCt9JWBZrX7j-AxU X-Proofpoint-ORIG-GUID: aYjCHfEYebw1PP2vPCt9JWBZrX7j-AxU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEyMDEwMSBTYWx0ZWRfX/4Ekpc0Uu9/Y KapZsI57X+/MCZrp24r70NZ8ojysXlfSob5G4y4aPnvsjE1asGMLXUxI+ngNK7QAvb6I/u5zIuG sjxIoXn+KBaiMwITd/t7F+EMHTWch4Jkc3d23aHR+emru6g7aV7mw9UNH1qTC3mFvLNNUcqEZsY /paCHvLxagKQ+qvTkdErqm1yCwJc0MIC25vUdgS1/9hlEtrXztVJ1kCw1xQS2mjaCBZD/LrPvma kYzyIwCTYKEOxnrzsdYL9YT/eMVzvnhbl/EoJkTFpwO6LalVHnp6fsjDphUHyFr4G5pdWH5N9Kd eTY4gL74dfcYcZ5jP5lHW9vel/IapDT5fA09cqlQ3TDZL9TRoVDpbwBfUr2z3L5WcaFnLG7LMgg lfBV0zaU1BOhyEW6JsKxRDRwFjuhwda6nc3RYhlZT7HaGtfHQLFsUD2CcMrh8HHkEquR/0lIaCg 1PSzaU0dtjvI5jRyg6w== X-Authority-Analysis: v=2.4 cv=c6ebhx9l c=1 sm=1 tr=0 ts=6a02fa8a cx=c_pps a=DUEm7b3gzWu7BqY5nP7+9g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=pGLkceISAAAA:8 a=alOFDL0nBBd-F9mXlB8A:9 a=QEXdDO2ut3YA:10 a=-aSRE8QhW-JAV6biHavz:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-11_05,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 malwarescore=0 spamscore=0 suspectscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605120101 On 5/10/26 11:47 AM, Erikas Bitovtas wrote: > Since in downstream kernel VENUS_CORE0_GDSC and VENUS_CORE1_GDSC have a > device tree property "qcom,supports-hw-trigger", add a HW_CTRL flag > to these GDSCs to pass their control to hardware. > > Venus core clock cannot be enabled if Venus core GDSCs are switched off. The downstream device tree suggests the reverse - the venus_coreN GDSCs refer to venus0_coreN_vcodec0_clk (and venus_gdsc lists clk_gcc_venus0_axi_clk and clk_gcc_venus0_vcodec0_clk) > But since they are set to be hardware controlled, they can be switched > off at any moment. Vote for the Venus core clock to enable it later when > GDSCs get turned on. I understand these words but I can't see how they reflect the change > > Signed-off-by: Erikas Bitovtas > --- > drivers/clk/qcom/gcc-msm8939.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c > index 45193b3d714b..420997b00ae0 100644 > --- a/drivers/clk/qcom/gcc-msm8939.c > +++ b/drivers/clk/qcom/gcc-msm8939.c > @@ -3664,6 +3664,7 @@ static struct clk_branch gcc_venus0_vcodec0_clk = { > > static struct clk_branch gcc_venus0_core0_vcodec0_clk = { > .halt_reg = 0x4c02c, > + .halt_check = BRANCH_HALT_SKIP, > .clkr = { > .enable_reg = 0x4c02c, > .enable_mask = BIT(0), > @@ -3681,6 +3682,7 @@ static struct clk_branch gcc_venus0_core0_vcodec0_clk = { > > static struct clk_branch gcc_venus0_core1_vcodec0_clk = { > .halt_reg = 0x4c034, > + .halt_check = BRANCH_HALT_SKIP, > .clkr = { > .enable_reg = 0x4c034, > .enable_mask = BIT(0), > @@ -3753,6 +3755,7 @@ static struct gdsc venus_core0_gdsc = { > .pd = { > .name = "venus_core0", > }, > + .flags = HW_CTRL, > .pwrsts = PWRSTS_OFF_ON, > }; > > @@ -3761,6 +3764,7 @@ static struct gdsc venus_core1_gdsc = { > .pd = { > .name = "venus_core1", > }, > + .flags = HW_CTRL, This should be HW_CTRL_TRIGGER, paired with a change to call dev_pm_genpd_set_hwmode() in the driver - this currently only happens in vcodec_control_v4(). Konrad