From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; dkim=none Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CBC7A10E2; Wed, 29 Nov 2023 22:05:06 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 1F18F24E260; Thu, 30 Nov 2023 14:04:52 +0800 (CST) Received: from EXMBX161.cuchost.com (172.16.6.71) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 30 Nov 2023 14:04:51 +0800 Received: from EXMBX066.cuchost.com (172.16.7.66) by EXMBX161.cuchost.com (172.16.6.71) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 30 Nov 2023 14:04:51 +0800 Received: from EXMBX066.cuchost.com ([fe80::5947:9245:907e:339f]) by EXMBX066.cuchost.com ([fe80::5947:9245:907e:339f%17]) with mapi id 15.00.1497.044; Thu, 30 Nov 2023 14:04:51 +0800 From: JeeHeng Sia To: Conor Dooley CC: "kernel@esmil.dk" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "krzk@kernel.org" , "conor+dt@kernel.org" , "paul.walmsley@sifive.com" , "palmer@dabbelt.com" , "aou@eecs.berkeley.edu" , "daniel.lezcano@linaro.org" , "tglx@linutronix.de" , "anup@brainfault.org" , "gregkh@linuxfoundation.org" , "jirislaby@kernel.org" , "michal.simek@amd.com" , Michael Zhu , "drew@beagleboard.org" , "devicetree@vger.kernel.org" , "linux-riscv@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Leyfoon Tan Subject: RE: [PATCH v2 1/6] dt-bindings: riscv: Add StarFive Dubhe compatibles Thread-Topic: [PATCH v2 1/6] dt-bindings: riscv: Add StarFive Dubhe compatibles Thread-Index: AQHaIol1JcCnwq8cUEOHXow7o5B+9LCQ2lcAgAGGuzA= Date: Thu, 30 Nov 2023 06:04:51 +0000 Message-ID: <08daada77b3e40049ef83f4eb762240c@EXMBX066.cuchost.com> References: <20231129060043.368874-1-jeeheng.sia@starfivetech.com> <20231129060043.368874-2-jeeheng.sia@starfivetech.com> <20231129-revisit-prefix-5327168e91f3@spud> In-Reply-To: <20231129-revisit-prefix-5327168e91f3@spud> Accept-Language: en-US, zh-CN Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-yovoleruleagent: yovoleflag Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 > -----Original Message----- > From: Conor Dooley > Sent: Wednesday, November 29, 2023 10:46 PM > To: JeeHeng Sia > Cc: kernel@esmil.dk; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.or= g; krzk@kernel.org; conor+dt@kernel.org; > paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; dani= el.lezcano@linaro.org; tglx@linutronix.de; > anup@brainfault.org; gregkh@linuxfoundation.org; jirislaby@kernel.org; mi= chal.simek@amd.com; Michael Zhu > ; drew@beagleboard.org; devicetree@vger.ker= nel.org; linux-riscv@lists.infradead.org; linux- > kernel@vger.kernel.org; Leyfoon Tan > Subject: Re: [PATCH v2 1/6] dt-bindings: riscv: Add StarFive Dubhe compat= ibles >=20 > On Wed, Nov 29, 2023 at 02:00:38PM +0800, Sia Jee Heng wrote: > > Add new compatible strings for Dubhe-80 and Dubhe-90. These are > > RISC-V cpu core from StarFive Technology and are used in StarFive > > JH8100 SoC. > > > > Signed-off-by: Sia Jee Heng > > Reviewed-by: Ley Foon Tan > > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Docume= ntation/devicetree/bindings/riscv/cpus.yaml > > index f392e367d673..493972b29a22 100644 > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > @@ -48,6 +48,8 @@ properties: > > - thead,c906 > > - thead,c910 > > - thead,c920 > > + - starfive,dubhe-80 > > + - starfive,dubhe-90 >=20 > s goes before t. Noted. Will fix it. >=20 > Cheers, > Conor. >=20 > > - const: riscv > > - items: > > - enum: > > -- > > 2.34.1 > >