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Fri, 28 Mar 2025 05:54:32 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG3anLwA38qSCKKag9lmtLmor/BQAnLHTK54dL2de4RfOxS+atpW42HtIHCjKX01cq8OUGIKw== X-Received: by 2002:a17:902:e805:b0:223:6254:b4ba with SMTP id d9443c01a7336-22804840baemr107748345ad.13.1743166471521; Fri, 28 Mar 2025 05:54:31 -0700 (PDT) Received: from [192.168.29.92] ([49.43.229.109]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2291eee5011sm17016405ad.103.2025.03.28.05.54.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 28 Mar 2025 05:54:31 -0700 (PDT) Message-ID: <090572fa-7c4c-798d-26e9-39570215b2b7@oss.qualcomm.com> Date: Fri, 28 Mar 2025 18:24:23 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v5 1/7] arm64: dts: qcom: sc7280: Increase config size to 256MB for ECAM feature Content-Language: en-US To: Manivannan Sadhasivam , Konrad Dybcio Cc: cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Bjorn Helgaas , Jingoo Han , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_vpernami@quicinc.com, mmareddy@quicinc.com References: <20250309-ecam_v4-v5-0-8eff4b59790d@oss.qualcomm.com> <20250309-ecam_v4-v5-1-8eff4b59790d@oss.qualcomm.com> <3332fe69-dddb-439d-884f-2b97845c14e1@oss.qualcomm.com> <0cc247a4-d857-4fb1-8f87-0d52d641eced@oss.qualcomm.com> From: Krishna Chaitanya Chundru In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: yJj8A5WZUdi0oFd5OIM6B0mtXnESaLec X-Proofpoint-ORIG-GUID: yJj8A5WZUdi0oFd5OIM6B0mtXnESaLec X-Authority-Analysis: v=2.4 cv=KvJN2XWN c=1 sm=1 tr=0 ts=67e69c09 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=YFFC5ybGexI6wqmPE8t+iw==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=taV9Rfz_io-hon4YrvgA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-28_06,2025-03-27_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxlogscore=999 malwarescore=0 priorityscore=1501 clxscore=1015 mlxscore=0 spamscore=0 impostorscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503280089 On 3/28/2025 5:14 PM, Manivannan Sadhasivam wrote: > On Wed, Mar 26, 2025 at 06:56:02PM +0100, Konrad Dybcio wrote: >> On 3/11/25 12:13 PM, Konrad Dybcio wrote: >>> On 3/9/25 6:45 AM, Krishna Chaitanya Chundru wrote: >>>> PCIe ECAM(Enhanced Configuration Access Mechanism) feature requires >>>> maximum of 256MB configuration space. >>>> >>>> To enable this feature increase configuration space size to 256MB. If >>>> the config space is increased, the BAR space needs to be truncated as >>>> it resides in the same location. To avoid the bar space truncation move >>>> config space, DBI, ELBI, iATU to upper PCIe region and use lower PCIe >>>> iregion entirely for BAR region. >>>> >>>> This depends on the commit: '10ba0854c5e6 ("PCI: qcom: Disable mirroring >>>> of DBI and iATU register space in BAR region")' >>>> >>>> Signed-off-by: Krishna Chaitanya Chundru >>>> Reviewed-by: Manivannan Sadhasivam >>>> --- >>> >>> Reviewed-by: Konrad Dybcio >> >> I took a second look - why are dbi and config regions overlapping? >> > > Not just DBI, ELBI too. > >> I would imagine the latter to be at a certain offset >> > > The problem is that for ECAM, we need config space region to be big enough to > cover all 256 buses. For that reason Krishna overlapped the config region and > DBI/ELBI. Initially I also questioned this and somehow convinced that there is > no other way (no other memory). But looking at the internal documentation now, > I realized that atleast 512MiB of PCIe space is available for each controller > instance. > DBI is the config space of the root port0, ecam expects all the config space is continuous i.e 256MB and this 256MB config space is ioremaped in ecam driver[1]. This 256 MB should contain the dbi memory too and elbi always with dbi region we can't move it other locations. We are keeping overlap region because once ecam driver io remaped all 256MB including dbi and elbi memory dwc memory can't ioremap the dbi and elbi region again. That is the reason for having this overlap region. > So I just quickly tried this series on SA8775p and by moving the config space > after the iATU region, I was able to have ECAM working without overlapping > addresses in DT. Here is the change I did: > I am sure ecam is not enabled with this below change because ecam block have the address alignment requirement that address should be aligned to the base address of the range is aligned to a 2(n+20)-byte memory address boundary from pcie spec 6.0.1, sec 7.2.2 (PCI Express Enhanced Configuration Access Mechanism (ECAM)), with out that address alignment ecam will not work since ecam driver gets bus number function number by shifting the address internally. If this is not acceptable we have mimic the ecam driver in dwc driver which is also not recommended. - Krishna Chaitanya. > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > index 3394ae2d1300..e41c8e3dd30c 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > @@ -6395,18 +6395,18 @@ arch_timer: timer { > pcie0: pcie@1c00000 { > compatible = "qcom,pcie-sa8775p"; > reg = <0x0 0x01c00000 0x0 0x3000>, > - <0x0 0x40000000 0x0 0xf20>, > - <0x0 0x40000f20 0x0 0xa8>, > - <0x0 0x40001000 0x0 0x4000>, > - <0x0 0x40100000 0x0 0x100000>, > + <0x4 0x00000000 0x0 0xf20>, > + <0x4 0x00000f20 0x0 0xa8>, > + <0x4 0x10000000 0x0 0x4000>, > + <0x4 0x10004000 0x0 0x10000000>, > <0x0 0x01c03000 0x0 0x1000>; > reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; > device_type = "pci"; > > #address-cells = <3>; > #size-cells = <2>; > - ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, > - <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; > + ranges = <0x01000000 0x0 0x00000000 0x0 0x40000000 0x0 0x100000>, > + <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff00000>; > bus-range = <0x00 0xff>; > > dma-coherent; > > > Krishna: Could you also try similar change on SC7280 and see if it works? > > - Mani >