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([2a01:e0a:982:cbb0:2fcf:6f16:3b3b:da8e]) by smtp.gmail.com with ESMTPSA id bs18-20020a056000071200b0034181bea3b0sm2928949wrb.3.2024.03.19.07.35.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 Mar 2024 07:35:26 -0700 (PDT) Message-ID: <090e306c-0bfc-4374-83ed-e883d73a0f0a@linaro.org> Date: Tue, 19 Mar 2024 15:35:25 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH 3/7] phy: qcom: qmp-pcie: register second optional PHY AUX clock Content-Language: en-US, fr From: Neil Armstrong To: Dmitry Baryshkov Cc: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-0-926d7a4ccd80@linaro.org> <20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-3-926d7a4ccd80@linaro.org> <85d67f3f-2b01-44c0-ace3-5e7cb48a9431@linaro.org> Autocrypt: addr=neil.armstrong@linaro.org; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 19/03/2024 11:59, Neil Armstrong wrote: > On 19/03/2024 11:55, Dmitry Baryshkov wrote: >> On Tue, 19 Mar 2024 at 12:45, Neil Armstrong wrote: >>> >>> The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock, >>> add the code to register it for PHYs configs that sets a aux_clock_rate. >>> >>> In order to get the right clock, add qmp_pcie_clk_hw_get() which uses >>> the newly introduced QMP_PCIE_PIPE_CLK & QMP_PCIE_PHY_AUX_CLK clock >>> IDs and also supports the legacy bindings by returning the PIPE clock. >>> >>> Signed-off-by: Neil Armstrong >>> --- >>>   drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 70 ++++++++++++++++++++++++++++++++ >>>   1 file changed, 70 insertions(+) >>> >>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >>> index 079b3e306489..2d05226ae200 100644 >>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >>> @@ -22,6 +22,8 @@ >>>   #include >>>   #include >>> >>> +#include >>> + >>>   #include "phy-qcom-qmp-common.h" >>> >>>   #include "phy-qcom-qmp.h" >>> @@ -2389,6 +2391,9 @@ struct qmp_phy_cfg { >>> >>>          /* QMP PHY pipe clock interface rate */ >>>          unsigned long pipe_clock_rate; >>> + >>> +       /* QMP PHY AUX clock interface rate */ >>> +       unsigned long aux_clock_rate; >>>   }; >>> >>>   struct qmp_pcie { >>> @@ -2420,6 +2425,7 @@ struct qmp_pcie { >>>          int mode; >>> >>>          struct clk_fixed_rate pipe_clk_fixed; >>> +       struct clk_fixed_rate aux_clk_fixed; >>>   }; >>> >>>   static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) >>> @@ -3681,6 +3687,62 @@ static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np) >>>          return devm_clk_hw_register(qmp->dev, &fixed->hw); >>>   } >>> >>> +/* >>> + * Register a fixed rate PHY aux clock. >>> + * >>> + * The _phy_aux_clksrc generated by PHY goes to the GCC that gate >>> + * controls it. The _phy_aux_clk coming out of the GCC is requested >>> + * by the PHY driver for its operations. >>> + * We register the _phy_aux_clksrc here. The gcc driver takes care >>> + * of assigning this _phy_aux_clksrc as parent to _phy_aux_clk. >>> + * Below picture shows this relationship. >>> + * >>> + *         +---------------+ >>> + *         |   PHY block   |<<---------------------------------------------+ >>> + *         |               |                                               | >>> + *         |   +-------+   |                      +-----+                  | >>> + *   I/P---^-->|  PLL  |---^--->phy_aux_clksrc--->| GCC |--->phy_aux_clk---+ >>> + *    clk  |   +-------+   |                      +-----+ >>> + *         +---------------+ >>> + */ >>> +static int phy_aux_clk_register(struct qmp_pcie *qmp, struct device_node *np) >>> +{ >>> +       struct clk_fixed_rate *fixed = &qmp->aux_clk_fixed; >>> +       struct clk_init_data init = { }; >>> +       int ret; >>> + >>> +       ret = of_property_read_string_index(np, "clock-output-names", 1, &init.name); >>> +       if (ret) { >>> +               dev_err(qmp->dev, "%pOFn: No clock-output-names index 1\n", np); >>> +               return ret; >>> +       } >>> + >>> +       init.ops = &clk_fixed_rate_ops; >>> + >>> +       fixed->fixed_rate = qmp->cfg->aux_clock_rate; >>> +       fixed->hw.init = &init; >>> + >>> +       return devm_clk_hw_register(qmp->dev, &fixed->hw); >>> +} >>> + >>> +static struct clk_hw *qmp_pcie_clk_hw_get(struct of_phandle_args *clkspec, void *data) >>> +{ >>> +       struct qmp_pcie *qmp = data; >>> + >>> +       /* Support legacy bindings */ >>> +       if (!clkspec->args_count) >>> +               return &qmp->pipe_clk_fixed.hw; >>> + >>> +       switch (clkspec->args[0]) { >>> +       case QMP_PCIE_PIPE_CLK: >>> +               return &qmp->pipe_clk_fixed.hw; >>> +       case QMP_PCIE_PHY_AUX_CLK: >>> +               return &qmp->aux_clk_fixed.hw; >>> +       } >>> + >>> +       return ERR_PTR(-EINVAL); >>> +} >> >> Can we use of_clk_hw_onecell_get() instead? I think it even should be >> possible to use onecell for both cases, it will look at the first arg, >> which will be 0 in case of #clock-cells equal to 0. > > Let me investigate if it's possible Ok, it would work but it would require building a clk_hw_onecell_data a runtime, while we could simply provide this qmp_pcie_clk_hw_get() and avoid runtime 2 allocations. I'm not sure it's worth it. Neil > >> >>> + >>>   static int qmp_pcie_register_clocks(struct qmp_pcie *qmp, struct device_node *np) >>>   { >>>          int ret; >>> @@ -3689,6 +3751,14 @@ static int qmp_pcie_register_clocks(struct qmp_pcie *qmp, struct device_node *np >>>          if (ret) >>>                  return ret; >>> >>> +       if (qmp->cfg->aux_clock_rate) { >>> +               ret = phy_aux_clk_register(qmp, np); >>> +               if (ret) >>> +                       return ret; >>> + >>> +               return devm_of_clk_add_hw_provider(qmp->dev, qmp_pcie_clk_hw_get, qmp); >>> +       } >>> + >>>          return devm_of_clk_add_hw_provider(qmp->dev, of_clk_hw_simple_get, >>>                                             &qmp->pipe_clk_fixed.hw); >>>   } >>> >>> -- >>> 2.34.1 >>> >>> >> >> >