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From: Conor Dooley <conor@kernel.org>
To: Tommaso Merciai <tomm.merciai@gmail.com>
Cc: Hal Feng <hal.feng@starfivetech.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-clk@vger.kernel.org, Stephen Boyd <sboyd@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Ben Dooks <ben.dooks@sifive.com>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>,
	Emil Renner Berthing <emil.renner.berthing@canonical.com>,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC
Date: Thu, 9 Mar 2023 17:52:49 +0000	[thread overview]
Message-ID: <09630acb-f1ae-4dbd-9c9c-9adb1743bfe4@spud> (raw)
In-Reply-To: <ZAoOLIERMYI8UVlA@tom-HP-ZBook-Fury-15-G7-Mobile-Workstation>

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On Thu, Mar 09, 2023 at 05:49:48PM +0100, Tommaso Merciai wrote:
> On Wed, Mar 08, 2023 at 01:36:41PM +0000, Conor Dooley wrote:
> > On Wed, Mar 08, 2023 at 01:28:01PM +0100, Tommaso Merciai wrote:
> > > On Tue, Mar 07, 2023 at 06:08:53PM +0800, Hal Feng wrote:
> > 
> > > > The above two methods can fix the problem. Here are my test results.
> > > > The VisionFive board can boot up successfully if and only if all above
> > > > two applied.
> > > > The VisionFive 2 board can boot up successfully if I merge Linus's new
> > > > changes.
> > > 
> > > Tested also on my side. Hope this can be helpfull.
> > > 
> > > > Hope your fix will be merged in rc2. Thank you for your reply.
> > > 
> > > Fully agree.
> > 
> > If you only have a VisionFive 2, it shouldn't matter to you, as you
> > don't need to fix up any SiFive errata (at the moment at least).
> > Linus' fix is already in his tree, so should be in -rc2!
> > The fix for the VisionFive was applied to Palmer's RISC-V fixes tree
> > last night:
> > https://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git/commit/?h=fixes&id=bf89b7ee52af5a5944fa3539e86089f72475055b
> > 
> > Thanks,
> > Conor.
> 
> 
> Hi Conor,
> Thanks for the info.
> Playing with this series I got the following error:
> 
> [    6.278182] BUG: spinlock bad magic on CPU#0, udevd/136
> [    6.283414]  lock: 0xffffffd84135e6c0, .magic: ffffffff, .owner: <none>/-1, .owner_cpu: -1
> [    6.291677] CPU: 0 PID: 136 Comm: udevd Not tainted 6.3.0-rc1-g92569901a7f9-dirty #14
> [    6.299502] Hardware name: StarFive VisionFive 2 v1.3B (DT)
> [    6.305069] Call Trace:
> [    6.307517] [<ffffffff80005530>] dump_backtrace+0x1c/0x24
> [    6.312921] [<ffffffff80844b4e>] show_stack+0x2c/0x38
> [    6.317976] [<ffffffff8085032c>] dump_stack_lvl+0x3c/0x54
> [    6.323377] [<ffffffff80850358>] dump_stack+0x14/0x1c
> [    6.328429] [<ffffffff80845668>] spin_dump+0x64/0x70
> [    6.333394] [<ffffffff80058f26>] do_raw_spin_lock+0xb4/0xf2
> [    6.338970] [<ffffffff80857d04>] _raw_spin_lock+0x1a/0x22
> [    6.344370] [<ffffffff8008153c>] add_timer_on+0x8a/0x132
> [    6.349684] [<ffffffff8084b9fa>] try_to_generate_entropy+0x216/0x278
> [    6.356037] [<ffffffff804ebfdc>] urandom_read_iter+0x40/0xb8
> [    6.361697] [<ffffffff801a1216>] vfs_read+0x17e/0x1f8
> [    6.366752] [<ffffffff801a1986>] ksys_read+0x5e/0xc8
> [    6.371710] [<ffffffff801a19fe>] sys_read+0xe/0x16
> [    6.376503] [<ffffffff8000357a>] ret_from_syscall+0x0/0x2
> [    6.381905] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000007
> [    6.390683] Oops [#1]
> [    6.392956] Modules linked in:
> [    6.396011] CPU: 0 PID: 136 Comm: udevd Not tainted 6.3.0-rc1-g92569901a7f9-dirty #14
> [    6.403835] Hardware name: StarFive VisionFive 2 v1.3B (DT)
> [    6.409401] epc : enqueue_timer+0x1a/0x90
> [    6.413414]  ra : add_timer_on+0xe2/0x132
> [    6.417425] epc : ffffffff80080c60 ra : ffffffff80081594 sp : ffffffc8044dbc60
> [    6.424640]  gp : ffffffff814ffe50 tp : ffffffd8c171ad00 t0 : 6666666666663c5b
> [    6.431855]  t1 : 000000000000005b t2 : 666666666666663c s0 : ffffffc8044dbcc0
> [    6.439070]  s1 : ffffffc8044dbd08 a0 : ffffffd84135e6c0 a1 : ffffffc8044dbd08
> [    6.446284]  a2 : ffffffffffffffff a3 : 000000003e000000 a4 : 000000000000023e
> [    6.453498]  a5 : 000000000000023e a6 : ffffffd84135f930 a7 : 0000000000000038
> [    6.460712]  s2 : ffffffd84135e6c0 s3 : 0000000000000040 s4 : ffffffff81501080
> [    6.467926]  s5 : ffffffd84135e6c0 s6 : ffffffff815011b8 s7 : ffffffffffffffff
> [    6.475141]  s8 : ffffffff81502820 s9 : 0000000000000040 s10: 0000002ab0a49320
> [    6.482355]  s11: 0000000000000001 t3 : ffffffff81512e97 t4 : ffffffff81512e97
> [    6.489569]  t5 : ffffffff81512e98 t6 : ffffffc8044db948
> [    6.494875] status: 0000000200000100 badaddr: 0000000000000007 cause: 000000000000000f
> [    6.502783] [<ffffffff80080c60>] enqueue_timer+0x1a/0x90
> [    6.508095] [<ffffffff8084b9fa>] try_to_generate_entropy+0x216/0x278
> [    6.514448] [<ffffffff804ebfdc>] urandom_read_iter+0x40/0xb8
> [    6.520107] [<ffffffff801a1216>] vfs_read+0x17e/0x1f8
> [    6.525160] [<ffffffff801a1986>] ksys_read+0x5e/0xc8
> [    6.530126] [<ffffffff801a19fe>] sys_read+0xe/0x16
> [    6.534918] [<ffffffff8000357a>] ret_from_syscall+0x0/0x2
> [    6.540322] Code: 87b2 0813 0805 1613 0037 9832 3603 0008 e190 c211 (e60c) 5613
> [    6.547711] ---[ end trace 0000000000000000 ]---
> [    6.552325] note: udevd[136] exited with irqs disabled
> [    6.557531] note: udevd[136] exited with preempt_count 2
> 
> 
> I'm working on top of Linux version 6.3.0-rc1-g92569901a7f.

Unfortunately, this g<sha> bit doesn't mean anything outside of your
repo so it's hard to infer anything from that.
This looks exactly like a bug is in v6.3-rc1, but Linus fixed in like
the second commit *after* -rc1.

What branch/commit/tag did you apply the series on top of?

Cheers,
Conor.

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  reply	other threads:[~2023-03-09 17:53 UTC|newest]

Thread overview: 71+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-21  2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
2023-02-21  2:46 ` [PATCH v4 01/19] clk: starfive: Factor out common JH7100 and JH7110 code Hal Feng
2023-02-21  2:46 ` [PATCH v4 02/19] clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h Hal Feng
2023-02-21  2:46 ` [PATCH v4 03/19] clk: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
2023-02-21  2:46 ` [PATCH v4 04/19] reset: Create subdirectory for StarFive drivers Hal Feng
2023-02-21  2:46 ` [PATCH v4 05/19] reset: starfive: Factor out common JH71X0 reset code Hal Feng
2023-02-21 17:10   ` Conor Dooley
2023-02-21  2:46 ` [PATCH v4 06/19] reset: starfive: Extract the " Hal Feng
2023-02-21 17:13   ` Conor Dooley
2023-02-21  2:46 ` [PATCH v4 07/19] reset: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
2023-02-21 17:17   ` Conor Dooley
2023-02-21  2:46 ` [PATCH v4 08/19] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers Hal Feng
2023-02-21  2:46 ` [PATCH v4 09/19] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Hal Feng
2023-02-21 17:23   ` Conor Dooley
2023-02-23  3:40     ` Hal Feng
2023-02-22  9:13   ` Krzysztof Kozlowski
2023-02-22 10:40     ` Conor Dooley
2023-02-23 10:22       ` Hal Feng
2023-02-21  2:46 ` [PATCH v4 10/19] dt-bindings: clock: Add StarFive JH7110 always-on " Hal Feng
2023-02-21 17:26   ` Conor Dooley
2023-02-23  5:52     ` Hal Feng
2023-03-09 14:22   ` Geert Uytterhoeven
2023-03-13  2:29     ` Hal Feng
2023-02-21  2:46 ` [PATCH v4 11/19] clk: starfive: Add StarFive JH7110 system clock driver Hal Feng
2023-02-21 15:12   ` Conor Dooley
2023-02-23  6:17     ` Hal Feng
2023-02-26 16:07   ` Emil Renner Berthing
2023-02-28  2:30     ` Hal Feng
2023-02-21  2:46 ` [PATCH v4 12/19] clk: starfive: Add StarFive JH7110 always-on " Hal Feng
2023-02-26 17:34   ` Emil Renner Berthing
2023-02-28  2:42     ` Hal Feng
2023-03-09  9:43       ` Hal Feng
2023-03-09 14:06         ` Emil Renner Berthing
2023-03-09 18:11           ` Conor Dooley
2023-03-09 18:19             ` Emil Renner Berthing
2023-03-09 19:32               ` Palmer Dabbelt
2023-02-21  2:46 ` [PATCH v4 13/19] reset: starfive: Add StarFive JH7110 reset driver Hal Feng
2023-02-21 15:33   ` Emil Renner Berthing
2023-02-21 16:34     ` Conor Dooley
2023-02-23  6:48       ` Hal Feng
2023-02-23  6:29     ` Hal Feng
2023-02-21  2:46 ` [PATCH v4 14/19] dt-bindings: timer: Add StarFive JH7110 clint Hal Feng
2023-02-21  2:46 ` [PATCH v4 15/19] dt-bindings: interrupt-controller: Add StarFive JH7110 plic Hal Feng
2023-02-21  2:46 ` [PATCH v4 16/19] dt-bindings: riscv: Add SiFive S7 compatible Hal Feng
2023-02-21 11:38   ` Krzysztof Kozlowski
2023-02-21 15:10   ` Conor Dooley
2023-02-21  2:46 ` [PATCH v4 17/19] riscv: dts: starfive: Add initial StarFive JH7110 device tree Hal Feng
2023-02-21 17:03   ` Conor Dooley
2023-02-23  7:16     ` Hal Feng
2023-02-27 18:10       ` Conor Dooley
2023-02-21  2:46 ` [PATCH v4 18/19] riscv: dts: starfive: Add StarFive JH7110 pin function definitions Hal Feng
2023-02-21  2:46 ` [PATCH v4 19/19] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree Hal Feng
2023-02-21 15:03   ` Emil Renner Berthing
2023-02-23  8:50     ` Hal Feng
2023-02-27 18:12       ` Conor Dooley
2023-02-27 20:00         ` Conor Dooley
2023-02-28  2:58           ` Hal Feng
2023-02-22 15:00 ` [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC patchwork-bot+linux-riscv
2023-03-03 19:08 ` Tommaso Merciai
2023-03-06  3:29   ` Hal Feng
2023-03-06 10:22     ` Tommaso Merciai
2023-03-07  8:36 ` Hal Feng
2023-03-07  8:51   ` Conor Dooley
2023-03-07 10:08     ` Hal Feng
2023-03-08 12:28       ` Tommaso Merciai
2023-03-08 13:36         ` Conor Dooley
2023-03-09 16:49           ` Tommaso Merciai
2023-03-09 17:52             ` Conor Dooley [this message]
2023-03-09 18:58               ` Tommaso Merciai
2023-03-09 19:03                 ` Conor Dooley
2023-03-10  7:48                   ` Tommaso Merciai

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