Re: [PATCH v4 2/3] drm/tidss: Update infrastructure to support K3 DSS cut-down versions

[Devarsh Thakkar <devarsht@ti.com>]

Hi Tomi

Thanks for the review. I had missed to respond back to below comment
before sending V5, so kindly find the response for the same as below.

On 27/03/25 16:48, Tomi Valkeinen wrote:

>> *dispc, u32 hw_plane,
>>                  const struct drm_plane_state *state,
>>                  u32 hw_videoport)
>>   {
>> -    bool lite = dispc->feat->vid_lite[hw_plane];
>> +    bool lite = dispc->feat->vid_info[hw_plane].is_lite;
>>       u32 fourcc = state->fb->format->format;
>>       u16 cpp = state->fb->format->cpp[0];
>>       u32 fb_width = state->fb->pitches[0] / cpp;
>> @@ -2210,7 +2275,7 @@ static void dispc_k2g_plane_init(struct
>> dispc_device *dispc)
>>       /* MFLAG_START = MFLAGNORMALSTARTMODE */
>>       REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6);
>>   -    for (hw_plane = 0; hw_plane < dispc->feat->num_planes;
>> hw_plane++) {
>> +    for (hw_plane = 0; hw_plane < dispc->feat->num_vids; hw_plane++) {
>>           u32 size = dispc_vid_get_fifo_size(dispc, hw_plane);
> 
> And here.
> 

I don't think we need to us hw_id for dispc_vid* functions as they
directly act on VID register base which is mapped based on device-tree.
So for e.g. if an SoC does not have VID0 then it won't map that register
base at all. For e.g. AM62L does not have VID region and has only VIDL
so to access VIDL base (which is the first vid region mapped hence index
0) we only need to use hw_plane as index 0

 void __iomem *base = dispc->base_vid[hw_plane];

The hw_id is only required for dispc_k3_vid* functions which access
common register space for vid* specific registers and bits. For e.g.
AM62L does not have VID base so there is a hole there and after 0x4
offset (i.e. at index 1) VIDL starts, so in this case we need to pass
hw_id as 1 (from vid_info struct).

Regards
Devarsh