From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73AF9C7EE23 for ; Tue, 23 May 2023 08:11:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230487AbjEWIKi (ORCPT ); Tue, 23 May 2023 04:10:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236212AbjEWIKB (ORCPT ); Tue, 23 May 2023 04:10:01 -0400 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36F4F170A for ; Tue, 23 May 2023 01:09:18 -0700 (PDT) Received: by mail-ed1-x52f.google.com with SMTP id 4fb4d7f45d1cf-50bcb229adaso1004767a12.2 for ; Tue, 23 May 2023 01:09:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684829348; x=1687421348; h=content-transfer-encoding:in-reply-to:subject:from:references:cc:to :content-language:user-agent:mime-version:date:message-id:from:to:cc :subject:date:message-id:reply-to; bh=h/aoipumKtjIgmVBCWgRH2IIEC1OCL6rlPm9b4d5hh0=; b=FPB3vccv0MbejywaqKBaLLrCmXWBfPSBcEc6wfvA2oPtlHmEek4Zm0mLhNtXaMcUpd mVU7WJXZYwYsHahkbadZtk0SkyjDmHN9toDMzECABaMA9iCqeLjCw53+xlhAaLWUlPjV AzZ/0O01z5OH4kXdUG1Y1f5x9mxOOddB+6sv9OTP0rXvLXMxvr0E+hkUM9Z4eyXLwjL/ XtqsCTCjDo84nFlJSfpFKX7M+YZF+IoqsN/Nz8KXzEdP3iMj+u37DucEpiwdIBv4k3Px 6FPH7vEdYldebvvDZqzrZcjotXMOzYpiYGrxO1HAplTVnWKFTa8TN4ZsysMqcQzZ+nLq 4wQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684829348; x=1687421348; h=content-transfer-encoding:in-reply-to:subject:from:references:cc:to :content-language:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=h/aoipumKtjIgmVBCWgRH2IIEC1OCL6rlPm9b4d5hh0=; b=GgGUKZ121pm4Qsoe9RNcSDtytAox+gFztKv2J91dQTZiIJ7azdUynJy7WABTnO8/eT rBHxZQKRT+vwAyfkCeXI0HjGMgWY/uCtT7Z3CiVZVvFXSQ4r75fQlGzCPPKVQzv2wyJF w2uuKsbmxNQqBI0K7ocM0mONhH2uf0RVpnMU8qk7TX9oeFqRkfK8ht6UXhNJQBx3tDkA iC/UcAKDy9px1+19d4DADZ5DCbTSL/4IqPVQzV8N3WuifVgzpKzBy7CoXiE9ZR5sna64 sDwlyO10GflIwgERHsE0XO4IEBYhhNTsSVRgUD1OhyerbK53M+xx1OAaezjFyg4PfAH8 TBmA== X-Gm-Message-State: AC+VfDzlXCifRl+vt2czU9ser3kumBSnYR/vHUJpIWLBVyA3cjB4hZHd ZGwseoC1TGvksppdcMvEqTCbplFmIxf1Nm0hWRs= X-Google-Smtp-Source: ACHHUZ4hBzBfGUkzVb30MbKl54siE4/TDVUICuxRJ347mzFww1b7qcAvP1rxrghl9gmrYfd6X7qPlQ== X-Received: by 2002:a05:6512:510:b0:4f3:8196:80c8 with SMTP id o16-20020a056512051000b004f3819680c8mr3993040lfb.1.1684828794784; Tue, 23 May 2023 00:59:54 -0700 (PDT) Received: from [192.168.1.101] (abyk138.neoplus.adsl.tpnet.pl. [83.9.30.138]) by smtp.gmail.com with ESMTPSA id p4-20020a2e9ac4000000b002a774fb7923sm1522807ljj.45.2023.05.23.00.59.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 23 May 2023 00:59:54 -0700 (PDT) Message-ID: <097944b0-fa7a-ad4d-1c3d-e74ab2b977de@linaro.org> Date: Tue, 23 May 2023 09:59:53 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Content-Language: en-US To: Bjorn Andersson , Bjorn Andersson Cc: Rob Clark , Dmitry Baryshkov , Sean Paul , Akhil P Oommen , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, johan@kernel.org, mani@kernel.org References: <20230523011522.65351-1-quic_bjorande@quicinc.com> <20230523011522.65351-3-quic_bjorande@quicinc.com> From: Konrad Dybcio Subject: Re: [PATCH v2 2/3] arm64: dts: qcom: sc8280xp: Add GPU related nodes In-Reply-To: <20230523011522.65351-3-quic_bjorande@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 23.05.2023 03:15, Bjorn Andersson wrote: > From: Bjorn Andersson > > Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the > SC8280XP. > > Signed-off-by: Bjorn Andersson > Signed-off-by: Bjorn Andersson > --- It does not look like you tested the DTS against bindings. Please run `make dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst for instructions). > > Changes since v1: > - Dropped gmu_pdc_seq region from &gmu, as it shouldn't have been used. > - Added missing compatible to &adreno_smmu. > - Dropped aoss_qmp clock in &gmu and &adreno_smmu. > > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 169 +++++++++++++++++++++++++ > 1 file changed, 169 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > index d2a2224d138a..329ec2119ecf 100644 > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > @@ -6,6 +6,7 @@ > > #include > #include > +#include > #include > #include > #include > @@ -2331,6 +2332,174 @@ tcsr: syscon@1fc0000 { > reg = <0x0 0x01fc0000 0x0 0x30000>; > }; > > + gpu: gpu@3d00000 { > + compatible = "qcom,adreno-690.0", "qcom,adreno"; > + > + reg = <0 0x03d00000 0 0x40000>, > + <0 0x03d9e000 0 0x1000>, > + <0 0x03d61000 0 0x800>; > + reg-names = "kgsl_3d0_reg_memory", > + "cx_mem", > + "cx_dbgc"; > + interrupts = ; > + iommus = <&adreno_smmu 0 0xc00>, <&adreno_smmu 1 0xc00>; > + operating-points-v2 = <&gpu_opp_table>; > + > + qcom,gmu = <&gmu>; > + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = "gfx-mem"; > + #cooling-cells = <2>; > + > + status = "disabled"; > + > + gpu_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-270000000 { > + opp-hz = /bits/ 64 <270000000>; > + opp-level = ; > + opp-peak-kBps = <451000>; > + }; > + > + opp-410000000 { > + opp-hz = /bits/ 64 <410000000>; > + opp-level = ; > + opp-peak-kBps = <1555000>; > + }; > + > + opp-500000000 { > + opp-hz = /bits/ 64 <500000000>; > + opp-level = ; > + opp-peak-kBps = <1555000>; > + }; > + > + opp-547000000 { > + opp-hz = /bits/ 64 <547000000>; > + opp-level = ; > + opp-peak-kBps = <1555000>; > + }; > + > + opp-606000000 { > + opp-hz = /bits/ 64 <606000000>; > + opp-level = ; > + opp-peak-kBps = <2736000>; > + }; > + > + opp-640000000 { > + opp-hz = /bits/ 64 <640000000>; > + opp-level = ; > + opp-peak-kBps = <2736000>; > + }; > + > + opp-690000000 { > + opp-hz = /bits/ 64 <690000000>; > + opp-level = ; > + opp-peak-kBps = <2736000>; > + }; > + }; > + }; > + > + gmu: gmu@3d6a000 { > + compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu"; > + reg = <0 0x03d6a000 0 0x34000>, > + <0 0x03de0000 0 0x10000>, > + <0 0x0b290000 0 0x10000>; > + reg-names = "gmu", "rscc", "gmu_pdc"; > + interrupts = , > + ; > + interrupt-names = "hfi", "gmu"; > + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, > + <&gpucc GPU_CC_CXO_CLK>, > + <&gcc GCC_DDRSS_GPU_AXI_CLK>, > + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, > + <&gpucc GPU_CC_AHB_CLK>, > + <&gpucc GPU_CC_HUB_CX_INT_CLK>, > + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; > + clock-names = "gmu", > + "cxo", > + "axi", > + "memnoc", > + "ahb", > + "hub", > + "smmu_vote"; > + power-domains = <&gpucc GPU_CC_CX_GDSC>, > + <&gpucc GPU_CC_GX_GDSC>; > + power-domain-names = "cx", > + "gx"; > + iommus = <&adreno_smmu 5 0xc00>; > + operating-points-v2 = <&gmu_opp_table>; > + > + status = "disabled"; I've recently discovered that - and I am not 100% sure - all GMUs are cache-coherent. Could you please ask somebody at qc about this? > + > + gmu_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + opp-level = ; > + }; Missing 500MHz + RPMH_REGULATOR_LEVEL_SVS (that may be used in the future for hw scheduling) > + }; > + }; > + > + gpucc: clock-controller@3d90000 { > + compatible = "qcom,sc8280xp-gpucc"; > + reg = <0 0x03d90000 0 0x9000>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_GPU_GPLL0_CLK_SRC>, > + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; > + clock-names = "bi_tcxo", > + "gcc_gpu_gpll0_clk_src", > + "gcc_gpu_gpll0_div_clk_src"; FWIW the driver doesn't use clock-names, but the binding defines it, so I suppose it's fine > + > + power-domains = <&rpmhpd SC8280XP_GFX>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + > + status = "disabled"; > + }; > + > + adreno_smmu: iommu@3da0000 { > + compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", > + "qcom,smmu-500", "arm,mmu-500"; > + reg = <0 0x03da0000 0 0x20000>; > + #iommu-cells = <2>; > + #global-interrupts = <2>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + > + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, > + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, > + <&gpucc GPU_CC_AHB_CLK>, > + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, > + <&gpucc GPU_CC_CX_GMU_CLK>, > + <&gpucc GPU_CC_HUB_CX_INT_CLK>, > + <&gpucc GPU_CC_HUB_AON_CLK>; > + clock-names = "gcc_gpu_memnoc_gfx_clk", > + "gcc_gpu_snoc_dvm_gfx_clk", > + "gpu_cc_ahb_clk", > + "gpu_cc_hlos1_vote_gpu_smmu_clk", > + "gpu_cc_cx_gmu_clk", > + "gpu_cc_hub_cx_int_clk", > + "gpu_cc_hub_aon_clk"; > + > + power-domains = <&gpucc GPU_CC_CX_GDSC>; > + > + status = "disabled"; This one should be dma-coherent (per downstream, plus 8350's mmu is for sure) Konrad > + }; > + > usb_0_hsphy: phy@88e5000 { > compatible = "qcom,sc8280xp-usb-hs-phy", > "qcom,usb-snps-hs-5nm-phy";