* [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-09-24 23:14 [PATCH 0/8] media: iris: add support for video codecs on Qcom kaanapali platform Vikash Garodia
@ 2025-09-24 23:14 ` Vikash Garodia
2025-09-25 3:06 ` Dmitry Baryshkov
` (3 more replies)
2025-09-24 23:14 ` [PATCH 2/8] media: iris: Add support for multiple clock sources Vikash Garodia
` (6 subsequent siblings)
7 siblings, 4 replies; 54+ messages in thread
From: Vikash Garodia @ 2025-09-24 23:14 UTC (permalink / raw)
To: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy, Vikash Garodia
Kaanapali SOC brings in the new generation of video IP i.e iris4. When
compared to previous generation, iris3x, it has,
- separate power domains for stream and pixel processing hardware blocks
(bse and vpp).
- additional power domain for apv codec.
- power domains for individual pipes (VPPx).
- different clocks and reset lines.
There are variants of this hardware, where only a single VPP pipe would
be functional (VPP0), and APV may not be present. In such case, the
hardware can be enabled without those 2 related power doamins, and
corresponding clocks. This explains the min entries for power domains
and clocks.
Iommus include all the different stream-ids which can be possibly
generated by vpu4 video hardware in both secure and non secure
execution mode.
This patch depends on following patches
https://lore.kernel.org/all/20250924-knp-interconnect-v1-1-4c822a72141c@oss.qualcomm.com/
https://lore.kernel.org/all/20250924-knp-clk-v1-3-29b02b818782@oss.qualcomm.com/
Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
---
.../bindings/media/qcom,kaanapali-iris.yaml | 236 +++++++++++++++++++++
1 file changed, 236 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..f3528d514fe29771227bee5f156962fedb1ea9cd
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
@@ -0,0 +1,236 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,kaanapali-iris.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm kaanapali iris video encode and decode accelerators
+
+maintainers:
+ - Vikash Garodia <vikash.garodia@oss.qualcomm.com>
+ - Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
+
+description:
+ The iris video processing unit is a video encode and decode accelerator
+ present on Qualcomm platforms.
+
+properties:
+ compatible:
+ const: qcom,kaanapali-iris
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ minItems: 5
+ maxItems: 7
+
+ power-domain-names:
+ items:
+ - const: venus
+ - const: vcodec0
+ - const: vpp0
+ - const: vpp1
+ - const: apv
+ - const: mxc
+ - const: mmcx
+
+ clocks:
+ minItems: 8
+ maxItems: 10
+
+ clock-names:
+ items:
+ - const: iface
+ - const: core
+ - const: vcodec0_core
+ - const: iface1
+ - const: core_freerun
+ - const: vcodec0_core_freerun
+ - const: vcodec_bse
+ - const: vcodec_vpp0
+ - const: vcodec_vpp1
+ - const: vcodec_apv
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: cpu-cfg
+ - const: video-mem
+
+ resets:
+ maxItems: 4
+
+ reset-names:
+ items:
+ - const: bus0
+ - const: bus1
+ - const: core_freerun_reset
+ - const: vcodec0_core_freerun_reset
+
+ iommus:
+ minItems: 3
+ maxItems: 8
+
+ memory-region:
+ maxItems: 1
+
+ dma-coherent: true
+
+ operating-points-v2: true
+
+ opp-table:
+ type: object
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - power-domain-names
+ - clocks
+ - clock-names
+ - interconnects
+ - interconnect-names
+ - resets
+ - reset-names
+ - iommus
+ - dma-coherent
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,kaanapali-gcc.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ video-codec@2000000 {
+ compatible = "qcom,kaanapali-iris";
+
+ reg = <0x02000000 0xf0000>;
+
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ power-domains = <&video_cc_mvs0c_gdsc>,
+ <&video_cc_mvs0_gdsc>,
+ <&video_cc_mvs0_vpp0_gdsc>,
+ <&video_cc_mvs0_vpp1_gdsc>,
+ <&video_cc_mvs0a_gdsc>,
+ <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_MMCX>;
+ power-domain-names = "venus",
+ "vcodec0",
+ "vpp0",
+ "vpp1",
+ "apv",
+ "mxc",
+ "mmcx";
+
+ operating-points-v2 = <&iris_opp_table>;
+
+ clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+ <&video_cc_mvs0c_clk>,
+ <&video_cc_mvs0_clk>,
+ <&gcc GCC_VIDEO_AXI1_CLK>,
+ <&video_cc_mvs0c_freerun_clk>,
+ <&video_cc_mvs0_freerun_clk>,
+ <&video_cc_mvs0b_clk>,
+ <&video_cc_mvs0_vpp0_clk>,
+ <&video_cc_mvs0_vpp1_clk>,
+ <&video_cc_mvs0a_clk>;
+ clock-names = "iface",
+ "core",
+ "vcodec0_core",
+ "iface1",
+ "core_freerun",
+ "vcodec0_core_freerun",
+ "vcodec_bse",
+ "vcodec_vpp0",
+ "vcodec_vpp1",
+ "vcodec_apv";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "cpu-cfg",
+ "video-mem";
+
+ memory-region = <&video_mem>;
+
+ resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
+ <&gcc GCC_VIDEO_AXI1_CLK_ARES>,
+ <&video_cc_mvs0c_freerun_clk_ares>,
+ <&video_cc_mvs0_freerun_clk_ares>;
+ reset-names = "bus0",
+ "bus1",
+ "core_freerun_reset",
+ "vcodec0_core_freerun_reset";
+
+ iommus = <&apps_smmu 0x1940 0x0>,
+ <&apps_smmu 0x1943 0x0>,
+ <&apps_smmu 0x1944 0x0>,
+ <&apps_smmu 0x1a20 0x0>;
+
+ dma-coherent;
+
+ iris_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-240000000 {
+ opp-hz = /bits/ 64 <240000000 240000000 240000000 360000000>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-338000000 {
+ opp-hz = /bits/ 64 <338000000 338000000 338000000 507000000>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-420000000 {
+ opp-hz = /bits/ 64 <420000000 420000000 420000000 630000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs>;
+ };
+
+ opp-444000000 {
+ opp-hz = /bits/ 64 <444000000 444000000 444000000 666000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-533000000 {
+ opp-hz = /bits/ 64 <533000000 533000000 533000000 800000000>;
+ required-opps = <&rpmhpd_opp_nom>,
+ <&rpmhpd_opp_nom>;
+ };
+
+ opp-630000000 {
+ opp-hz = /bits/ 64 <630000000 630000000 630000000 1104000000>;
+ required-opps = <&rpmhpd_opp_turbo>,
+ <&rpmhpd_opp_turbo>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000 630000000 630000000 1260000000>;
+ required-opps = <&rpmhpd_opp_turbo_l0>,
+ <&rpmhpd_opp_turbo_l0>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000 630000000 850000000 1260000000>;
+ required-opps = <&rpmhpd_opp_turbo_l1>,
+ <&rpmhpd_opp_turbo_l1>;
+ };
+ };
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-09-24 23:14 ` [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding Vikash Garodia
@ 2025-09-25 3:06 ` Dmitry Baryshkov
2025-09-25 7:57 ` Vikash Garodia
2025-09-25 5:11 ` Rob Herring (Arm)
` (2 subsequent siblings)
3 siblings, 1 reply; 54+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 3:06 UTC (permalink / raw)
To: Vikash Garodia
Cc: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, linux-arm-msm, linux-media,
devicetree, linux-kernel, Vishnu Reddy
On Thu, Sep 25, 2025 at 04:44:39AM +0530, Vikash Garodia wrote:
> Kaanapali SOC brings in the new generation of video IP i.e iris4. When
> compared to previous generation, iris3x, it has,
> - separate power domains for stream and pixel processing hardware blocks
> (bse and vpp).
> - additional power domain for apv codec.
> - power domains for individual pipes (VPPx).
> - different clocks and reset lines.
>
> There are variants of this hardware, where only a single VPP pipe would
> be functional (VPP0), and APV may not be present. In such case, the
> hardware can be enabled without those 2 related power doamins, and
> corresponding clocks. This explains the min entries for power domains
> and clocks.
> Iommus include all the different stream-ids which can be possibly
> generated by vpu4 video hardware in both secure and non secure
> execution mode.
>
> This patch depends on following patches
> https://lore.kernel.org/all/20250924-knp-interconnect-v1-1-4c822a72141c@oss.qualcomm.com/
> https://lore.kernel.org/all/20250924-knp-clk-v1-3-29b02b818782@oss.qualcomm.com/
This doesn't belong to the commit message. But you also can drop this
dependency alltogether. Could you please do it?
>
> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> ---
> .../bindings/media/qcom,kaanapali-iris.yaml | 236 +++++++++++++++++++++
> 1 file changed, 236 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..f3528d514fe29771227bee5f156962fedb1ea9cd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
> @@ -0,0 +1,236 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/qcom,kaanapali-iris.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm kaanapali iris video encode and decode accelerators
> +
> +maintainers:
> + - Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> + - Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
> +
> +description:
> + The iris video processing unit is a video encode and decode accelerator
> + present on Qualcomm platforms.
> +
> +properties:
> + compatible:
> + const: qcom,kaanapali-iris
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + power-domains:
> + minItems: 5
> + maxItems: 7
> +
> + power-domain-names:
> + items:
> + - const: venus
> + - const: vcodec0
> + - const: vpp0
> + - const: vpp1
> + - const: apv
> + - const: mxc
> + - const: mmcx
> +
> + clocks:
> + minItems: 8
> + maxItems: 10
> +
> + clock-names:
> + items:
> + - const: iface
> + - const: core
> + - const: vcodec0_core
> + - const: iface1
> + - const: core_freerun
> + - const: vcodec0_core_freerun
> + - const: vcodec_bse
> + - const: vcodec_vpp0
> + - const: vcodec_vpp1
> + - const: vcodec_apv
> +
> + interconnects:
> + maxItems: 2
> +
> + interconnect-names:
> + items:
> + - const: cpu-cfg
> + - const: video-mem
> +
> + resets:
> + maxItems: 4
> +
> + reset-names:
> + items:
> + - const: bus0
> + - const: bus1
> + - const: core_freerun_reset
> + - const: vcodec0_core_freerun_reset
> +
> + iommus:
> + minItems: 3
> + maxItems: 8
> +
> + memory-region:
> + maxItems: 1
> +
> + dma-coherent: true
> +
> + operating-points-v2: true
> +
> + opp-table:
> + type: object
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - power-domains
> + - power-domain-names
> + - clocks
> + - clock-names
> + - interconnects
> + - interconnect-names
> + - resets
> + - reset-names
> + - iommus
> + - dma-coherent
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/qcom,kaanapali-gcc.h>
> + #include <dt-bindings/interconnect/qcom,icc.h>
> + #include <dt-bindings/power/qcom,rpmhpd.h>
> +
> + video-codec@2000000 {
> + compatible = "qcom,kaanapali-iris";
> +
> + reg = <0x02000000 0xf0000>;
> +
> + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
> +
> + power-domains = <&video_cc_mvs0c_gdsc>,
> + <&video_cc_mvs0_gdsc>,
> + <&video_cc_mvs0_vpp0_gdsc>,
> + <&video_cc_mvs0_vpp1_gdsc>,
> + <&video_cc_mvs0a_gdsc>,
> + <&rpmhpd RPMHPD_MXC>,
> + <&rpmhpd RPMHPD_MMCX>;
> + power-domain-names = "venus",
> + "vcodec0",
> + "vpp0",
> + "vpp1",
> + "apv",
> + "mxc",
> + "mmcx";
> +
> + operating-points-v2 = <&iris_opp_table>;
> +
> + clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
> + <&video_cc_mvs0c_clk>,
> + <&video_cc_mvs0_clk>,
> + <&gcc GCC_VIDEO_AXI1_CLK>,
> + <&video_cc_mvs0c_freerun_clk>,
> + <&video_cc_mvs0_freerun_clk>,
> + <&video_cc_mvs0b_clk>,
> + <&video_cc_mvs0_vpp0_clk>,
> + <&video_cc_mvs0_vpp1_clk>,
> + <&video_cc_mvs0a_clk>;
> + clock-names = "iface",
> + "core",
> + "vcodec0_core",
> + "iface1",
> + "core_freerun",
> + "vcodec0_core_freerun",
> + "vcodec_bse",
> + "vcodec_vpp0",
> + "vcodec_vpp1",
> + "vcodec_apv";
> +
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "cpu-cfg",
> + "video-mem";
> +
> + memory-region = <&video_mem>;
> +
> + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
> + <&gcc GCC_VIDEO_AXI1_CLK_ARES>,
> + <&video_cc_mvs0c_freerun_clk_ares>,
> + <&video_cc_mvs0_freerun_clk_ares>;
> + reset-names = "bus0",
> + "bus1",
> + "core_freerun_reset",
> + "vcodec0_core_freerun_reset";
> +
> + iommus = <&apps_smmu 0x1940 0x0>,
> + <&apps_smmu 0x1943 0x0>,
> + <&apps_smmu 0x1944 0x0>,
> + <&apps_smmu 0x1a20 0x0>;
> +
> + dma-coherent;
> +
> + iris_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-240000000 {
> + opp-hz = /bits/ 64 <240000000 240000000 240000000 360000000>;
> + required-opps = <&rpmhpd_opp_low_svs>,
> + <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-338000000 {
> + opp-hz = /bits/ 64 <338000000 338000000 338000000 507000000>;
> + required-opps = <&rpmhpd_opp_low_svs>,
> + <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-420000000 {
> + opp-hz = /bits/ 64 <420000000 420000000 420000000 630000000>;
> + required-opps = <&rpmhpd_opp_svs>,
> + <&rpmhpd_opp_svs>;
> + };
> +
> + opp-444000000 {
> + opp-hz = /bits/ 64 <444000000 444000000 444000000 666000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>,
> + <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-533000000 {
> + opp-hz = /bits/ 64 <533000000 533000000 533000000 800000000>;
> + required-opps = <&rpmhpd_opp_nom>,
> + <&rpmhpd_opp_nom>;
> + };
> +
> + opp-630000000 {
> + opp-hz = /bits/ 64 <630000000 630000000 630000000 1104000000>;
> + required-opps = <&rpmhpd_opp_turbo>,
> + <&rpmhpd_opp_turbo>;
> + };
> +
> + opp-800000000 {
> + opp-hz = /bits/ 64 <800000000 630000000 630000000 1260000000>;
> + required-opps = <&rpmhpd_opp_turbo_l0>,
> + <&rpmhpd_opp_turbo_l0>;
> + };
> +
> + opp-1000000000 {
> + opp-hz = /bits/ 64 <1000000000 630000000 850000000 1260000000>;
> + required-opps = <&rpmhpd_opp_turbo_l1>,
> + <&rpmhpd_opp_turbo_l1>;
> + };
> + };
> + };
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-09-25 3:06 ` Dmitry Baryshkov
@ 2025-09-25 7:57 ` Vikash Garodia
2025-09-25 8:59 ` Konrad Dybcio
2025-09-25 19:20 ` Dmitry Baryshkov
0 siblings, 2 replies; 54+ messages in thread
From: Vikash Garodia @ 2025-09-25 7:57 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, linux-arm-msm, linux-media,
devicetree, linux-kernel, Vishnu Reddy
On 9/25/2025 8:36 AM, Dmitry Baryshkov wrote:
> On Thu, Sep 25, 2025 at 04:44:39AM +0530, Vikash Garodia wrote:
>> Kaanapali SOC brings in the new generation of video IP i.e iris4. When
>> compared to previous generation, iris3x, it has,
>> - separate power domains for stream and pixel processing hardware blocks
>> (bse and vpp).
>> - additional power domain for apv codec.
>> - power domains for individual pipes (VPPx).
>> - different clocks and reset lines.
>>
>> There are variants of this hardware, where only a single VPP pipe would
>> be functional (VPP0), and APV may not be present. In such case, the
>> hardware can be enabled without those 2 related power doamins, and
>> corresponding clocks. This explains the min entries for power domains
>> and clocks.
>> Iommus include all the different stream-ids which can be possibly
>> generated by vpu4 video hardware in both secure and non secure
>> execution mode.
>>
>> This patch depends on following patches
>> https://lore.kernel.org/all/20250924-knp-interconnect-v1-1-4c822a72141c@oss.qualcomm.com/
>> https://lore.kernel.org/all/20250924-knp-clk-v1-3-29b02b818782@oss.qualcomm.com/
>
> This doesn't belong to the commit message. But you also can drop this
> dependency alltogether. Could you please do it?
Sure, i see below works good w.r.t schema and dtb checker. Please review and
confirm.
diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
index f3528d514fe2..537e8d627a72 100644
--- a/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
+++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
@@ -106,9 +106,7 @@ unevaluatedProperties: false
examples:
- |
- #include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/qcom,kaanapali-gcc.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
@@ -136,10 +134,10 @@ examples:
operating-points-v2 = <&iris_opp_table>;
- clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+ clocks = <&gcc_video_axi0_clk>,
<&video_cc_mvs0c_clk>,
<&video_cc_mvs0_clk>,
- <&gcc GCC_VIDEO_AXI1_CLK>,
+ <&gcc_video_axi1_clk>,
<&video_cc_mvs0c_freerun_clk>,
<&video_cc_mvs0_freerun_clk>,
<&video_cc_mvs0b_clk>,
@@ -157,17 +155,15 @@ examples:
"vcodec_vpp1",
"vcodec_apv";
- interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
- &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
- <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnects = <&gem_noc_master_appss_proc &config_noc_slave_venus_cfg>,
+ <&mmss_noc_master_video_mvp &mc_virt_slave_ebi1>;
interconnect-names = "cpu-cfg",
"video-mem";
memory-region = <&video_mem>;
- resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
- <&gcc GCC_VIDEO_AXI1_CLK_ARES>,
+ resets = <&gcc_video_axi0_clk_ares>,
+ <&gcc_video_axi1_clk_ares>,
Regards,
Vikash
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-09-25 7:57 ` Vikash Garodia
@ 2025-09-25 8:59 ` Konrad Dybcio
2025-09-25 19:09 ` Vikash Garodia
2025-09-25 19:20 ` Dmitry Baryshkov
1 sibling, 1 reply; 54+ messages in thread
From: Konrad Dybcio @ 2025-09-25 8:59 UTC (permalink / raw)
To: Vikash Garodia, Dmitry Baryshkov
Cc: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, linux-arm-msm, linux-media,
devicetree, linux-kernel, Vishnu Reddy
On 9/25/25 9:57 AM, Vikash Garodia wrote:
>
> On 9/25/2025 8:36 AM, Dmitry Baryshkov wrote:
>> On Thu, Sep 25, 2025 at 04:44:39AM +0530, Vikash Garodia wrote:
>>> Kaanapali SOC brings in the new generation of video IP i.e iris4. When
>>> compared to previous generation, iris3x, it has,
>>> - separate power domains for stream and pixel processing hardware blocks
>>> (bse and vpp).
>>> - additional power domain for apv codec.
>>> - power domains for individual pipes (VPPx).
>>> - different clocks and reset lines.
>>>
>>> There are variants of this hardware, where only a single VPP pipe would
>>> be functional (VPP0), and APV may not be present. In such case, the
>>> hardware can be enabled without those 2 related power doamins, and
>>> corresponding clocks. This explains the min entries for power domains
>>> and clocks.
>>> Iommus include all the different stream-ids which can be possibly
>>> generated by vpu4 video hardware in both secure and non secure
>>> execution mode.
>>>
>>> This patch depends on following patches
>>> https://lore.kernel.org/all/20250924-knp-interconnect-v1-1-4c822a72141c@oss.qualcomm.com/
>>> https://lore.kernel.org/all/20250924-knp-clk-v1-3-29b02b818782@oss.qualcomm.com/
>>
>> This doesn't belong to the commit message. But you also can drop this
>> dependency alltogether. Could you please do it?
>
> Sure, i see below works good w.r.t schema and dtb checker. Please review and
> confirm.
lgtm, you can also drop the interconnect header (i think you don't
need any rpmhpd additions so it can stay - potayto/potahto)
Konrad
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
> b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
> index f3528d514fe2..537e8d627a72 100644
> --- a/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
> +++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
> @@ -106,9 +106,7 @@ unevaluatedProperties: false
>
> examples:
> - |
> - #include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> - #include <dt-bindings/clock/qcom,kaanapali-gcc.h>
> #include <dt-bindings/interconnect/qcom,icc.h>
> #include <dt-bindings/power/qcom,rpmhpd.h>
>
> @@ -136,10 +134,10 @@ examples:
>
> operating-points-v2 = <&iris_opp_table>;
>
> - clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
> + clocks = <&gcc_video_axi0_clk>,
> <&video_cc_mvs0c_clk>,
> <&video_cc_mvs0_clk>,
> - <&gcc GCC_VIDEO_AXI1_CLK>,
> + <&gcc_video_axi1_clk>,
> <&video_cc_mvs0c_freerun_clk>,
> <&video_cc_mvs0_freerun_clk>,
> <&video_cc_mvs0b_clk>,
> @@ -157,17 +155,15 @@ examples:
> "vcodec_vpp1",
> "vcodec_apv";
>
> - interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> - &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
> - <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS
> - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> + interconnects = <&gem_noc_master_appss_proc &config_noc_slave_venus_cfg>,
> + <&mmss_noc_master_video_mvp &mc_virt_slave_ebi1>;
> interconnect-names = "cpu-cfg",
> "video-mem";
>
> memory-region = <&video_mem>;
>
> - resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
> - <&gcc GCC_VIDEO_AXI1_CLK_ARES>,
> + resets = <&gcc_video_axi0_clk_ares>,
> + <&gcc_video_axi1_clk_ares>,
>
> Regards,
> Vikash
>
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-09-25 8:59 ` Konrad Dybcio
@ 2025-09-25 19:09 ` Vikash Garodia
0 siblings, 0 replies; 54+ messages in thread
From: Vikash Garodia @ 2025-09-25 19:09 UTC (permalink / raw)
To: Konrad Dybcio, Dmitry Baryshkov
Cc: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, linux-arm-msm, linux-media,
devicetree, linux-kernel, Vishnu Reddy
On 9/25/2025 2:29 PM, Konrad Dybcio wrote:
> On 9/25/25 9:57 AM, Vikash Garodia wrote:
>>
>> On 9/25/2025 8:36 AM, Dmitry Baryshkov wrote:
>>> On Thu, Sep 25, 2025 at 04:44:39AM +0530, Vikash Garodia wrote:
>>>> Kaanapali SOC brings in the new generation of video IP i.e iris4. When
>>>> compared to previous generation, iris3x, it has,
>>>> - separate power domains for stream and pixel processing hardware blocks
>>>> (bse and vpp).
>>>> - additional power domain for apv codec.
>>>> - power domains for individual pipes (VPPx).
>>>> - different clocks and reset lines.
>>>>
>>>> There are variants of this hardware, where only a single VPP pipe would
>>>> be functional (VPP0), and APV may not be present. In such case, the
>>>> hardware can be enabled without those 2 related power doamins, and
>>>> corresponding clocks. This explains the min entries for power domains
>>>> and clocks.
>>>> Iommus include all the different stream-ids which can be possibly
>>>> generated by vpu4 video hardware in both secure and non secure
>>>> execution mode.
>>>>
>>>> This patch depends on following patches
>>>> https://lore.kernel.org/all/20250924-knp-interconnect-v1-1-4c822a72141c@oss.qualcomm.com/
>>>> https://lore.kernel.org/all/20250924-knp-clk-v1-3-29b02b818782@oss.qualcomm.com/
>>>
>>> This doesn't belong to the commit message. But you also can drop this
>>> dependency alltogether. Could you please do it?
>>
>> Sure, i see below works good w.r.t schema and dtb checker. Please review and
>> confirm.
>
> lgtm, you can also drop the interconnect header (i think you don't
> need any rpmhpd additions so it can stay - potayto/potahto)
>
interconnect can be removed as well.
Regards,
Vikash
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-09-25 7:57 ` Vikash Garodia
2025-09-25 8:59 ` Konrad Dybcio
@ 2025-09-25 19:20 ` Dmitry Baryshkov
1 sibling, 0 replies; 54+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 19:20 UTC (permalink / raw)
To: Vikash Garodia
Cc: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, linux-arm-msm, linux-media,
devicetree, linux-kernel, Vishnu Reddy
On Thu, Sep 25, 2025 at 01:27:29PM +0530, Vikash Garodia wrote:
>
> On 9/25/2025 8:36 AM, Dmitry Baryshkov wrote:
> > On Thu, Sep 25, 2025 at 04:44:39AM +0530, Vikash Garodia wrote:
> >> Kaanapali SOC brings in the new generation of video IP i.e iris4. When
> >> compared to previous generation, iris3x, it has,
> >> - separate power domains for stream and pixel processing hardware blocks
> >> (bse and vpp).
> >> - additional power domain for apv codec.
> >> - power domains for individual pipes (VPPx).
> >> - different clocks and reset lines.
> >>
> >> There are variants of this hardware, where only a single VPP pipe would
> >> be functional (VPP0), and APV may not be present. In such case, the
> >> hardware can be enabled without those 2 related power doamins, and
> >> corresponding clocks. This explains the min entries for power domains
> >> and clocks.
> >> Iommus include all the different stream-ids which can be possibly
> >> generated by vpu4 video hardware in both secure and non secure
> >> execution mode.
> >>
> >> This patch depends on following patches
> >> https://lore.kernel.org/all/20250924-knp-interconnect-v1-1-4c822a72141c@oss.qualcomm.com/
> >> https://lore.kernel.org/all/20250924-knp-clk-v1-3-29b02b818782@oss.qualcomm.com/
> >
> > This doesn't belong to the commit message. But you also can drop this
> > dependency alltogether. Could you please do it?
>
> Sure, i see below works good w.r.t schema and dtb checker. Please review and
> confirm.
Yes
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-09-24 23:14 ` [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding Vikash Garodia
2025-09-25 3:06 ` Dmitry Baryshkov
@ 2025-09-25 5:11 ` Rob Herring (Arm)
2025-09-25 9:08 ` Krzysztof Kozlowski
2025-09-25 19:25 ` Dmitry Baryshkov
3 siblings, 0 replies; 54+ messages in thread
From: Rob Herring (Arm) @ 2025-09-25 5:11 UTC (permalink / raw)
To: Vikash Garodia
Cc: Krzysztof Kozlowski, Abhinav Kumar, devicetree, Philipp Zabel,
Conor Dooley, linux-arm-msm, Mauro Carvalho Chehab,
Bryan O'Donoghue, Vishnu Reddy, linux-kernel, linux-media,
Dikshita Agarwal
On Thu, 25 Sep 2025 04:44:39 +0530, Vikash Garodia wrote:
> Kaanapali SOC brings in the new generation of video IP i.e iris4. When
> compared to previous generation, iris3x, it has,
> - separate power domains for stream and pixel processing hardware blocks
> (bse and vpp).
> - additional power domain for apv codec.
> - power domains for individual pipes (VPPx).
> - different clocks and reset lines.
>
> There are variants of this hardware, where only a single VPP pipe would
> be functional (VPP0), and APV may not be present. In such case, the
> hardware can be enabled without those 2 related power doamins, and
> corresponding clocks. This explains the min entries for power domains
> and clocks.
> Iommus include all the different stream-ids which can be possibly
> generated by vpu4 video hardware in both secure and non secure
> execution mode.
>
> This patch depends on following patches
> https://lore.kernel.org/all/20250924-knp-interconnect-v1-1-4c822a72141c@oss.qualcomm.com/
> https://lore.kernel.org/all/20250924-knp-clk-v1-3-29b02b818782@oss.qualcomm.com/
>
> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> ---
> .../bindings/media/qcom,kaanapali-iris.yaml | 236 +++++++++++++++++++++
> 1 file changed, 236 insertions(+)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/media/qcom,kaanapali-iris.example.dts:24:18: fatal error: dt-bindings/interconnect/qcom,kaanapali-rpmh.h: No such file or directory
24 | #include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[2]: *** [scripts/Makefile.dtbs:132: Documentation/devicetree/bindings/media/qcom,kaanapali-iris.example.dtb] Error 1
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1525: dt_binding_check] Error 2
make: *** [Makefile:248: __sub-make] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250925-knp_video-v1-1-e323c0b3c0cd@oss.qualcomm.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-09-24 23:14 ` [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding Vikash Garodia
2025-09-25 3:06 ` Dmitry Baryshkov
2025-09-25 5:11 ` Rob Herring (Arm)
@ 2025-09-25 9:08 ` Krzysztof Kozlowski
2025-09-25 19:23 ` Vikash Garodia
2025-09-25 19:25 ` Dmitry Baryshkov
3 siblings, 1 reply; 54+ messages in thread
From: Krzysztof Kozlowski @ 2025-09-25 9:08 UTC (permalink / raw)
To: Vikash Garodia
Cc: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, linux-arm-msm, linux-media,
devicetree, linux-kernel, Vishnu Reddy
On Thu, 25 Sept 2025 at 08:16, Vikash Garodia
<vikash.garodia@oss.qualcomm.com> wrote:
>
> Kaanapali SOC brings in the new generation of video IP i.e iris4. When
> compared to previous generation, iris3x, it has,
> - separate power domains for stream and pixel processing hardware blocks
> (bse and vpp).
> - additional power domain for apv codec.
> - power domains for individual pipes (VPPx).
> - different clocks and reset lines.
>
> There are variants of this hardware, where only a single VPP pipe would
> be functional (VPP0), and APV may not be present. In such case, the
> hardware can be enabled without those 2 related power doamins, and
> corresponding clocks. This explains the min entries for power domains
> and clocks.
> Iommus include all the different stream-ids which can be possibly
> generated by vpu4 video hardware in both secure and non secure
> execution mode.
>
> This patch depends on following patches
No, it cannot.
Don't send such patches then. We gave you already clear guidance how
this is supposed to be solved.
> https://lore.kernel.org/all/20250924-knp-interconnect-v1-1-4c822a72141c@oss.qualcomm.com/
> https://lore.kernel.org/all/20250924-knp-clk-v1-3-29b02b818782@oss.qualcomm.com/
>
> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> ---
> .../bindings/media/qcom,kaanapali-iris.yaml | 236 +++++++++++++++++++++
> 1 file changed, 236 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..f3528d514fe29771227bee5f156962fedb1ea9cd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
> @@ -0,0 +1,236 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/qcom,kaanapali-iris.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm kaanapali iris video encode and decode accelerators
> +
> +maintainers:
> + - Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> + - Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
> +
> +description:
> + The iris video processing unit is a video encode and decode accelerator
> + present on Qualcomm platforms.
> +
> +properties:
> + compatible:
> + const: qcom,kaanapali-iris
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + power-domains:
> + minItems: 5
> + maxItems: 7
> +
> + power-domain-names:
Wrong constraints, see writing bindings.
> + items:
> + - const: venus
> + - const: vcodec0
> + - const: vpp0
> + - const: vpp1
> + - const: apv
> + - const: mxc
> + - const: mmcx
> +
> + clocks:
> + minItems: 8
> + maxItems: 10
also wrong
> +
> + clock-names:
> + items:
> + - const: iface
> + - const: core
> + - const: vcodec0_core
> + - const: iface1
> + - const: core_freerun
> + - const: vcodec0_core_freerun
> + - const: vcodec_bse
> + - const: vcodec_vpp0
> + - const: vcodec_vpp1
> + - const: vcodec_apv
> +
> + interconnects:
> + maxItems: 2
> +
> + interconnect-names:
> + items:
> + - const: cpu-cfg
> + - const: video-mem
> +
> + resets:
> + maxItems: 4
> +
> + reset-names:
> + items:
> + - const: bus0
> + - const: bus1
> + - const: core_freerun_reset
> + - const: vcodec0_core_freerun_reset
> +
> + iommus:
> + minItems: 3
> + maxItems: 8
No, you need to list the items.
You've been told that already in that discussion.
> +
> + memory-region:
> + maxItems: 1
> +
> + dma-coherent: true
> +
> + operating-points-v2: true
> +
> + opp-table:
> + type: object
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - power-domains
> + - power-domain-names
> + - clocks
> + - clock-names
> + - interconnects
> + - interconnect-names
> + - resets
> + - reset-names
> + - iommus
> + - dma-coherent
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/qcom,kaanapali-gcc.h>
> + #include <dt-bindings/interconnect/qcom,icc.h>
> + #include <dt-bindings/power/qcom,rpmhpd.h>
> +
> + video-codec@2000000 {
> + compatible = "qcom,kaanapali-iris";
> +
Please read dts coding style and look how dts for Qualcomm is written.
> + reg = <0x02000000 0xf0000>;
> +
> + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
> +
> + power-domains = <&video_cc_mvs0c_gdsc>,
,
Krzysztof
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-09-25 9:08 ` Krzysztof Kozlowski
@ 2025-09-25 19:23 ` Vikash Garodia
0 siblings, 0 replies; 54+ messages in thread
From: Vikash Garodia @ 2025-09-25 19:23 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, linux-arm-msm, linux-media,
devicetree, linux-kernel, Vishnu Reddy
On 9/25/2025 2:38 PM, Krzysztof Kozlowski wrote:
> On Thu, 25 Sept 2025 at 08:16, Vikash Garodia
> <vikash.garodia@oss.qualcomm.com> wrote:
>>
>> Kaanapali SOC brings in the new generation of video IP i.e iris4. When
>> compared to previous generation, iris3x, it has,
>> - separate power domains for stream and pixel processing hardware blocks
>> (bse and vpp).
>> - additional power domain for apv codec.
>> - power domains for individual pipes (VPPx).
>> - different clocks and reset lines.
>>
>> There are variants of this hardware, where only a single VPP pipe would
>> be functional (VPP0), and APV may not be present. In such case, the
>> hardware can be enabled without those 2 related power doamins, and
>> corresponding clocks. This explains the min entries for power domains
>> and clocks.
>> Iommus include all the different stream-ids which can be possibly
>> generated by vpu4 video hardware in both secure and non secure
>> execution mode.
>>
>> This patch depends on following patches
>
> No, it cannot.
>
> Don't send such patches then. We gave you already clear guidance how
> this is supposed to be solved.
The dependencies would be removed now in next revision.
>
>
>> https://lore.kernel.org/all/20250924-knp-interconnect-v1-1-4c822a72141c@oss.qualcomm.com/
>> https://lore.kernel.org/all/20250924-knp-clk-v1-3-29b02b818782@oss.qualcomm.com/
>>
>> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
>> ---
>> .../bindings/media/qcom,kaanapali-iris.yaml | 236 +++++++++++++++++++++
>> 1 file changed, 236 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..f3528d514fe29771227bee5f156962fedb1ea9cd
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
>> @@ -0,0 +1,236 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/media/qcom,kaanapali-iris.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm kaanapali iris video encode and decode accelerators
>> +
>> +maintainers:
>> + - Vikash Garodia <vikash.garodia@oss.qualcomm.com>
>> + - Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
>> +
>> +description:
>> + The iris video processing unit is a video encode and decode accelerator
>> + present on Qualcomm platforms.
>> +
>> +properties:
>> + compatible:
>> + const: qcom,kaanapali-iris
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + power-domains:
>> + minItems: 5
>> + maxItems: 7
>> +
>> + power-domain-names:
>
> Wrong constraints, see writing bindings.
Got it, please review if below is fine
power-domains:
minItems: 5
maxItems: 7
description:
Some of the power domains are optional(vpp1 and apv) and depends on the
hardware variants having them or not.
power-domain-names:
minItems: 5
items:
- const: venus
- const: vcodec0
- const: mxc
- const: mmcx
- const: vpp0
- enum: [vpp1, apv]
- enum: [vpp1, apv]
>
>> + items:
>> + - const: venus
>> + - const: vcodec0
>> + - const: vpp0
>> + - const: vpp1
>> + - const: apv
>> + - const: mxc
>> + - const: mmcx
>> +
>> + clocks:
>> + minItems: 8
>> + maxItems: 10
>
> also wrong
Please review if below looks good
clocks:
minItems: 8
maxItems: 10
description:
Some of the clocks are optional(vcodec_vpp1 and vcodec_apv) and depends on
the hardware variants having them or not.
clock-names:
minItems: 8
items:
- const: iface
- const: core
- const: vcodec0_core
- const: iface1
- const: core_freerun
- const: vcodec0_core_freerun
- const: vcodec_bse
- const: vcodec_vpp0
- enum: [vcodec_vpp1, vcodec_apv]
- enum: [vcodec_vpp1, vcodec_apv]
>
>> +
>> + clock-names:
>> + items:
>> + - const: iface
>> + - const: core
>> + - const: vcodec0_core
>> + - const: iface1
>> + - const: core_freerun
>> + - const: vcodec0_core_freerun
>> + - const: vcodec_bse
>> + - const: vcodec_vpp0
>> + - const: vcodec_vpp1
>> + - const: vcodec_apv
>> +
>> + interconnects:
>> + maxItems: 2
>> +
>> + interconnect-names:
>> + items:
>> + - const: cpu-cfg
>> + - const: video-mem
>> +
>> + resets:
>> + maxItems: 4
>> +
>> + reset-names:
>> + items:
>> + - const: bus0
>> + - const: bus1
>> + - const: core_freerun_reset
>> + - const: vcodec0_core_freerun_reset
>> +
>> + iommus:
>> + minItems: 3
>> + maxItems: 8
>
> No, you need to list the items.
Could you please elaborate how this is expected ? any reference would be
appreciated here.
>
> You've been told that already in that discussion.
>
>
>> +
>> + memory-region:
>> + maxItems: 1
>> +
>> + dma-coherent: true
>> +
>> + operating-points-v2: true
>> +
>> + opp-table:
>> + type: object
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - interrupts
>> + - power-domains
>> + - power-domain-names
>> + - clocks
>> + - clock-names
>> + - interconnects
>> + - interconnect-names
>> + - resets
>> + - reset-names
>> + - iommus
>> + - dma-coherent
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h>
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> + #include <dt-bindings/clock/qcom,kaanapali-gcc.h>
>> + #include <dt-bindings/interconnect/qcom,icc.h>
>> + #include <dt-bindings/power/qcom,rpmhpd.h>
>> +
>> + video-codec@2000000 {
>> + compatible = "qcom,kaanapali-iris";
>> +
>
> Please read dts coding style and look how dts for Qualcomm is written.
made the changes w.r.t spacing alignment and alphabetical order, following the
reference of sm8750 iris yaml. It can be reviewed in next revision.
Regards,
Vikash
>
>> + reg = <0x02000000 0xf0000>;
>> +
>> + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + power-domains = <&video_cc_mvs0c_gdsc>,
> ,
> Krzysztof
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-09-24 23:14 ` [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding Vikash Garodia
` (2 preceding siblings ...)
2025-09-25 9:08 ` Krzysztof Kozlowski
@ 2025-09-25 19:25 ` Dmitry Baryshkov
2025-09-25 19:31 ` Vikash Garodia
3 siblings, 1 reply; 54+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 19:25 UTC (permalink / raw)
To: Vikash Garodia
Cc: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, linux-arm-msm, linux-media,
devicetree, linux-kernel, Vishnu Reddy
On Thu, Sep 25, 2025 at 04:44:39AM +0530, Vikash Garodia wrote:
> Kaanapali SOC brings in the new generation of video IP i.e iris4. When
> compared to previous generation, iris3x, it has,
> - separate power domains for stream and pixel processing hardware blocks
> (bse and vpp).
> - additional power domain for apv codec.
> - power domains for individual pipes (VPPx).
> - different clocks and reset lines.
>
> There are variants of this hardware, where only a single VPP pipe would
> be functional (VPP0), and APV may not be present. In such case, the
> hardware can be enabled without those 2 related power doamins, and
> corresponding clocks. This explains the min entries for power domains
> and clocks.
> Iommus include all the different stream-ids which can be possibly
> generated by vpu4 video hardware in both secure and non secure
> execution mode.
>
> This patch depends on following patches
> https://lore.kernel.org/all/20250924-knp-interconnect-v1-1-4c822a72141c@oss.qualcomm.com/
> https://lore.kernel.org/all/20250924-knp-clk-v1-3-29b02b818782@oss.qualcomm.com/
>
> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> ---
> .../bindings/media/qcom,kaanapali-iris.yaml | 236 +++++++++++++++++++++
> 1 file changed, 236 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..f3528d514fe29771227bee5f156962fedb1ea9cd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
> @@ -0,0 +1,236 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/qcom,kaanapali-iris.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm kaanapali iris video encode and decode accelerators
> +
> +maintainers:
> + - Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> + - Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
> +
> +description:
> + The iris video processing unit is a video encode and decode accelerator
> + present on Qualcomm platforms.
> +
> +properties:
> + compatible:
> + const: qcom,kaanapali-iris
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + power-domains:
> + minItems: 5
> + maxItems: 7
You are sending bindings for a single device on a single platform. How
comes that it has min != max?
> +
> + power-domain-names:
> + items:
> + - const: venus
> + - const: vcodec0
> + - const: vpp0
> + - const: vpp1
> + - const: apv
> + - const: mxc
> + - const: mmcx
> +
> + clocks:
> + minItems: 8
> + maxItems: 10
And here.
> +
> + clock-names:
> + items:
> + - const: iface
> + - const: core
> + - const: vcodec0_core
> + - const: iface1
> + - const: core_freerun
> + - const: vcodec0_core_freerun
> + - const: vcodec_bse
> + - const: vcodec_vpp0
> + - const: vcodec_vpp1
> + - const: vcodec_apv
> +
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-09-25 19:25 ` Dmitry Baryshkov
@ 2025-09-25 19:31 ` Vikash Garodia
2025-09-25 19:38 ` Dmitry Baryshkov
0 siblings, 1 reply; 54+ messages in thread
From: Vikash Garodia @ 2025-09-25 19:31 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, linux-arm-msm, linux-media,
devicetree, linux-kernel, Vishnu Reddy
On 9/26/2025 12:55 AM, Dmitry Baryshkov wrote:
> On Thu, Sep 25, 2025 at 04:44:39AM +0530, Vikash Garodia wrote:
>> Kaanapali SOC brings in the new generation of video IP i.e iris4. When
>> compared to previous generation, iris3x, it has,
>> - separate power domains for stream and pixel processing hardware blocks
>> (bse and vpp).
>> - additional power domain for apv codec.
>> - power domains for individual pipes (VPPx).
>> - different clocks and reset lines.
>>
>> There are variants of this hardware, where only a single VPP pipe would
>> be functional (VPP0), and APV may not be present. In such case, the
>> hardware can be enabled without those 2 related power doamins, and
>> corresponding clocks. This explains the min entries for power domains
>> and clocks.
>> Iommus include all the different stream-ids which can be possibly
>> generated by vpu4 video hardware in both secure and non secure
>> execution mode.
>>
>> This patch depends on following patches
>> https://lore.kernel.org/all/20250924-knp-interconnect-v1-1-4c822a72141c@oss.qualcomm.com/
>> https://lore.kernel.org/all/20250924-knp-clk-v1-3-29b02b818782@oss.qualcomm.com/
>>
>> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
>> ---
>> .../bindings/media/qcom,kaanapali-iris.yaml | 236 +++++++++++++++++++++
>> 1 file changed, 236 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..f3528d514fe29771227bee5f156962fedb1ea9cd
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
>> @@ -0,0 +1,236 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/media/qcom,kaanapali-iris.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm kaanapali iris video encode and decode accelerators
>> +
>> +maintainers:
>> + - Vikash Garodia <vikash.garodia@oss.qualcomm.com>
>> + - Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
>> +
>> +description:
>> + The iris video processing unit is a video encode and decode accelerator
>> + present on Qualcomm platforms.
>> +
>> +properties:
>> + compatible:
>> + const: qcom,kaanapali-iris
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + power-domains:
>> + minItems: 5
>> + maxItems: 7
>
> You are sending bindings for a single device on a single platform. How
> comes that it has min != max?
I was planning to reuse this binding for the variant SOCs of kaanapali/vpu4. If
we do not have min interface, then for those variants, we have to either have
separate bindings or add if/else conditions(?). Introducing min now can make it
easily usable for upcoming vpu4 variants.
>
>> +
>> + power-domain-names:
>> + items:
>> + - const: venus
>> + - const: vcodec0
>> + - const: vpp0
>> + - const: vpp1
>> + - const: apv
>> + - const: mxc
>> + - const: mmcx
>> +
>> + clocks:
>> + minItems: 8
>> + maxItems: 10
>
> And here.
Same case here.
>
>> +
>> + clock-names:
>> + items:
>> + - const: iface
>> + - const: core
>> + - const: vcodec0_core
>> + - const: iface1
>> + - const: core_freerun
>> + - const: vcodec0_core_freerun
>> + - const: vcodec_bse
>> + - const: vcodec_vpp0
>> + - const: vcodec_vpp1
>> + - const: vcodec_apv
>> +
>
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-09-25 19:31 ` Vikash Garodia
@ 2025-09-25 19:38 ` Dmitry Baryshkov
2025-09-25 19:45 ` Vikash Garodia
2025-09-26 11:47 ` Konrad Dybcio
0 siblings, 2 replies; 54+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 19:38 UTC (permalink / raw)
To: Vikash Garodia
Cc: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, linux-arm-msm, linux-media,
devicetree, linux-kernel, Vishnu Reddy
On Fri, Sep 26, 2025 at 01:01:29AM +0530, Vikash Garodia wrote:
>
> On 9/26/2025 12:55 AM, Dmitry Baryshkov wrote:
> > On Thu, Sep 25, 2025 at 04:44:39AM +0530, Vikash Garodia wrote:
> >> Kaanapali SOC brings in the new generation of video IP i.e iris4. When
> >> compared to previous generation, iris3x, it has,
> >> - separate power domains for stream and pixel processing hardware blocks
> >> (bse and vpp).
> >> - additional power domain for apv codec.
> >> - power domains for individual pipes (VPPx).
> >> - different clocks and reset lines.
> >>
> >> There are variants of this hardware, where only a single VPP pipe would
> >> be functional (VPP0), and APV may not be present. In such case, the
> >> hardware can be enabled without those 2 related power doamins, and
> >> corresponding clocks. This explains the min entries for power domains
> >> and clocks.
> >> Iommus include all the different stream-ids which can be possibly
> >> generated by vpu4 video hardware in both secure and non secure
> >> execution mode.
> >>
> >> This patch depends on following patches
> >> https://lore.kernel.org/all/20250924-knp-interconnect-v1-1-4c822a72141c@oss.qualcomm.com/
> >> https://lore.kernel.org/all/20250924-knp-clk-v1-3-29b02b818782@oss.qualcomm.com/
> >>
> >> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> >> ---
> >> .../bindings/media/qcom,kaanapali-iris.yaml | 236 +++++++++++++++++++++
> >> 1 file changed, 236 insertions(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
> >> new file mode 100644
> >> index 0000000000000000000000000000000000000000..f3528d514fe29771227bee5f156962fedb1ea9cd
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
> >> @@ -0,0 +1,236 @@
> >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >> +%YAML 1.2
> >> +---
> >> +$id: http://devicetree.org/schemas/media/qcom,kaanapali-iris.yaml#
> >> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >> +
> >> +title: Qualcomm kaanapali iris video encode and decode accelerators
> >> +
> >> +maintainers:
> >> + - Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> >> + - Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
> >> +
> >> +description:
> >> + The iris video processing unit is a video encode and decode accelerator
> >> + present on Qualcomm platforms.
> >> +
> >> +properties:
> >> + compatible:
> >> + const: qcom,kaanapali-iris
> >> +
> >> + reg:
> >> + maxItems: 1
> >> +
> >> + interrupts:
> >> + maxItems: 1
> >> +
> >> + power-domains:
> >> + minItems: 5
> >> + maxItems: 7
> >
> > You are sending bindings for a single device on a single platform. How
> > comes that it has min != max?
>
> I was planning to reuse this binding for the variant SOCs of kaanapali/vpu4. If
> we do not have min interface, then for those variants, we have to either have
> separate bindings or add if/else conditions(?). Introducing min now can make it
> easily usable for upcoming vpu4 variants.
No, it makes it harder to follow the changes. This platform has
this-and-that requirements. Then you add another platform and it's clear
that the changes are for that platform. Now you have mixed two different
patches into a single one.
>
> >
> >> +
> >> + power-domain-names:
> >> + items:
> >> + - const: venus
> >> + - const: vcodec0
> >> + - const: vpp0
> >> + - const: vpp1
> >> + - const: apv
> >> + - const: mxc
> >> + - const: mmcx
> >> +
> >> + clocks:
> >> + minItems: 8
> >> + maxItems: 10
> >
> > And here.
>
> Same case here.
> >
> >> +
> >> + clock-names:
> >> + items:
> >> + - const: iface
> >> + - const: core
> >> + - const: vcodec0_core
> >> + - const: iface1
> >> + - const: core_freerun
> >> + - const: vcodec0_core_freerun
> >> + - const: vcodec_bse
> >> + - const: vcodec_vpp0
> >> + - const: vcodec_vpp1
> >> + - const: vcodec_apv
> >> +
> >
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-09-25 19:38 ` Dmitry Baryshkov
@ 2025-09-25 19:45 ` Vikash Garodia
2025-09-25 20:33 ` Dmitry Baryshkov
2025-09-26 11:47 ` Konrad Dybcio
1 sibling, 1 reply; 54+ messages in thread
From: Vikash Garodia @ 2025-09-25 19:45 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, linux-arm-msm, linux-media,
devicetree, linux-kernel, Vishnu Reddy
On 9/26/2025 1:08 AM, Dmitry Baryshkov wrote:
> On Fri, Sep 26, 2025 at 01:01:29AM +0530, Vikash Garodia wrote:
>>
>> On 9/26/2025 12:55 AM, Dmitry Baryshkov wrote:
>>> On Thu, Sep 25, 2025 at 04:44:39AM +0530, Vikash Garodia wrote:
>>>> Kaanapali SOC brings in the new generation of video IP i.e iris4. When
>>>> compared to previous generation, iris3x, it has,
>>>> - separate power domains for stream and pixel processing hardware blocks
>>>> (bse and vpp).
>>>> - additional power domain for apv codec.
>>>> - power domains for individual pipes (VPPx).
>>>> - different clocks and reset lines.
>>>>
>>>> There are variants of this hardware, where only a single VPP pipe would
>>>> be functional (VPP0), and APV may not be present. In such case, the
>>>> hardware can be enabled without those 2 related power doamins, and
>>>> corresponding clocks. This explains the min entries for power domains
>>>> and clocks.
>>>> Iommus include all the different stream-ids which can be possibly
>>>> generated by vpu4 video hardware in both secure and non secure
>>>> execution mode.
>>>>
>>>> This patch depends on following patches
>>>> https://lore.kernel.org/all/20250924-knp-interconnect-v1-1-4c822a72141c@oss.qualcomm.com/
>>>> https://lore.kernel.org/all/20250924-knp-clk-v1-3-29b02b818782@oss.qualcomm.com/
>>>>
>>>> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
>>>> ---
>>>> .../bindings/media/qcom,kaanapali-iris.yaml | 236 +++++++++++++++++++++
>>>> 1 file changed, 236 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
>>>> new file mode 100644
>>>> index 0000000000000000000000000000000000000000..f3528d514fe29771227bee5f156962fedb1ea9cd
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
>>>> @@ -0,0 +1,236 @@
>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>> +%YAML 1.2
>>>> +---
>>>> +$id: http://devicetree.org/schemas/media/qcom,kaanapali-iris.yaml#
>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: Qualcomm kaanapali iris video encode and decode accelerators
>>>> +
>>>> +maintainers:
>>>> + - Vikash Garodia <vikash.garodia@oss.qualcomm.com>
>>>> + - Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
>>>> +
>>>> +description:
>>>> + The iris video processing unit is a video encode and decode accelerator
>>>> + present on Qualcomm platforms.
>>>> +
>>>> +properties:
>>>> + compatible:
>>>> + const: qcom,kaanapali-iris
>>>> +
>>>> + reg:
>>>> + maxItems: 1
>>>> +
>>>> + interrupts:
>>>> + maxItems: 1
>>>> +
>>>> + power-domains:
>>>> + minItems: 5
>>>> + maxItems: 7
>>>
>>> You are sending bindings for a single device on a single platform. How
>>> comes that it has min != max?
>>
>> I was planning to reuse this binding for the variant SOCs of kaanapali/vpu4. If
>> we do not have min interface, then for those variants, we have to either have
>> separate bindings or add if/else conditions(?). Introducing min now can make it
>> easily usable for upcoming vpu4 variants.
>
> No, it makes it harder to follow the changes. This platform has
> this-and-that requirements. Then you add another platform and it's clear
> that the changes are for that platform. Now you have mixed two different
> patches into a single one.
you are suggesting to add new schema when the new variant comes in ? there is
also a possibility that this hardware(kaanapali) can be used without those
optional power domains as well. Let say, someone does not want apv codec, in
such case, that pd becomes optional.
Regards,
Vikash
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-09-25 19:45 ` Vikash Garodia
@ 2025-09-25 20:33 ` Dmitry Baryshkov
0 siblings, 0 replies; 54+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 20:33 UTC (permalink / raw)
To: Vikash Garodia
Cc: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, linux-arm-msm, linux-media,
devicetree, linux-kernel, Vishnu Reddy
On Fri, Sep 26, 2025 at 01:15:15AM +0530, Vikash Garodia wrote:
>
> On 9/26/2025 1:08 AM, Dmitry Baryshkov wrote:
> > On Fri, Sep 26, 2025 at 01:01:29AM +0530, Vikash Garodia wrote:
> >>
> >> On 9/26/2025 12:55 AM, Dmitry Baryshkov wrote:
> >>> On Thu, Sep 25, 2025 at 04:44:39AM +0530, Vikash Garodia wrote:
> >>>> Kaanapali SOC brings in the new generation of video IP i.e iris4. When
> >>>> compared to previous generation, iris3x, it has,
> >>>> - separate power domains for stream and pixel processing hardware blocks
> >>>> (bse and vpp).
> >>>> - additional power domain for apv codec.
> >>>> - power domains for individual pipes (VPPx).
> >>>> - different clocks and reset lines.
> >>>>
> >>>> There are variants of this hardware, where only a single VPP pipe would
> >>>> be functional (VPP0), and APV may not be present. In such case, the
> >>>> hardware can be enabled without those 2 related power doamins, and
> >>>> corresponding clocks. This explains the min entries for power domains
> >>>> and clocks.
> >>>> Iommus include all the different stream-ids which can be possibly
> >>>> generated by vpu4 video hardware in both secure and non secure
> >>>> execution mode.
> >>>>
> >>>> This patch depends on following patches
> >>>> https://lore.kernel.org/all/20250924-knp-interconnect-v1-1-4c822a72141c@oss.qualcomm.com/
> >>>> https://lore.kernel.org/all/20250924-knp-clk-v1-3-29b02b818782@oss.qualcomm.com/
> >>>>
> >>>> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> >>>> ---
> >>>> .../bindings/media/qcom,kaanapali-iris.yaml | 236 +++++++++++++++++++++
> >>>> 1 file changed, 236 insertions(+)
> >>>>
> >>>> diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
> >>>> new file mode 100644
> >>>> index 0000000000000000000000000000000000000000..f3528d514fe29771227bee5f156962fedb1ea9cd
> >>>> --- /dev/null
> >>>> +++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
> >>>> @@ -0,0 +1,236 @@
> >>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >>>> +%YAML 1.2
> >>>> +---
> >>>> +$id: http://devicetree.org/schemas/media/qcom,kaanapali-iris.yaml#
> >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>>> +
> >>>> +title: Qualcomm kaanapali iris video encode and decode accelerators
> >>>> +
> >>>> +maintainers:
> >>>> + - Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> >>>> + - Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
> >>>> +
> >>>> +description:
> >>>> + The iris video processing unit is a video encode and decode accelerator
> >>>> + present on Qualcomm platforms.
> >>>> +
> >>>> +properties:
> >>>> + compatible:
> >>>> + const: qcom,kaanapali-iris
> >>>> +
> >>>> + reg:
> >>>> + maxItems: 1
> >>>> +
> >>>> + interrupts:
> >>>> + maxItems: 1
> >>>> +
> >>>> + power-domains:
> >>>> + minItems: 5
> >>>> + maxItems: 7
> >>>
> >>> You are sending bindings for a single device on a single platform. How
> >>> comes that it has min != max?
> >>
> >> I was planning to reuse this binding for the variant SOCs of kaanapali/vpu4. If
> >> we do not have min interface, then for those variants, we have to either have
> >> separate bindings or add if/else conditions(?). Introducing min now can make it
> >> easily usable for upcoming vpu4 variants.
> >
> > No, it makes it harder to follow the changes. This platform has
> > this-and-that requirements. Then you add another platform and it's clear
> > that the changes are for that platform. Now you have mixed two different
> > patches into a single one.
>
> you are suggesting to add new schema when the new variant comes in ?
No, I'm suggesting extending the schema when the new variant comes in
instead.
> there is
> also a possibility that this hardware(kaanapali) can be used without those
> optional power domains as well. Let say, someone does not want apv codec, in
> such case, that pd becomes optional.
That's totally a software construct - not enabling unused domains. Here
you are describing, you know, the hardware. And in the hardware the IP
core has a fixed number of connected clocks and power domains.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-09-25 19:38 ` Dmitry Baryshkov
2025-09-25 19:45 ` Vikash Garodia
@ 2025-09-26 11:47 ` Konrad Dybcio
2025-09-26 13:55 ` Vikash Garodia
1 sibling, 1 reply; 54+ messages in thread
From: Konrad Dybcio @ 2025-09-26 11:47 UTC (permalink / raw)
To: Dmitry Baryshkov, Vikash Garodia
Cc: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, linux-arm-msm, linux-media,
devicetree, linux-kernel, Vishnu Reddy
On 9/25/25 9:38 PM, Dmitry Baryshkov wrote:
> On Fri, Sep 26, 2025 at 01:01:29AM +0530, Vikash Garodia wrote:
>>
>> On 9/26/2025 12:55 AM, Dmitry Baryshkov wrote:
>>> On Thu, Sep 25, 2025 at 04:44:39AM +0530, Vikash Garodia wrote:
[...]
>>>> + power-domains:
>>>> + minItems: 5
>>>> + maxItems: 7
>>>
>>> You are sending bindings for a single device on a single platform. How
>>> comes that it has min != max?
>>
>> I was planning to reuse this binding for the variant SOCs of kaanapali/vpu4. If
>> we do not have min interface, then for those variants, we have to either have
>> separate bindings or add if/else conditions(?). Introducing min now can make it
>> easily usable for upcoming vpu4 variants.
>
> No, it makes it harder to follow the changes. This platform has
> this-and-that requirements. Then you add another platform and it's clear
> that the changes are for that platform. Now you have mixed two different
> patches into a single one.
Vikash, preparing for future submissions is a very good thing,
however "a binding" can be thought of as a tuple of
(compatible, allowed_properties, required_properties)
which needs(asterisk) to remain immutable
You can make changes to this file later, when introducing said
platforms and it will be fine, so long as you preserve the same allowed
and required properties that you're trying to associate with Kanaapali
here
(i.e. YAML refactors are OK but the result must come out identical)
Konrad
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-09-26 11:47 ` Konrad Dybcio
@ 2025-09-26 13:55 ` Vikash Garodia
2025-09-26 22:25 ` Dmitry Baryshkov
0 siblings, 1 reply; 54+ messages in thread
From: Vikash Garodia @ 2025-09-26 13:55 UTC (permalink / raw)
To: Konrad Dybcio, Dmitry Baryshkov
Cc: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, linux-arm-msm, linux-media,
devicetree, linux-kernel, Vishnu Reddy
On 9/26/2025 5:17 PM, Konrad Dybcio wrote:
> On 9/25/25 9:38 PM, Dmitry Baryshkov wrote:
>> On Fri, Sep 26, 2025 at 01:01:29AM +0530, Vikash Garodia wrote:
>>>
>>> On 9/26/2025 12:55 AM, Dmitry Baryshkov wrote:
>>>> On Thu, Sep 25, 2025 at 04:44:39AM +0530, Vikash Garodia wrote:
>
>
> [...]
>
>>>>> + power-domains:
>>>>> + minItems: 5
>>>>> + maxItems: 7
>>>>
>>>> You are sending bindings for a single device on a single platform. How
>>>> comes that it has min != max?
>>>
>>> I was planning to reuse this binding for the variant SOCs of kaanapali/vpu4. If
>>> we do not have min interface, then for those variants, we have to either have
>>> separate bindings or add if/else conditions(?). Introducing min now can make it
>>> easily usable for upcoming vpu4 variants.
>>
>> No, it makes it harder to follow the changes. This platform has
>> this-and-that requirements. Then you add another platform and it's clear
>> that the changes are for that platform. Now you have mixed two different
>> patches into a single one.
>
> Vikash, preparing for future submissions is a very good thing,
> however "a binding" can be thought of as a tuple of
>
> (compatible, allowed_properties, required_properties)
>
> which needs(asterisk) to remain immutable
>
> You can make changes to this file later, when introducing said
> platforms and it will be fine, so long as you preserve the same allowed
> and required properties that you're trying to associate with Kanaapali
> here
Let say, we have a kaanapali hardware (calling it as kaanapali_next) with 6
power domains, instead of 7, given that one of the pipe is malfunctional or
fused out in that hardware distrubution, should the binding be extended for such
variant like below ?
power-domains:
maxItems: 7
- if:
properties:
compatible:
enum:
- qcom,kaanapali_next-iris
then:
properties:
power-domains:
maxItems: 6
else:
properties:
power-domains:
maxItems: 7
Also, what is the downside in existing approach where we say that the hardware
can be functional with 5 pds, and 2 are optional based on hardware having them
or not ? So all combinations of [5, 6, 7] pds are valid. IIUC, the optional
entries are made for such cases where some hardware parts are variable, please
correct my understanding.
Regards,
Vikash
> (i.e. YAML refactors are OK but the result must come out identical)
>
> Konrad
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-09-26 13:55 ` Vikash Garodia
@ 2025-09-26 22:25 ` Dmitry Baryshkov
2025-10-02 9:18 ` Vikash Garodia
0 siblings, 1 reply; 54+ messages in thread
From: Dmitry Baryshkov @ 2025-09-26 22:25 UTC (permalink / raw)
To: Vikash Garodia
Cc: Konrad Dybcio, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, linux-arm-msm,
linux-media, devicetree, linux-kernel, Vishnu Reddy
On Fri, Sep 26, 2025 at 07:25:30PM +0530, Vikash Garodia wrote:
>
> On 9/26/2025 5:17 PM, Konrad Dybcio wrote:
> > On 9/25/25 9:38 PM, Dmitry Baryshkov wrote:
> >> On Fri, Sep 26, 2025 at 01:01:29AM +0530, Vikash Garodia wrote:
> >>>
> >>> On 9/26/2025 12:55 AM, Dmitry Baryshkov wrote:
> >>>> On Thu, Sep 25, 2025 at 04:44:39AM +0530, Vikash Garodia wrote:
> >
> >
> > [...]
> >
> >>>>> + power-domains:
> >>>>> + minItems: 5
> >>>>> + maxItems: 7
> >>>>
> >>>> You are sending bindings for a single device on a single platform. How
> >>>> comes that it has min != max?
> >>>
> >>> I was planning to reuse this binding for the variant SOCs of kaanapali/vpu4. If
> >>> we do not have min interface, then for those variants, we have to either have
> >>> separate bindings or add if/else conditions(?). Introducing min now can make it
> >>> easily usable for upcoming vpu4 variants.
> >>
> >> No, it makes it harder to follow the changes. This platform has
> >> this-and-that requirements. Then you add another platform and it's clear
> >> that the changes are for that platform. Now you have mixed two different
> >> patches into a single one.
> >
> > Vikash, preparing for future submissions is a very good thing,
> > however "a binding" can be thought of as a tuple of
> >
> > (compatible, allowed_properties, required_properties)
> >
> > which needs(asterisk) to remain immutable
> >
> > You can make changes to this file later, when introducing said
> > platforms and it will be fine, so long as you preserve the same allowed
> > and required properties that you're trying to associate with Kanaapali
> > here
>
> Let say, we have a kaanapali hardware (calling it as kaanapali_next) with 6
> power domains, instead of 7, given that one of the pipe is malfunctional or
> fused out in that hardware distrubution, should the binding be extended for such
> variant like below ?
This comes together with the description of kaanapali_next and a proper
commit message, describing the usage of fuses in the nvram for this
hardware, etc. My point is that you are adding support for a fixed class
of hardware: normal Kaanapali device, no extras, no disabled blocks,
etc. This class of hardware has a fixed connections between IP blocks,
fixed number of cores, power domains, etc.
Only when we actually add kaanapali_next, kaanapali_lite, kaanapali+1 or
kaanapali-minor it would be logical to extend the base declarations, add
add if-conditions for both kaanapali and the new device (notice
if-conditions for kaanapali too).
I can say it other way around: the bindings that you've submitted are
not complete as you have not bound kaanapali desription according to its
actual hardware.
>
> power-domains:
> maxItems: 7
>
> - if:
> properties:
> compatible:
> enum:
> - qcom,kaanapali_next-iris
> then:
> properties:
> power-domains:
> maxItems: 6
>
> else:
> properties:
> power-domains:
> maxItems: 7
>
> Also, what is the downside in existing approach where we say that the hardware
> can be functional with 5 pds, and 2 are optional based on hardware having them
> or not ? So all combinations of [5, 6, 7] pds are valid. IIUC, the optional
> entries are made for such cases where some hardware parts are variable, please
> correct my understanding.
Kaanapali hardware is not variable, is it?
>
> Regards,
> Vikash
>
> > (i.e. YAML refactors are OK but the result must come out identical)
> >
> > Konrad
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-09-26 22:25 ` Dmitry Baryshkov
@ 2025-10-02 9:18 ` Vikash Garodia
2025-10-07 13:58 ` Krzysztof Kozlowski
0 siblings, 1 reply; 54+ messages in thread
From: Vikash Garodia @ 2025-10-02 9:18 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Konrad Dybcio, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, linux-arm-msm,
linux-media, devicetree, linux-kernel, Vishnu Reddy
On 9/27/2025 3:55 AM, Dmitry Baryshkov wrote:
> On Fri, Sep 26, 2025 at 07:25:30PM +0530, Vikash Garodia wrote:
>>
>> On 9/26/2025 5:17 PM, Konrad Dybcio wrote:
>>> On 9/25/25 9:38 PM, Dmitry Baryshkov wrote:
>>>> On Fri, Sep 26, 2025 at 01:01:29AM +0530, Vikash Garodia wrote:
>>>>>
>>>>> On 9/26/2025 12:55 AM, Dmitry Baryshkov wrote:
>>>>>> On Thu, Sep 25, 2025 at 04:44:39AM +0530, Vikash Garodia wrote:
>>>
>>>
>>> [...]
>>>
>>>>>>> + power-domains:
>>>>>>> + minItems: 5
>>>>>>> + maxItems: 7
>>>>>>
>>>>>> You are sending bindings for a single device on a single platform. How
>>>>>> comes that it has min != max?
>>>>>
>>>>> I was planning to reuse this binding for the variant SOCs of kaanapali/vpu4. If
>>>>> we do not have min interface, then for those variants, we have to either have
>>>>> separate bindings or add if/else conditions(?). Introducing min now can make it
>>>>> easily usable for upcoming vpu4 variants.
>>>>
>>>> No, it makes it harder to follow the changes. This platform has
>>>> this-and-that requirements. Then you add another platform and it's clear
>>>> that the changes are for that platform. Now you have mixed two different
>>>> patches into a single one.
>>>
>>> Vikash, preparing for future submissions is a very good thing,
>>> however "a binding" can be thought of as a tuple of
>>>
>>> (compatible, allowed_properties, required_properties)
>>>
>>> which needs(asterisk) to remain immutable
>>>
>>> You can make changes to this file later, when introducing said
>>> platforms and it will be fine, so long as you preserve the same allowed
>>> and required properties that you're trying to associate with Kanaapali
>>> here
>>
>> Let say, we have a kaanapali hardware (calling it as kaanapali_next) with 6
>> power domains, instead of 7, given that one of the pipe is malfunctional or
>> fused out in that hardware distrubution, should the binding be extended for such
>> variant like below ?
>
> This comes together with the description of kaanapali_next and a proper
> commit message, describing the usage of fuses in the nvram for this
> hardware, etc. My point is that you are adding support for a fixed class
> of hardware: normal Kaanapali device, no extras, no disabled blocks,
> etc. This class of hardware has a fixed connections between IP blocks,
> fixed number of cores, power domains, etc.
>
> Only when we actually add kaanapali_next, kaanapali_lite, kaanapali+1 or
> kaanapali-minor it would be logical to extend the base declarations, add
> add if-conditions for both kaanapali and the new device (notice
> if-conditions for kaanapali too).
>
> I can say it other way around: the bindings that you've submitted are
> not complete as you have not bound kaanapali desription according to its
> actual hardware.
>
>>
>> power-domains:
>> maxItems: 7
>>
>> - if:
>> properties:
>> compatible:
>> enum:
>> - qcom,kaanapali_next-iris
>> then:
>> properties:
>> power-domains:
>> maxItems: 6
>>
>> else:
>> properties:
>> power-domains:
>> maxItems: 7
>>
>> Also, what is the downside in existing approach where we say that the hardware
>> can be functional with 5 pds, and 2 are optional based on hardware having them
>> or not ? So all combinations of [5, 6, 7] pds are valid. IIUC, the optional
>> entries are made for such cases where some hardware parts are variable, please
>> correct my understanding.
>
> Kaanapali hardware is not variable, is it?
By variable i meant the hardware is functional with or without those bindings,
hence was keeping them as an interface but optional. If that fits into optional
category, i can keep it existing way, otherwise will update to fix binding.
Regards,
Vikash
>
>>
>> Regards,
>> Vikash
>>
>>> (i.e. YAML refactors are OK but the result must come out identical)
>>>
>>> Konrad
>
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-10-02 9:18 ` Vikash Garodia
@ 2025-10-07 13:58 ` Krzysztof Kozlowski
2025-10-08 9:53 ` Vikash Garodia
0 siblings, 1 reply; 54+ messages in thread
From: Krzysztof Kozlowski @ 2025-10-07 13:58 UTC (permalink / raw)
To: Vikash Garodia, Dmitry Baryshkov
Cc: Konrad Dybcio, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, linux-arm-msm,
linux-media, devicetree, linux-kernel, Vishnu Reddy
On 02/10/2025 18:18, Vikash Garodia wrote:
>>> then:
>>> properties:
>>> power-domains:
>>> maxItems: 6
>>>
>>> else:
>>> properties:
>>> power-domains:
>>> maxItems: 7
>>>
>>> Also, what is the downside in existing approach where we say that the hardware
>>> can be functional with 5 pds, and 2 are optional based on hardware having them
>>> or not ? So all combinations of [5, 6, 7] pds are valid. IIUC, the optional
>>> entries are made for such cases where some hardware parts are variable, please
>>> correct my understanding.
>>
>> Kaanapali hardware is not variable, is it?
>
> By variable i meant the hardware is functional with or without those bindings,
> hence was keeping them as an interface but optional. If that fits into optional
> category, i can keep it existing way, otherwise will update to fix binding.
You describe here how SoC is wired/engineered/created. Can you create a
board with the Kaanapali SoC where the power domain is not there?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-10-07 13:58 ` Krzysztof Kozlowski
@ 2025-10-08 9:53 ` Vikash Garodia
0 siblings, 0 replies; 54+ messages in thread
From: Vikash Garodia @ 2025-10-08 9:53 UTC (permalink / raw)
To: Krzysztof Kozlowski, Dmitry Baryshkov
Cc: Konrad Dybcio, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, linux-arm-msm,
linux-media, devicetree, linux-kernel, Vishnu Reddy
On 10/7/2025 7:28 PM, Krzysztof Kozlowski wrote:
>>>> then:
>>>> properties:
>>>> power-domains:
>>>> maxItems: 6
>>>>
>>>> else:
>>>> properties:
>>>> power-domains:
>>>> maxItems: 7
>>>>
>>>> Also, what is the downside in existing approach where we say that the hardware
>>>> can be functional with 5 pds, and 2 are optional based on hardware having them
>>>> or not ? So all combinations of [5, 6, 7] pds are valid. IIUC, the optional
>>>> entries are made for such cases where some hardware parts are variable, please
>>>> correct my understanding.
>>> Kaanapali hardware is not variable, is it?
>> By variable i meant the hardware is functional with or without those bindings,
>> hence was keeping them as an interface but optional. If that fits into optional
>> category, i can keep it existing way, otherwise will update to fix binding.
> You describe here how SoC is wired/engineered/created. Can you create a
> board with the Kaanapali SoC where the power domain is not there?
Not in kaanapali, so it explains if and only if the same SOC can be created
without those specific wiring, then it falls into optional category.
In the next revision of this series, will keep them under regular binding (not
optional).
Regards,
Vikash
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH 2/8] media: iris: Add support for multiple clock sources
2025-09-24 23:14 [PATCH 0/8] media: iris: add support for video codecs on Qcom kaanapali platform Vikash Garodia
2025-09-24 23:14 ` [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding Vikash Garodia
@ 2025-09-24 23:14 ` Vikash Garodia
2025-09-25 23:59 ` Bryan O'Donoghue
2025-09-24 23:14 ` [PATCH 3/8] media: iris: Add support for multiple TZ CP configs Vikash Garodia
` (5 subsequent siblings)
7 siblings, 1 reply; 54+ messages in thread
From: Vikash Garodia @ 2025-09-24 23:14 UTC (permalink / raw)
To: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy, Vikash Garodia
vpu4 comes with more than one clock sources running the hardware, so far
it was clocked by single clock source in vpu3x and earlier. Configure
OPP table for video device with these different video clocks, such that
the OPP can be set to multiple clocks during dev_pm_opp_set_opp(). This
patch extends the support for multiple clocks in driver, which would be
used in subsequent patch for kaanapali, when the platform data is
prepared.
Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
---
.../media/platform/qcom/iris/iris_platform_common.h | 1 +
.../media/platform/qcom/iris/iris_platform_gen2.c | 9 +++++++++
.../media/platform/qcom/iris/iris_platform_sm8250.c | 6 ++++++
drivers/media/platform/qcom/iris/iris_power.c | 2 +-
drivers/media/platform/qcom/iris/iris_probe.c | 20 ++++++++------------
drivers/media/platform/qcom/iris/iris_resources.c | 16 ++++++++++++++--
drivers/media/platform/qcom/iris/iris_resources.h | 1 +
drivers/media/platform/qcom/iris/iris_vpu_common.c | 4 ++--
8 files changed, 42 insertions(+), 17 deletions(-)
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index 58d05e0a112eed25faea027a34c719c89d6c3897..df03de08c44839c1b6c137874eb7273c638d5f2c 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -206,6 +206,7 @@ struct iris_platform_data {
const char * const *opp_pd_tbl;
unsigned int opp_pd_tbl_size;
const struct platform_clk_data *clk_tbl;
+ const char * const *opp_clk_tbl;
unsigned int clk_tbl_size;
const char * const *clk_rst_tbl;
unsigned int clk_rst_tbl_size;
diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
index 36d69cc73986b74534a2912524c8553970fd862e..fea800811a389a58388175c733ad31c4d9c636b0 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
@@ -633,6 +633,11 @@ static const struct platform_clk_data sm8550_clk_table[] = {
{IRIS_HW_CLK, "vcodec0_core" },
};
+static const char * const sm8550_opp_clk_table[] = {
+ "vcodec0_core",
+ NULL,
+};
+
static struct ubwc_config_data ubwc_config_sm8550 = {
.max_channels = 8,
.mal_length = 32,
@@ -756,6 +761,7 @@ struct iris_platform_data sm8550_data = {
.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
.clk_tbl = sm8550_clk_table,
.clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
+ .opp_clk_tbl = sm8550_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu/vpu30_p4.mbn",
@@ -848,6 +854,7 @@ struct iris_platform_data sm8650_data = {
.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
.clk_tbl = sm8550_clk_table,
.clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
+ .opp_clk_tbl = sm8550_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu/vpu33_p4.mbn",
@@ -930,6 +937,7 @@ struct iris_platform_data sm8750_data = {
.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
.clk_tbl = sm8750_clk_table,
.clk_tbl_size = ARRAY_SIZE(sm8750_clk_table),
+ .opp_clk_tbl = sm8550_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu/vpu35_p4.mbn",
@@ -1017,6 +1025,7 @@ struct iris_platform_data qcs8300_data = {
.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
.clk_tbl = sm8550_clk_table,
.clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
+ .opp_clk_tbl = sm8550_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu/vpu30_p4_s6.mbn",
diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
index 16486284f8acccf6a95a27f6003e885226e28f4d..1b1b6aa751106ee0b0bc71bb0df2e78340190e66 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
@@ -273,6 +273,11 @@ static const struct platform_clk_data sm8250_clk_table[] = {
{IRIS_HW_CLK, "vcodec0_core" },
};
+static const char * const sm8250_opp_clk_table[] = {
+ "vcodec0_core",
+ NULL,
+};
+
static struct tz_cp_config tz_cp_config_sm8250 = {
.cp_start = 0,
.cp_size = 0x25800000,
@@ -333,6 +338,7 @@ struct iris_platform_data sm8250_data = {
.opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table),
.clk_tbl = sm8250_clk_table,
.clk_tbl_size = ARRAY_SIZE(sm8250_clk_table),
+ .opp_clk_tbl = sm8250_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu-1.0/venus.mbn",
diff --git a/drivers/media/platform/qcom/iris/iris_power.c b/drivers/media/platform/qcom/iris/iris_power.c
index dbca42df0910fd3c0fb253dbfabf1afa2c3d32ad..91aa21d4070ebcebbe2ed127a03e5e49b9a2bd5c 100644
--- a/drivers/media/platform/qcom/iris/iris_power.c
+++ b/drivers/media/platform/qcom/iris/iris_power.c
@@ -91,7 +91,7 @@ static int iris_set_clocks(struct iris_inst *inst)
}
core->power.clk_freq = freq;
- ret = dev_pm_opp_set_rate(core->dev, freq);
+ ret = iris_opp_set_rate(core->dev, freq);
mutex_unlock(&core->lock);
return ret;
diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c
index 00e99be16e087c4098f930151fd76cd381d721ce..ad82a62f8b923d818ffe77c131d7eb6da8c34002 100644
--- a/drivers/media/platform/qcom/iris/iris_probe.c
+++ b/drivers/media/platform/qcom/iris/iris_probe.c
@@ -40,8 +40,6 @@ static int iris_init_icc(struct iris_core *core)
static int iris_init_power_domains(struct iris_core *core)
{
- const struct platform_clk_data *clk_tbl;
- u32 clk_cnt, i;
int ret;
struct dev_pm_domain_attach_data iris_pd_data = {
@@ -56,6 +54,11 @@ static int iris_init_power_domains(struct iris_core *core)
.pd_flags = PD_FLAG_DEV_LINK_ON | PD_FLAG_REQUIRED_OPP,
};
+ struct dev_pm_opp_config iris_opp_clk_data = {
+ .clk_names = core->iris_platform_data->opp_clk_tbl,
+ .config_clks = dev_pm_opp_config_clks_simple,
+ };
+
ret = devm_pm_domain_attach_list(core->dev, &iris_pd_data, &core->pmdomain_tbl);
if (ret < 0)
return ret;
@@ -64,16 +67,9 @@ static int iris_init_power_domains(struct iris_core *core)
if (ret < 0)
return ret;
- clk_tbl = core->iris_platform_data->clk_tbl;
- clk_cnt = core->iris_platform_data->clk_tbl_size;
-
- for (i = 0; i < clk_cnt; i++) {
- if (clk_tbl[i].clk_type == IRIS_HW_CLK) {
- ret = devm_pm_opp_set_clkname(core->dev, clk_tbl[i].clk_name);
- if (ret)
- return ret;
- }
- }
+ ret = devm_pm_opp_set_config(core->dev, &iris_opp_clk_data);
+ if (ret)
+ return ret;
return devm_pm_opp_of_add_table(core->dev);
}
diff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/media/platform/qcom/iris/iris_resources.c
index cf32f268b703c1c042a9bcf146e444fff4f4990d..939f6617f2631503fa8cb3e874b9de6b2fbe7b76 100644
--- a/drivers/media/platform/qcom/iris/iris_resources.c
+++ b/drivers/media/platform/qcom/iris/iris_resources.c
@@ -4,6 +4,7 @@
*/
#include <linux/clk.h>
+#include <linux/devfreq.h>
#include <linux/interconnect.h>
#include <linux/pm_domain.h>
#include <linux/pm_opp.h>
@@ -58,11 +59,22 @@ int iris_unset_icc_bw(struct iris_core *core)
return icc_bulk_set_bw(core->icc_count, core->icc_tbl);
}
+int iris_opp_set_rate(struct device *dev, unsigned long freq)
+{
+ struct dev_pm_opp *opp __free(put_opp);
+
+ opp = devfreq_recommended_opp(dev, &freq, 0);
+ if (IS_ERR(opp))
+ return PTR_ERR(opp);
+
+ return dev_pm_opp_set_opp(dev, opp);
+}
+
int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev)
{
int ret;
- ret = dev_pm_opp_set_rate(core->dev, ULONG_MAX);
+ ret = iris_opp_set_rate(core->dev, ULONG_MAX);
if (ret)
return ret;
@@ -77,7 +89,7 @@ int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev)
{
int ret;
- ret = dev_pm_opp_set_rate(core->dev, 0);
+ ret = iris_opp_set_rate(core->dev, 0);
if (ret)
return ret;
diff --git a/drivers/media/platform/qcom/iris/iris_resources.h b/drivers/media/platform/qcom/iris/iris_resources.h
index f723dfe5bd81a9c9db22d53bde4e18743d771210..6bfbd2dc6db095ec05e53c894e048285f82446c6 100644
--- a/drivers/media/platform/qcom/iris/iris_resources.h
+++ b/drivers/media/platform/qcom/iris/iris_resources.h
@@ -8,6 +8,7 @@
struct iris_core;
+int iris_opp_set_rate(struct device *dev, unsigned long freq);
int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev);
int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev);
int iris_unset_icc_bw(struct iris_core *core);
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
index bb98950e018fadf69ac4f41b3037f7fd6ac33c5b..bbd999a41236dca5cf5700e452a6fed69f4fc922 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
@@ -266,7 +266,7 @@ void iris_vpu_power_off_hw(struct iris_core *core)
void iris_vpu_power_off(struct iris_core *core)
{
- dev_pm_opp_set_rate(core->dev, 0);
+ iris_opp_set_rate(core->dev, 0);
core->iris_platform_data->vpu_ops->power_off_hw(core);
core->iris_platform_data->vpu_ops->power_off_controller(core);
iris_unset_icc_bw(core);
@@ -352,7 +352,7 @@ int iris_vpu_power_on(struct iris_core *core)
freq = core->power.clk_freq ? core->power.clk_freq :
(u32)ULONG_MAX;
- dev_pm_opp_set_rate(core->dev, freq);
+ iris_opp_set_rate(core->dev, freq);
core->iris_platform_data->set_preset_registers(core);
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH 2/8] media: iris: Add support for multiple clock sources
2025-09-24 23:14 ` [PATCH 2/8] media: iris: Add support for multiple clock sources Vikash Garodia
@ 2025-09-25 23:59 ` Bryan O'Donoghue
2025-10-02 9:25 ` Vikash Garodia
0 siblings, 1 reply; 54+ messages in thread
From: Bryan O'Donoghue @ 2025-09-25 23:59 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 25/09/2025 00:14, Vikash Garodia wrote:
> vpu4 comes with more than one clock sources running the hardware, so far
> it was clocked by single clock source in vpu3x and earlier. Configure
> OPP table for video device with these different video clocks, such that
> the OPP can be set to multiple clocks during dev_pm_opp_set_opp(). This
> patch extends the support for multiple clocks in driver, which would be
> used in subsequent patch for kaanapali, when the platform data is
> prepared.
You need to fix the commit log here a bit.
vpu4 depends on more than one clock source. Thus far hardware versions
up to vpu3x have been clocked by a single source using dev_pm_opp_set_opp().
This adds support for multiple clocks by
- Adding a lookup table
- Using devm_pm_opp_set_config to set the array of clocks
- See comment below about breaking into two patches below
>
> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> ---
> .../media/platform/qcom/iris/iris_platform_common.h | 1 +
> .../media/platform/qcom/iris/iris_platform_gen2.c | 9 +++++++++
> .../media/platform/qcom/iris/iris_platform_sm8250.c | 6 ++++++
> drivers/media/platform/qcom/iris/iris_power.c | 2 +-
> drivers/media/platform/qcom/iris/iris_probe.c | 20 ++++++++------------
> drivers/media/platform/qcom/iris/iris_resources.c | 16 ++++++++++++++--
> drivers/media/platform/qcom/iris/iris_resources.h | 1 +
> drivers/media/platform/qcom/iris/iris_vpu_common.c | 4 ++--
> 8 files changed, 42 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
> index 58d05e0a112eed25faea027a34c719c89d6c3897..df03de08c44839c1b6c137874eb7273c638d5f2c 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
> @@ -206,6 +206,7 @@ struct iris_platform_data {
> const char * const *opp_pd_tbl;
> unsigned int opp_pd_tbl_size;
> const struct platform_clk_data *clk_tbl;
> + const char * const *opp_clk_tbl;
> unsigned int clk_tbl_size;
> const char * const *clk_rst_tbl;
> unsigned int clk_rst_tbl_size;
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> index 36d69cc73986b74534a2912524c8553970fd862e..fea800811a389a58388175c733ad31c4d9c636b0 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> @@ -633,6 +633,11 @@ static const struct platform_clk_data sm8550_clk_table[] = {
> {IRIS_HW_CLK, "vcodec0_core" },
> };
>
> +static const char * const sm8550_opp_clk_table[] = {
> + "vcodec0_core",
> + NULL,
> +};
> +
> static struct ubwc_config_data ubwc_config_sm8550 = {
> .max_channels = 8,
> .mal_length = 32,
> @@ -756,6 +761,7 @@ struct iris_platform_data sm8550_data = {
> .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
> .clk_tbl = sm8550_clk_table,
> .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
> + .opp_clk_tbl = sm8550_opp_clk_table,
> /* Upper bound of DMA address range */
> .dma_mask = 0xe0000000 - 1,
> .fwname = "qcom/vpu/vpu30_p4.mbn",
> @@ -848,6 +854,7 @@ struct iris_platform_data sm8650_data = {
> .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
> .clk_tbl = sm8550_clk_table,
> .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
> + .opp_clk_tbl = sm8550_opp_clk_table,
> /* Upper bound of DMA address range */
> .dma_mask = 0xe0000000 - 1,
> .fwname = "qcom/vpu/vpu33_p4.mbn",
> @@ -930,6 +937,7 @@ struct iris_platform_data sm8750_data = {
> .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
> .clk_tbl = sm8750_clk_table,
> .clk_tbl_size = ARRAY_SIZE(sm8750_clk_table),
> + .opp_clk_tbl = sm8550_opp_clk_table,
> /* Upper bound of DMA address range */
> .dma_mask = 0xe0000000 - 1,
> .fwname = "qcom/vpu/vpu35_p4.mbn",
> @@ -1017,6 +1025,7 @@ struct iris_platform_data qcs8300_data = {
> .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
> .clk_tbl = sm8550_clk_table,
> .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
> + .opp_clk_tbl = sm8550_opp_clk_table,
> /* Upper bound of DMA address range */
> .dma_mask = 0xe0000000 - 1,
> .fwname = "qcom/vpu/vpu30_p4_s6.mbn",
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
> index 16486284f8acccf6a95a27f6003e885226e28f4d..1b1b6aa751106ee0b0bc71bb0df2e78340190e66 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
> @@ -273,6 +273,11 @@ static const struct platform_clk_data sm8250_clk_table[] = {
> {IRIS_HW_CLK, "vcodec0_core" },
> };
>
> +static const char * const sm8250_opp_clk_table[] = {
> + "vcodec0_core",
> + NULL,
> +};
> +
> static struct tz_cp_config tz_cp_config_sm8250 = {
> .cp_start = 0,
> .cp_size = 0x25800000,
> @@ -333,6 +338,7 @@ struct iris_platform_data sm8250_data = {
> .opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table),
> .clk_tbl = sm8250_clk_table,
> .clk_tbl_size = ARRAY_SIZE(sm8250_clk_table),
> + .opp_clk_tbl = sm8250_opp_clk_table,
> /* Upper bound of DMA address range */
> .dma_mask = 0xe0000000 - 1,
> .fwname = "qcom/vpu-1.0/venus.mbn",
> diff --git a/drivers/media/platform/qcom/iris/iris_power.c b/drivers/media/platform/qcom/iris/iris_power.c
> index dbca42df0910fd3c0fb253dbfabf1afa2c3d32ad..91aa21d4070ebcebbe2ed127a03e5e49b9a2bd5c 100644
> --- a/drivers/media/platform/qcom/iris/iris_power.c
> +++ b/drivers/media/platform/qcom/iris/iris_power.c
> @@ -91,7 +91,7 @@ static int iris_set_clocks(struct iris_inst *inst)
> }
>
> core->power.clk_freq = freq;
> - ret = dev_pm_opp_set_rate(core->dev, freq);
> + ret = iris_opp_set_rate(core->dev, freq);
> mutex_unlock(&core->lock);
>
> return ret;
> diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c
> index 00e99be16e087c4098f930151fd76cd381d721ce..ad82a62f8b923d818ffe77c131d7eb6da8c34002 100644
> --- a/drivers/media/platform/qcom/iris/iris_probe.c
> +++ b/drivers/media/platform/qcom/iris/iris_probe.c
> @@ -40,8 +40,6 @@ static int iris_init_icc(struct iris_core *core)
>
> static int iris_init_power_domains(struct iris_core *core)
> {
> - const struct platform_clk_data *clk_tbl;
> - u32 clk_cnt, i;
> int ret;
>
> struct dev_pm_domain_attach_data iris_pd_data = {
> @@ -56,6 +54,11 @@ static int iris_init_power_domains(struct iris_core *core)
> .pd_flags = PD_FLAG_DEV_LINK_ON | PD_FLAG_REQUIRED_OPP,
> };
>
> + struct dev_pm_opp_config iris_opp_clk_data = {
> + .clk_names = core->iris_platform_data->opp_clk_tbl,
> + .config_clks = dev_pm_opp_config_clks_simple,
> + };
> +
> ret = devm_pm_domain_attach_list(core->dev, &iris_pd_data, &core->pmdomain_tbl);
> if (ret < 0)
> return ret;
> @@ -64,16 +67,9 @@ static int iris_init_power_domains(struct iris_core *core)
> if (ret < 0)
> return ret;
>
> - clk_tbl = core->iris_platform_data->clk_tbl;
> - clk_cnt = core->iris_platform_data->clk_tbl_size;
> -
> - for (i = 0; i < clk_cnt; i++) {
> - if (clk_tbl[i].clk_type == IRIS_HW_CLK) {
> - ret = devm_pm_opp_set_clkname(core->dev, clk_tbl[i].clk_name);
> - if (ret)
> - return ret;
> - }
> - }
> + ret = devm_pm_opp_set_config(core->dev, &iris_opp_clk_data);
> + if (ret)
> + return ret;
>
> return devm_pm_opp_of_add_table(core->dev);
> }
> diff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/media/platform/qcom/iris/iris_resources.c
> index cf32f268b703c1c042a9bcf146e444fff4f4990d..939f6617f2631503fa8cb3e874b9de6b2fbe7b76 100644
> --- a/drivers/media/platform/qcom/iris/iris_resources.c
> +++ b/drivers/media/platform/qcom/iris/iris_resources.c
> @@ -4,6 +4,7 @@
> */
>
> #include <linux/clk.h>
> +#include <linux/devfreq.h>
> #include <linux/interconnect.h>
> #include <linux/pm_domain.h>
> #include <linux/pm_opp.h>
> @@ -58,11 +59,22 @@ int iris_unset_icc_bw(struct iris_core *core)
> return icc_bulk_set_bw(core->icc_count, core->icc_tbl);
> }
>
> +int iris_opp_set_rate(struct device *dev, unsigned long freq)
> +{
> + struct dev_pm_opp *opp __free(put_opp);
> +
> + opp = devfreq_recommended_opp(dev, &freq, 0);
> + if (IS_ERR(opp))
> + return PTR_ERR(opp);
> +
> + return dev_pm_opp_set_opp(dev, opp);
> +}
> +
I think this should be separated out from the clock setting and table
usage into a second patch because you can end up with different clock
frequencies here than before and being pedantic, I think that ought to
be made explicit in the commit log.
> int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev)
> {
> int ret;
>
> - ret = dev_pm_opp_set_rate(core->dev, ULONG_MAX);
> + ret = iris_opp_set_rate(core->dev, ULONG_MAX);
> if (ret)
> return ret;
>
> @@ -77,7 +89,7 @@ int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev)
> {
> int ret;
>
> - ret = dev_pm_opp_set_rate(core->dev, 0);
> + ret = iris_opp_set_rate(core->dev, 0);
> if (ret)
> return ret;
>
> diff --git a/drivers/media/platform/qcom/iris/iris_resources.h b/drivers/media/platform/qcom/iris/iris_resources.h
> index f723dfe5bd81a9c9db22d53bde4e18743d771210..6bfbd2dc6db095ec05e53c894e048285f82446c6 100644
> --- a/drivers/media/platform/qcom/iris/iris_resources.h
> +++ b/drivers/media/platform/qcom/iris/iris_resources.h
> @@ -8,6 +8,7 @@
>
> struct iris_core;
>
> +int iris_opp_set_rate(struct device *dev, unsigned long freq);
> int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev);
> int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev);
> int iris_unset_icc_bw(struct iris_core *core);
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> index bb98950e018fadf69ac4f41b3037f7fd6ac33c5b..bbd999a41236dca5cf5700e452a6fed69f4fc922 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> @@ -266,7 +266,7 @@ void iris_vpu_power_off_hw(struct iris_core *core)
>
> void iris_vpu_power_off(struct iris_core *core)
> {
> - dev_pm_opp_set_rate(core->dev, 0);
> + iris_opp_set_rate(core->dev, 0);
> core->iris_platform_data->vpu_ops->power_off_hw(core);
> core->iris_platform_data->vpu_ops->power_off_controller(core);
> iris_unset_icc_bw(core);
> @@ -352,7 +352,7 @@ int iris_vpu_power_on(struct iris_core *core)
> freq = core->power.clk_freq ? core->power.clk_freq :
> (u32)ULONG_MAX;
>
> - dev_pm_opp_set_rate(core->dev, freq);
> + iris_opp_set_rate(core->dev, freq);
>
> core->iris_platform_data->set_preset_registers(core);
>
>
> --
> 2.34.1
>
>
---
bod
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH 2/8] media: iris: Add support for multiple clock sources
2025-09-25 23:59 ` Bryan O'Donoghue
@ 2025-10-02 9:25 ` Vikash Garodia
0 siblings, 0 replies; 54+ messages in thread
From: Vikash Garodia @ 2025-10-02 9:25 UTC (permalink / raw)
To: Bryan O'Donoghue, Dikshita Agarwal, Abhinav Kumar,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 9/26/2025 5:29 AM, Bryan O'Donoghue wrote:
> On 25/09/2025 00:14, Vikash Garodia wrote:
>> vpu4 comes with more than one clock sources running the hardware, so far
>> it was clocked by single clock source in vpu3x and earlier. Configure
>> OPP table for video device with these different video clocks, such that
>> the OPP can be set to multiple clocks during dev_pm_opp_set_opp(). This
>> patch extends the support for multiple clocks in driver, which would be
>> used in subsequent patch for kaanapali, when the platform data is
>> prepared.
>
> You need to fix the commit log here a bit.
>
> vpu4 depends on more than one clock source. Thus far hardware versions up to
> vpu3x have been clocked by a single source using dev_pm_opp_set_opp().
>
> This adds support for multiple clocks by
>
> - Adding a lookup table
> - Using devm_pm_opp_set_config to set the array of clocks
> - See comment below about breaking into two patches below
>
>>
>> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
>> ---
>> .../media/platform/qcom/iris/iris_platform_common.h | 1 +
>> .../media/platform/qcom/iris/iris_platform_gen2.c | 9 +++++++++
>> .../media/platform/qcom/iris/iris_platform_sm8250.c | 6 ++++++
>> drivers/media/platform/qcom/iris/iris_power.c | 2 +-
>> drivers/media/platform/qcom/iris/iris_probe.c | 20 ++++++++------------
>> drivers/media/platform/qcom/iris/iris_resources.c | 16 ++++++++++++++--
>> drivers/media/platform/qcom/iris/iris_resources.h | 1 +
>> drivers/media/platform/qcom/iris/iris_vpu_common.c | 4 ++--
>> 8 files changed, 42 insertions(+), 17 deletions(-)
>>
>> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h
>> b/drivers/media/platform/qcom/iris/iris_platform_common.h
>> index
>> 58d05e0a112eed25faea027a34c719c89d6c3897..df03de08c44839c1b6c137874eb7273c638d5f2c 100644
>> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
>> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
>> @@ -206,6 +206,7 @@ struct iris_platform_data {
>> const char * const *opp_pd_tbl;
>> unsigned int opp_pd_tbl_size;
>> const struct platform_clk_data *clk_tbl;
>> + const char * const *opp_clk_tbl;
>> unsigned int clk_tbl_size;
>> const char * const *clk_rst_tbl;
>> unsigned int clk_rst_tbl_size;
>> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
>> b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
>> index
>> 36d69cc73986b74534a2912524c8553970fd862e..fea800811a389a58388175c733ad31c4d9c636b0 100644
>> --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
>> +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
>> @@ -633,6 +633,11 @@ static const struct platform_clk_data sm8550_clk_table[] = {
>> {IRIS_HW_CLK, "vcodec0_core" },
>> };
>>
>> +static const char * const sm8550_opp_clk_table[] = {
>> + "vcodec0_core",
>> + NULL,
>> +};
>> +
>> static struct ubwc_config_data ubwc_config_sm8550 = {
>> .max_channels = 8,
>> .mal_length = 32,
>> @@ -756,6 +761,7 @@ struct iris_platform_data sm8550_data = {
>> .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
>> .clk_tbl = sm8550_clk_table,
>> .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
>> + .opp_clk_tbl = sm8550_opp_clk_table,
>> /* Upper bound of DMA address range */
>> .dma_mask = 0xe0000000 - 1,
>> .fwname = "qcom/vpu/vpu30_p4.mbn",
>> @@ -848,6 +854,7 @@ struct iris_platform_data sm8650_data = {
>> .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
>> .clk_tbl = sm8550_clk_table,
>> .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
>> + .opp_clk_tbl = sm8550_opp_clk_table,
>> /* Upper bound of DMA address range */
>> .dma_mask = 0xe0000000 - 1,
>> .fwname = "qcom/vpu/vpu33_p4.mbn",
>> @@ -930,6 +937,7 @@ struct iris_platform_data sm8750_data = {
>> .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
>> .clk_tbl = sm8750_clk_table,
>> .clk_tbl_size = ARRAY_SIZE(sm8750_clk_table),
>> + .opp_clk_tbl = sm8550_opp_clk_table,
>> /* Upper bound of DMA address range */
>> .dma_mask = 0xe0000000 - 1,
>> .fwname = "qcom/vpu/vpu35_p4.mbn",
>> @@ -1017,6 +1025,7 @@ struct iris_platform_data qcs8300_data = {
>> .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
>> .clk_tbl = sm8550_clk_table,
>> .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
>> + .opp_clk_tbl = sm8550_opp_clk_table,
>> /* Upper bound of DMA address range */
>> .dma_mask = 0xe0000000 - 1,
>> .fwname = "qcom/vpu/vpu30_p4_s6.mbn",
>> diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
>> b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
>> index
>> 16486284f8acccf6a95a27f6003e885226e28f4d..1b1b6aa751106ee0b0bc71bb0df2e78340190e66 100644
>> --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
>> +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
>> @@ -273,6 +273,11 @@ static const struct platform_clk_data sm8250_clk_table[] = {
>> {IRIS_HW_CLK, "vcodec0_core" },
>> };
>>
>> +static const char * const sm8250_opp_clk_table[] = {
>> + "vcodec0_core",
>> + NULL,
>> +};
>> +
>> static struct tz_cp_config tz_cp_config_sm8250 = {
>> .cp_start = 0,
>> .cp_size = 0x25800000,
>> @@ -333,6 +338,7 @@ struct iris_platform_data sm8250_data = {
>> .opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table),
>> .clk_tbl = sm8250_clk_table,
>> .clk_tbl_size = ARRAY_SIZE(sm8250_clk_table),
>> + .opp_clk_tbl = sm8250_opp_clk_table,
>> /* Upper bound of DMA address range */
>> .dma_mask = 0xe0000000 - 1,
>> .fwname = "qcom/vpu-1.0/venus.mbn",
>> diff --git a/drivers/media/platform/qcom/iris/iris_power.c
>> b/drivers/media/platform/qcom/iris/iris_power.c
>> index
>> dbca42df0910fd3c0fb253dbfabf1afa2c3d32ad..91aa21d4070ebcebbe2ed127a03e5e49b9a2bd5c 100644
>> --- a/drivers/media/platform/qcom/iris/iris_power.c
>> +++ b/drivers/media/platform/qcom/iris/iris_power.c
>> @@ -91,7 +91,7 @@ static int iris_set_clocks(struct iris_inst *inst)
>> }
>>
>> core->power.clk_freq = freq;
>> - ret = dev_pm_opp_set_rate(core->dev, freq);
>> + ret = iris_opp_set_rate(core->dev, freq);
>> mutex_unlock(&core->lock);
>>
>> return ret;
>> diff --git a/drivers/media/platform/qcom/iris/iris_probe.c
>> b/drivers/media/platform/qcom/iris/iris_probe.c
>> index
>> 00e99be16e087c4098f930151fd76cd381d721ce..ad82a62f8b923d818ffe77c131d7eb6da8c34002 100644
>> --- a/drivers/media/platform/qcom/iris/iris_probe.c
>> +++ b/drivers/media/platform/qcom/iris/iris_probe.c
>> @@ -40,8 +40,6 @@ static int iris_init_icc(struct iris_core *core)
>>
>> static int iris_init_power_domains(struct iris_core *core)
>> {
>> - const struct platform_clk_data *clk_tbl;
>> - u32 clk_cnt, i;
>> int ret;
>>
>> struct dev_pm_domain_attach_data iris_pd_data = {
>> @@ -56,6 +54,11 @@ static int iris_init_power_domains(struct iris_core *core)
>> .pd_flags = PD_FLAG_DEV_LINK_ON | PD_FLAG_REQUIRED_OPP,
>> };
>>
>> + struct dev_pm_opp_config iris_opp_clk_data = {
>> + .clk_names = core->iris_platform_data->opp_clk_tbl,
>> + .config_clks = dev_pm_opp_config_clks_simple,
>> + };
>> +
>> ret = devm_pm_domain_attach_list(core->dev, &iris_pd_data,
>> &core->pmdomain_tbl);
>> if (ret < 0)
>> return ret;
>> @@ -64,16 +67,9 @@ static int iris_init_power_domains(struct iris_core *core)
>> if (ret < 0)
>> return ret;
>>
>> - clk_tbl = core->iris_platform_data->clk_tbl;
>> - clk_cnt = core->iris_platform_data->clk_tbl_size;
>> -
>> - for (i = 0; i < clk_cnt; i++) {
>> - if (clk_tbl[i].clk_type == IRIS_HW_CLK) {
>> - ret = devm_pm_opp_set_clkname(core->dev, clk_tbl[i].clk_name);
>> - if (ret)
>> - return ret;
>> - }
>> - }
>> + ret = devm_pm_opp_set_config(core->dev, &iris_opp_clk_data);
>> + if (ret)
>> + return ret;
>>
>> return devm_pm_opp_of_add_table(core->dev);
>> }
>> diff --git a/drivers/media/platform/qcom/iris/iris_resources.c
>> b/drivers/media/platform/qcom/iris/iris_resources.c
>> index
>> cf32f268b703c1c042a9bcf146e444fff4f4990d..939f6617f2631503fa8cb3e874b9de6b2fbe7b76 100644
>> --- a/drivers/media/platform/qcom/iris/iris_resources.c
>> +++ b/drivers/media/platform/qcom/iris/iris_resources.c
>> @@ -4,6 +4,7 @@
>> */
>>
>> #include <linux/clk.h>
>> +#include <linux/devfreq.h>
>> #include <linux/interconnect.h>
>> #include <linux/pm_domain.h>
>> #include <linux/pm_opp.h>
>> @@ -58,11 +59,22 @@ int iris_unset_icc_bw(struct iris_core *core)
>> return icc_bulk_set_bw(core->icc_count, core->icc_tbl);
>> }
>>
>> +int iris_opp_set_rate(struct device *dev, unsigned long freq)
>> +{
>> + struct dev_pm_opp *opp __free(put_opp);
>> +
>> + opp = devfreq_recommended_opp(dev, &freq, 0);
>> + if (IS_ERR(opp))
>> + return PTR_ERR(opp);
>> +
>> + return dev_pm_opp_set_opp(dev, opp);
>> +}
>> +
>
> I think this should be separated out from the clock setting and table usage into
> a second patch because you can end up with different clock frequencies here than
> before and being pedantic, I think that ought to be made explicit in the commit
> log.
The idea here is to keep the usage of the table alongwith introduction to clock
table. This way it even makes code review easier on how the table is utilized in
getting the opp and setting it.
Regards,
Vikash
>
>> int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev)
>> {
>> int ret;
>>
>> - ret = dev_pm_opp_set_rate(core->dev, ULONG_MAX);
>> + ret = iris_opp_set_rate(core->dev, ULONG_MAX);
>> if (ret)
>> return ret;
>>
>> @@ -77,7 +89,7 @@ int iris_disable_power_domains(struct iris_core *core,
>> struct device *pd_dev)
>> {
>> int ret;
>>
>> - ret = dev_pm_opp_set_rate(core->dev, 0);
>> + ret = iris_opp_set_rate(core->dev, 0);
>> if (ret)
>> return ret;
>>
>> diff --git a/drivers/media/platform/qcom/iris/iris_resources.h
>> b/drivers/media/platform/qcom/iris/iris_resources.h
>> index
>> f723dfe5bd81a9c9db22d53bde4e18743d771210..6bfbd2dc6db095ec05e53c894e048285f82446c6 100644
>> --- a/drivers/media/platform/qcom/iris/iris_resources.h
>> +++ b/drivers/media/platform/qcom/iris/iris_resources.h
>> @@ -8,6 +8,7 @@
>>
>> struct iris_core;
>>
>> +int iris_opp_set_rate(struct device *dev, unsigned long freq);
>> int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev);
>> int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev);
>> int iris_unset_icc_bw(struct iris_core *core);
>> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c
>> b/drivers/media/platform/qcom/iris/iris_vpu_common.c
>> index
>> bb98950e018fadf69ac4f41b3037f7fd6ac33c5b..bbd999a41236dca5cf5700e452a6fed69f4fc922 100644
>> --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
>> +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
>> @@ -266,7 +266,7 @@ void iris_vpu_power_off_hw(struct iris_core *core)
>>
>> void iris_vpu_power_off(struct iris_core *core)
>> {
>> - dev_pm_opp_set_rate(core->dev, 0);
>> + iris_opp_set_rate(core->dev, 0);
>> core->iris_platform_data->vpu_ops->power_off_hw(core);
>> core->iris_platform_data->vpu_ops->power_off_controller(core);
>> iris_unset_icc_bw(core);
>> @@ -352,7 +352,7 @@ int iris_vpu_power_on(struct iris_core *core)
>> freq = core->power.clk_freq ? core->power.clk_freq :
>> (u32)ULONG_MAX;
>>
>> - dev_pm_opp_set_rate(core->dev, freq);
>> + iris_opp_set_rate(core->dev, freq);
>>
>> core->iris_platform_data->set_preset_registers(core);
>>
>>
>> --
>> 2.34.1
>>
>>
>
> ---
> bod
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH 3/8] media: iris: Add support for multiple TZ CP configs
2025-09-24 23:14 [PATCH 0/8] media: iris: add support for video codecs on Qcom kaanapali platform Vikash Garodia
2025-09-24 23:14 ` [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding Vikash Garodia
2025-09-24 23:14 ` [PATCH 2/8] media: iris: Add support for multiple clock sources Vikash Garodia
@ 2025-09-24 23:14 ` Vikash Garodia
2025-09-25 9:01 ` Konrad Dybcio
2025-09-26 0:30 ` Bryan O'Donoghue
2025-09-24 23:14 ` [PATCH 4/8] media: iris: Introduce buffer size calculations for vpu4 Vikash Garodia
` (4 subsequent siblings)
7 siblings, 2 replies; 54+ messages in thread
From: Vikash Garodia @ 2025-09-24 23:14 UTC (permalink / raw)
To: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy, Vikash Garodia
vpu4 needs an additional configuration w.r.t CP regions. Make the CP
configuration as array such that the multiple configuration can be
managed per platform.
Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_firmware.c | 23 ++++++++++++---------
.../platform/qcom/iris/iris_platform_common.h | 3 ++-
.../media/platform/qcom/iris/iris_platform_gen2.c | 24 ++++++++++++++--------
.../platform/qcom/iris/iris_platform_sm8250.c | 15 ++++++++------
4 files changed, 39 insertions(+), 26 deletions(-)
diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c
index 9ab499fad946446a87036720f49c9c8d311f3060..ad65c419e4416d0531d4c3deb04c22d44b29e500 100644
--- a/drivers/media/platform/qcom/iris/iris_firmware.c
+++ b/drivers/media/platform/qcom/iris/iris_firmware.c
@@ -70,9 +70,9 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name)
int iris_fw_load(struct iris_core *core)
{
- struct tz_cp_config *cp_config = core->iris_platform_data->tz_cp_config_data;
+ const struct tz_cp_config *cp_config;
const char *fwpath = NULL;
- int ret;
+ int i, ret;
ret = of_property_read_string_index(core->dev->of_node, "firmware-name", 0,
&fwpath);
@@ -91,14 +91,17 @@ int iris_fw_load(struct iris_core *core)
return ret;
}
- ret = qcom_scm_mem_protect_video_var(cp_config->cp_start,
- cp_config->cp_size,
- cp_config->cp_nonpixel_start,
- cp_config->cp_nonpixel_size);
- if (ret) {
- dev_err(core->dev, "protect memory failed\n");
- qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
- return ret;
+ for (i = 0; i < core->iris_platform_data->tz_cp_config_data_size; i++) {
+ cp_config = &core->iris_platform_data->tz_cp_config_data[i];
+ ret = qcom_scm_mem_protect_video_var(cp_config->cp_start,
+ cp_config->cp_size,
+ cp_config->cp_nonpixel_start,
+ cp_config->cp_nonpixel_size);
+ if (ret) {
+ dev_err(core->dev, "protect memory failed\n");
+ qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
+ return ret;
+ }
}
return ret;
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index df03de08c44839c1b6c137874eb7273c638d5f2c..ae49e95ba2252fc1442f7c81d8010dbfd86da0da 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -220,7 +220,8 @@ struct iris_platform_data {
u32 inst_fw_caps_dec_size;
struct platform_inst_fw_cap *inst_fw_caps_enc;
u32 inst_fw_caps_enc_size;
- struct tz_cp_config *tz_cp_config_data;
+ const struct tz_cp_config *tz_cp_config_data;
+ u32 tz_cp_config_data_size;
u32 core_arch;
u32 hw_response_timeout;
struct ubwc_config_data *ubwc_config;
diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
index fea800811a389a58388175c733ad31c4d9c636b0..00c6b9021b98aac80612b1bb9734c8dac8146bd9 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
@@ -648,11 +648,13 @@ static struct ubwc_config_data ubwc_config_sm8550 = {
.bank_spreading = 1,
};
-static struct tz_cp_config tz_cp_config_sm8550 = {
- .cp_start = 0,
- .cp_size = 0x25800000,
- .cp_nonpixel_start = 0x01000000,
- .cp_nonpixel_size = 0x24800000,
+static const struct tz_cp_config tz_cp_config_sm8550[] = {
+ {
+ .cp_start = 0,
+ .cp_size = 0x25800000,
+ .cp_nonpixel_start = 0x01000000,
+ .cp_nonpixel_size = 0x24800000,
+ },
};
static const u32 sm8550_vdec_input_config_params_default[] = {
@@ -771,7 +773,8 @@ struct iris_platform_data sm8550_data = {
.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
.inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
- .tz_cp_config_data = &tz_cp_config_sm8550,
+ .tz_cp_config_data = tz_cp_config_sm8550,
+ .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
.core_arch = VIDEO_ARCH_LX,
.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
.ubwc_config = &ubwc_config_sm8550,
@@ -864,7 +867,8 @@ struct iris_platform_data sm8650_data = {
.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
.inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
- .tz_cp_config_data = &tz_cp_config_sm8550,
+ .tz_cp_config_data = tz_cp_config_sm8550,
+ .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
.core_arch = VIDEO_ARCH_LX,
.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
.ubwc_config = &ubwc_config_sm8550,
@@ -947,7 +951,8 @@ struct iris_platform_data sm8750_data = {
.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
.inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
- .tz_cp_config_data = &tz_cp_config_sm8550,
+ .tz_cp_config_data = tz_cp_config_sm8550,
+ .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
.core_arch = VIDEO_ARCH_LX,
.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
.ubwc_config = &ubwc_config_sm8550,
@@ -1035,7 +1040,8 @@ struct iris_platform_data qcs8300_data = {
.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_qcs8300_dec),
.inst_fw_caps_enc = inst_fw_cap_qcs8300_enc,
.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_qcs8300_enc),
- .tz_cp_config_data = &tz_cp_config_sm8550,
+ .tz_cp_config_data = tz_cp_config_sm8550,
+ .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
.core_arch = VIDEO_ARCH_LX,
.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
.ubwc_config = &ubwc_config_sm8550,
diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
index 1b1b6aa751106ee0b0bc71bb0df2e78340190e66..8927c3ff59dab59c7d2cbcd92550f9ee3a2b5c1e 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
@@ -278,11 +278,13 @@ static const char * const sm8250_opp_clk_table[] = {
NULL,
};
-static struct tz_cp_config tz_cp_config_sm8250 = {
- .cp_start = 0,
- .cp_size = 0x25800000,
- .cp_nonpixel_start = 0x01000000,
- .cp_nonpixel_size = 0x24800000,
+static const struct tz_cp_config tz_cp_config_sm8250[] = {
+ {
+ .cp_start = 0,
+ .cp_size = 0x25800000,
+ .cp_nonpixel_start = 0x01000000,
+ .cp_nonpixel_size = 0x24800000,
+ },
};
static const u32 sm8250_vdec_input_config_param_default[] = {
@@ -348,7 +350,8 @@ struct iris_platform_data sm8250_data = {
.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8250_dec),
.inst_fw_caps_enc = inst_fw_cap_sm8250_enc,
.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc),
- .tz_cp_config_data = &tz_cp_config_sm8250,
+ .tz_cp_config_data = tz_cp_config_sm8250,
+ .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250),
.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
.num_vpp_pipe = 4,
.max_session_count = 16,
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH 3/8] media: iris: Add support for multiple TZ CP configs
2025-09-24 23:14 ` [PATCH 3/8] media: iris: Add support for multiple TZ CP configs Vikash Garodia
@ 2025-09-25 9:01 ` Konrad Dybcio
2025-09-25 19:27 ` Vikash Garodia
2025-09-26 0:30 ` Bryan O'Donoghue
1 sibling, 1 reply; 54+ messages in thread
From: Konrad Dybcio @ 2025-09-25 9:01 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 9/25/25 1:14 AM, Vikash Garodia wrote:
> vpu4 needs an additional configuration w.r.t CP regions. Make the CP
> configuration as array such that the multiple configuration can be
> managed per platform.
>
> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> ---
[...]
> - ret = qcom_scm_mem_protect_video_var(cp_config->cp_start,
> - cp_config->cp_size,
> - cp_config->cp_nonpixel_start,
> - cp_config->cp_nonpixel_size);
> - if (ret) {
> - dev_err(core->dev, "protect memory failed\n");
> - qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
> - return ret;
> + for (i = 0; i < core->iris_platform_data->tz_cp_config_data_size; i++) {
> + cp_config = &core->iris_platform_data->tz_cp_config_data[i];
> + ret = qcom_scm_mem_protect_video_var(cp_config->cp_start,
> + cp_config->cp_size,
> + cp_config->cp_nonpixel_start,
> + cp_config->cp_nonpixel_size);
> + if (ret) {
> + dev_err(core->dev, "protect memory failed\n");
> + qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
> + return ret;
> + }
> }
Do we need to do any "un-protecting" when unrolling from an error?
Konrad
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH 3/8] media: iris: Add support for multiple TZ CP configs
2025-09-25 9:01 ` Konrad Dybcio
@ 2025-09-25 19:27 ` Vikash Garodia
2025-09-26 11:44 ` Konrad Dybcio
0 siblings, 1 reply; 54+ messages in thread
From: Vikash Garodia @ 2025-09-25 19:27 UTC (permalink / raw)
To: Konrad Dybcio, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 9/25/2025 2:31 PM, Konrad Dybcio wrote:
> On 9/25/25 1:14 AM, Vikash Garodia wrote:
>> vpu4 needs an additional configuration w.r.t CP regions. Make the CP
>> configuration as array such that the multiple configuration can be
>> managed per platform.
>>
>> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
>> ---
>
> [...]
>
>> - ret = qcom_scm_mem_protect_video_var(cp_config->cp_start,
>> - cp_config->cp_size,
>> - cp_config->cp_nonpixel_start,
>> - cp_config->cp_nonpixel_size);
>> - if (ret) {
>> - dev_err(core->dev, "protect memory failed\n");
>> - qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
>> - return ret;
>> + for (i = 0; i < core->iris_platform_data->tz_cp_config_data_size; i++) {
>> + cp_config = &core->iris_platform_data->tz_cp_config_data[i];
>> + ret = qcom_scm_mem_protect_video_var(cp_config->cp_start,
>> + cp_config->cp_size,
>> + cp_config->cp_nonpixel_start,
>> + cp_config->cp_nonpixel_size);
>> + if (ret) {
>> + dev_err(core->dev, "protect memory failed\n");
>> + qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
>> + return ret;
>> + }
>> }
>
> Do we need to do any "un-protecting" when unrolling from an error?
Not needed for unwinding part.
Regards,
Vikash
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH 3/8] media: iris: Add support for multiple TZ CP configs
2025-09-25 19:27 ` Vikash Garodia
@ 2025-09-26 11:44 ` Konrad Dybcio
0 siblings, 0 replies; 54+ messages in thread
From: Konrad Dybcio @ 2025-09-26 11:44 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 9/25/25 9:27 PM, Vikash Garodia wrote:
>
> On 9/25/2025 2:31 PM, Konrad Dybcio wrote:
>> On 9/25/25 1:14 AM, Vikash Garodia wrote:
>>> vpu4 needs an additional configuration w.r.t CP regions. Make the CP
>>> configuration as array such that the multiple configuration can be
>>> managed per platform.
>>>
>>> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>>> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>>> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
>>> ---
>>
>> [...]
>>
>>> - ret = qcom_scm_mem_protect_video_var(cp_config->cp_start,
>>> - cp_config->cp_size,
>>> - cp_config->cp_nonpixel_start,
>>> - cp_config->cp_nonpixel_size);
>>> - if (ret) {
>>> - dev_err(core->dev, "protect memory failed\n");
>>> - qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
>>> - return ret;
>>> + for (i = 0; i < core->iris_platform_data->tz_cp_config_data_size; i++) {
>>> + cp_config = &core->iris_platform_data->tz_cp_config_data[i];
>>> + ret = qcom_scm_mem_protect_video_var(cp_config->cp_start,
>>> + cp_config->cp_size,
>>> + cp_config->cp_nonpixel_start,
>>> + cp_config->cp_nonpixel_size);
>>> + if (ret) {
>>> + dev_err(core->dev, "protect memory failed\n");
>>> + qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
>>> + return ret;
>>> + }
>>> }
>>
>> Do we need to do any "un-protecting" when unrolling from an error?
>
> Not needed for unwinding part.
Thanks for confirming
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH 3/8] media: iris: Add support for multiple TZ CP configs
2025-09-24 23:14 ` [PATCH 3/8] media: iris: Add support for multiple TZ CP configs Vikash Garodia
2025-09-25 9:01 ` Konrad Dybcio
@ 2025-09-26 0:30 ` Bryan O'Donoghue
2025-09-29 5:45 ` Vishnu Reddy
1 sibling, 1 reply; 54+ messages in thread
From: Bryan O'Donoghue @ 2025-09-26 0:30 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 25/09/2025 00:14, Vikash Garodia wrote:
> vpu4 needs an additional configuration w.r.t CP regions. Make the CP
"with-respect-to" and please define CP once and then use the
abbreviation liberally.
> configuration as array such that the multiple configuration can be
> managed per platform.
>
> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/iris/iris_firmware.c | 23 ++++++++++++---------
> .../platform/qcom/iris/iris_platform_common.h | 3 ++-
> .../media/platform/qcom/iris/iris_platform_gen2.c | 24 ++++++++++++++--------
> .../platform/qcom/iris/iris_platform_sm8250.c | 15 ++++++++------
> 4 files changed, 39 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c
> index 9ab499fad946446a87036720f49c9c8d311f3060..ad65c419e4416d0531d4c3deb04c22d44b29e500 100644
> --- a/drivers/media/platform/qcom/iris/iris_firmware.c
> +++ b/drivers/media/platform/qcom/iris/iris_firmware.c
> @@ -70,9 +70,9 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name)
>
> int iris_fw_load(struct iris_core *core)
> {
> - struct tz_cp_config *cp_config = core->iris_platform_data->tz_cp_config_data;
> + const struct tz_cp_config *cp_config;
> const char *fwpath = NULL;
> - int ret;
> + int i, ret;
>
> ret = of_property_read_string_index(core->dev->of_node, "firmware-name", 0,
> &fwpath);
> @@ -91,14 +91,17 @@ int iris_fw_load(struct iris_core *core)
> return ret;
> }
>
> - ret = qcom_scm_mem_protect_video_var(cp_config->cp_start,
> - cp_config->cp_size,
> - cp_config->cp_nonpixel_start,
> - cp_config->cp_nonpixel_size);
> - if (ret) {
> - dev_err(core->dev, "protect memory failed\n");
> - qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
> - return ret;
> + for (i = 0; i < core->iris_platform_data->tz_cp_config_data_size; i++) {
> + cp_config = &core->iris_platform_data->tz_cp_config_data[i];
> + ret = qcom_scm_mem_protect_video_var(cp_config->cp_start,
> + cp_config->cp_size,
> + cp_config->cp_nonpixel_start,
> + cp_config->cp_nonpixel_size);
> + if (ret) {
> + dev_err(core->dev, "protect memory failed\n");
I think this error message could be better ->
"qcom_scm_mem_protect_video_var()=%d" or err string.
Its not super-important just an observation.
> + qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
> + return ret;
> + }
> }
>
> return ret;
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
> index df03de08c44839c1b6c137874eb7273c638d5f2c..ae49e95ba2252fc1442f7c81d8010dbfd86da0da 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
> @@ -220,7 +220,8 @@ struct iris_platform_data {
> u32 inst_fw_caps_dec_size;
> struct platform_inst_fw_cap *inst_fw_caps_enc;
> u32 inst_fw_caps_enc_size;
> - struct tz_cp_config *tz_cp_config_data;
> + const struct tz_cp_config *tz_cp_config_data;
> + u32 tz_cp_config_data_size;
> u32 core_arch;
> u32 hw_response_timeout;
> struct ubwc_config_data *ubwc_config;
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> index fea800811a389a58388175c733ad31c4d9c636b0..00c6b9021b98aac80612b1bb9734c8dac8146bd9 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> @@ -648,11 +648,13 @@ static struct ubwc_config_data ubwc_config_sm8550 = {
> .bank_spreading = 1,
> };
>
> -static struct tz_cp_config tz_cp_config_sm8550 = {
> - .cp_start = 0,
> - .cp_size = 0x25800000,
> - .cp_nonpixel_start = 0x01000000,
> - .cp_nonpixel_size = 0x24800000,
> +static const struct tz_cp_config tz_cp_config_sm8550[] = {
> + {
> + .cp_start = 0,
> + .cp_size = 0x25800000,
> + .cp_nonpixel_start = 0x01000000,
> + .cp_nonpixel_size = 0x24800000,
> + },
> };
>
> static const u32 sm8550_vdec_input_config_params_default[] = {
> @@ -771,7 +773,8 @@ struct iris_platform_data sm8550_data = {
> .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
> .inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
> .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
> - .tz_cp_config_data = &tz_cp_config_sm8550,
> + .tz_cp_config_data = tz_cp_config_sm8550,
> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
> .core_arch = VIDEO_ARCH_LX,
> .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> .ubwc_config = &ubwc_config_sm8550,
> @@ -864,7 +867,8 @@ struct iris_platform_data sm8650_data = {
> .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
> .inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
> .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
> - .tz_cp_config_data = &tz_cp_config_sm8550,
> + .tz_cp_config_data = tz_cp_config_sm8550,
> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
> .core_arch = VIDEO_ARCH_LX,
> .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> .ubwc_config = &ubwc_config_sm8550,
> @@ -947,7 +951,8 @@ struct iris_platform_data sm8750_data = {
> .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
> .inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
> .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
> - .tz_cp_config_data = &tz_cp_config_sm8550,
> + .tz_cp_config_data = tz_cp_config_sm8550,
> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
> .core_arch = VIDEO_ARCH_LX,
> .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> .ubwc_config = &ubwc_config_sm8550,
> @@ -1035,7 +1040,8 @@ struct iris_platform_data qcs8300_data = {
> .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_qcs8300_dec),
> .inst_fw_caps_enc = inst_fw_cap_qcs8300_enc,
> .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_qcs8300_enc),
> - .tz_cp_config_data = &tz_cp_config_sm8550,
> + .tz_cp_config_data = tz_cp_config_sm8550,
> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
> .core_arch = VIDEO_ARCH_LX,
> .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> .ubwc_config = &ubwc_config_sm8550,
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
> index 1b1b6aa751106ee0b0bc71bb0df2e78340190e66..8927c3ff59dab59c7d2cbcd92550f9ee3a2b5c1e 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
> @@ -278,11 +278,13 @@ static const char * const sm8250_opp_clk_table[] = {
> NULL,
> };
>
> -static struct tz_cp_config tz_cp_config_sm8250 = {
> - .cp_start = 0,
> - .cp_size = 0x25800000,
> - .cp_nonpixel_start = 0x01000000,
> - .cp_nonpixel_size = 0x24800000,
> +static const struct tz_cp_config tz_cp_config_sm8250[] = {
> + {
> + .cp_start = 0,
> + .cp_size = 0x25800000,
> + .cp_nonpixel_start = 0x01000000,
> + .cp_nonpixel_size = 0x24800000,
> + },
> };
>
> static const u32 sm8250_vdec_input_config_param_default[] = {
> @@ -348,7 +350,8 @@ struct iris_platform_data sm8250_data = {
> .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8250_dec),
> .inst_fw_caps_enc = inst_fw_cap_sm8250_enc,
> .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc),
> - .tz_cp_config_data = &tz_cp_config_sm8250,
> + .tz_cp_config_data = tz_cp_config_sm8250,
> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250),
> .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> .num_vpp_pipe = 4,
> .max_session_count = 16,
>
> --
> 2.34.1
>
>
Please tidy up the commit log.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH 3/8] media: iris: Add support for multiple TZ CP configs
2025-09-26 0:30 ` Bryan O'Donoghue
@ 2025-09-29 5:45 ` Vishnu Reddy
0 siblings, 0 replies; 54+ messages in thread
From: Vishnu Reddy @ 2025-09-29 5:45 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel
On 9/26/2025 6:00 AM, Bryan O'Donoghue wrote:
> On 25/09/2025 00:14, Vikash Garodia wrote:
>> vpu4 needs an additional configuration w.r.t CP regions. Make the CP
>
> "with-respect-to" and please define CP once and then use the
> abbreviation liberally.
>> configuration as array such that the multiple configuration can be
>> managed per platform.
>>
>> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
>> ---
>> drivers/media/platform/qcom/iris/iris_firmware.c | 23
>> ++++++++++++---------
>> .../platform/qcom/iris/iris_platform_common.h | 3 ++-
>> .../media/platform/qcom/iris/iris_platform_gen2.c | 24
>> ++++++++++++++--------
>> .../platform/qcom/iris/iris_platform_sm8250.c | 15 ++++++++------
>> 4 files changed, 39 insertions(+), 26 deletions(-)
>>
>> diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c
>> b/drivers/media/platform/qcom/iris/iris_firmware.c
>> index
>> 9ab499fad946446a87036720f49c9c8d311f3060..ad65c419e4416d0531d4c3deb04c22d44b29e500 100644
>> --- a/drivers/media/platform/qcom/iris/iris_firmware.c
>> +++ b/drivers/media/platform/qcom/iris/iris_firmware.c
>> @@ -70,9 +70,9 @@ static int iris_load_fw_to_memory(struct iris_core
>> *core, const char *fw_name)
>>
>> int iris_fw_load(struct iris_core *core)
>> {
>> - struct tz_cp_config *cp_config =
>> core->iris_platform_data->tz_cp_config_data;
>> + const struct tz_cp_config *cp_config;
>> const char *fwpath = NULL;
>> - int ret;
>> + int i, ret;
>>
>> ret = of_property_read_string_index(core->dev->of_node,
>> "firmware-name", 0,
>> &fwpath);
>> @@ -91,14 +91,17 @@ int iris_fw_load(struct iris_core *core)
>> return ret;
>> }
>>
>> - ret = qcom_scm_mem_protect_video_var(cp_config->cp_start,
>> - cp_config->cp_size,
>> - cp_config->cp_nonpixel_start,
>> - cp_config->cp_nonpixel_size);
>> - if (ret) {
>> - dev_err(core->dev, "protect memory failed\n");
>> - qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
>> - return ret;
>> + for (i = 0; i < core->iris_platform_data->tz_cp_config_data_size;
>> i++) {
>> + cp_config = &core->iris_platform_data->tz_cp_config_data[i];
>> + ret = qcom_scm_mem_protect_video_var(cp_config->cp_start,
>> + cp_config->cp_size,
>> + cp_config->cp_nonpixel_start,
>> + cp_config->cp_nonpixel_size);
>> + if (ret) {
>> + dev_err(core->dev, "protect memory failed\n");
>
> I think this error message could be better ->
> "qcom_scm_mem_protect_video_var()=%d" or err string.
>
> Its not super-important just an observation.
>
ACK.
>> + qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
>> + return ret;
>> + }
>> }
>>
>> return ret;
>> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h
>> b/drivers/media/platform/qcom/iris/iris_platform_common.h
>> index
>> df03de08c44839c1b6c137874eb7273c638d5f2c..ae49e95ba2252fc1442f7c81d8010dbfd86da0da 100644
>> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
>> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
>> @@ -220,7 +220,8 @@ struct iris_platform_data {
>> u32 inst_fw_caps_dec_size;
>> struct platform_inst_fw_cap *inst_fw_caps_enc;
>> u32 inst_fw_caps_enc_size;
>> - struct tz_cp_config *tz_cp_config_data;
>> + const struct tz_cp_config *tz_cp_config_data;
>> + u32 tz_cp_config_data_size;
>> u32 core_arch;
>> u32 hw_response_timeout;
>> struct ubwc_config_data *ubwc_config;
>> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
>> b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
>> index
>> fea800811a389a58388175c733ad31c4d9c636b0..00c6b9021b98aac80612b1bb9734c8dac8146bd9 100644
>> --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
>> +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
>> @@ -648,11 +648,13 @@ static struct ubwc_config_data
>> ubwc_config_sm8550 = {
>> .bank_spreading = 1,
>> };
>>
>> -static struct tz_cp_config tz_cp_config_sm8550 = {
>> - .cp_start = 0,
>> - .cp_size = 0x25800000,
>> - .cp_nonpixel_start = 0x01000000,
>> - .cp_nonpixel_size = 0x24800000,
>> +static const struct tz_cp_config tz_cp_config_sm8550[] = {
>> + {
>> + .cp_start = 0,
>> + .cp_size = 0x25800000,
>> + .cp_nonpixel_start = 0x01000000,
>> + .cp_nonpixel_size = 0x24800000,
>> + },
>> };
>>
>> static const u32 sm8550_vdec_input_config_params_default[] = {
>> @@ -771,7 +773,8 @@ struct iris_platform_data sm8550_data = {
>> .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
>> .inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
>> .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
>> - .tz_cp_config_data = &tz_cp_config_sm8550,
>> + .tz_cp_config_data = tz_cp_config_sm8550,
>> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
>> .core_arch = VIDEO_ARCH_LX,
>> .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
>> .ubwc_config = &ubwc_config_sm8550,
>> @@ -864,7 +867,8 @@ struct iris_platform_data sm8650_data = {
>> .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
>> .inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
>> .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
>> - .tz_cp_config_data = &tz_cp_config_sm8550,
>> + .tz_cp_config_data = tz_cp_config_sm8550,
>> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
>> .core_arch = VIDEO_ARCH_LX,
>> .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
>> .ubwc_config = &ubwc_config_sm8550,
>> @@ -947,7 +951,8 @@ struct iris_platform_data sm8750_data = {
>> .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
>> .inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
>> .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
>> - .tz_cp_config_data = &tz_cp_config_sm8550,
>> + .tz_cp_config_data = tz_cp_config_sm8550,
>> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
>> .core_arch = VIDEO_ARCH_LX,
>> .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
>> .ubwc_config = &ubwc_config_sm8550,
>> @@ -1035,7 +1040,8 @@ struct iris_platform_data qcs8300_data = {
>> .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_qcs8300_dec),
>> .inst_fw_caps_enc = inst_fw_cap_qcs8300_enc,
>> .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_qcs8300_enc),
>> - .tz_cp_config_data = &tz_cp_config_sm8550,
>> + .tz_cp_config_data = tz_cp_config_sm8550,
>> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
>> .core_arch = VIDEO_ARCH_LX,
>> .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
>> .ubwc_config = &ubwc_config_sm8550,
>> diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
>> b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
>> index
>> 1b1b6aa751106ee0b0bc71bb0df2e78340190e66..8927c3ff59dab59c7d2cbcd92550f9ee3a2b5c1e 100644
>> --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
>> +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
>> @@ -278,11 +278,13 @@ static const char * const sm8250_opp_clk_table[]
>> = {
>> NULL,
>> };
>>
>> -static struct tz_cp_config tz_cp_config_sm8250 = {
>> - .cp_start = 0,
>> - .cp_size = 0x25800000,
>> - .cp_nonpixel_start = 0x01000000,
>> - .cp_nonpixel_size = 0x24800000,
>> +static const struct tz_cp_config tz_cp_config_sm8250[] = {
>> + {
>> + .cp_start = 0,
>> + .cp_size = 0x25800000,
>> + .cp_nonpixel_start = 0x01000000,
>> + .cp_nonpixel_size = 0x24800000,
>> + },
>> };
>>
>> static const u32 sm8250_vdec_input_config_param_default[] = {
>> @@ -348,7 +350,8 @@ struct iris_platform_data sm8250_data = {
>> .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8250_dec),
>> .inst_fw_caps_enc = inst_fw_cap_sm8250_enc,
>> .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc),
>> - .tz_cp_config_data = &tz_cp_config_sm8250,
>> + .tz_cp_config_data = tz_cp_config_sm8250,
>> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250),
>> .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
>> .num_vpp_pipe = 4,
>> .max_session_count = 16,
>>
>> --
>> 2.34.1
>>
>>
>
> Please tidy up the commit log.
>
> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
ACK.
Regards,
Vishnu Reddy
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH 4/8] media: iris: Introduce buffer size calculations for vpu4
2025-09-24 23:14 [PATCH 0/8] media: iris: add support for video codecs on Qcom kaanapali platform Vikash Garodia
` (2 preceding siblings ...)
2025-09-24 23:14 ` [PATCH 3/8] media: iris: Add support for multiple TZ CP configs Vikash Garodia
@ 2025-09-24 23:14 ` Vikash Garodia
2025-09-26 13:00 ` Bryan O'Donoghue
2025-09-24 23:14 ` [PATCH 5/8] media: iris: Move vpu register defines to common header file Vikash Garodia
` (3 subsequent siblings)
7 siblings, 1 reply; 54+ messages in thread
From: Vikash Garodia @ 2025-09-24 23:14 UTC (permalink / raw)
To: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy, Vikash Garodia
Introduces vp4 buffer size calculation for both encoder and decoder.
Reuse the buffer size calculation which are common, while adding the
vpu4 ones separately.
Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 289 +++++++++++++++++++++
drivers/media/platform/qcom/iris/iris_vpu_buffer.h | 5 +-
2 files changed, 293 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
index 4463be05ce165adef6b152eb0c155d2e6a7b3c36..a08925e941b34d6df86b19ca52691327c020c811 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
@@ -1408,6 +1408,251 @@ static u32 iris_vpu_enc_vpss_size(struct iris_inst *inst)
return hfi_buffer_vpss_enc(width, height, ds_enable, 0, 0);
}
+static u32 hfi_vpu4x_vp9d_lb_size(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
+{
+ u32 max_value = max(frame_width, frame_height);
+ u32 size_vp9d_qp = DIV_ROUND_UP(frame_width, 64) * DIV_ROUND_UP(frame_height, 64) * 128;
+ u32 size_dpb_obp = (ALIGN(max_value, 64) * 192) + (256 * 6);
+ u32 size_vp9d_fe_left_lb = ALIGN(max_value, 64) * 492;
+ u32 size_vp9d_top_lb = (ALIGN(max_value, 64) * 190) + 256;
+ u32 size_vp9d_se_left_lb = ALIGN(max_value, 64);
+
+ return size_vp9d_qp + (size_dpb_obp * num_vpp_pipes) + size_vp9d_fe_left_lb +
+ size_vp9d_top_lb + (size_vp9d_se_left_lb * num_vpp_pipes);
+}
+
+static u32 hfi_vpu4x_buffer_line_vp9d(u32 frame_width, u32 frame_height, u32 _yuv_bufcount_min,
+ bool is_opb, u32 num_vpp_pipes)
+{
+ u32 lb_size = hfi_vpu4x_vp9d_lb_size(frame_width, frame_height, num_vpp_pipes);
+ u32 dpb_obp_size = 0;
+
+ if (is_opb)
+ dpb_obp_size = ((ALIGN(max(frame_width, frame_height), 64) * 192) + (256 * 6)) *
+ num_vpp_pipes;
+
+ return lb_size + dpb_obp_size;
+}
+
+static u32 iris_vpu4x_dec_line_size(struct iris_inst *inst)
+{
+ u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
+ u32 out_min_count = inst->buffers[BUF_OUTPUT].min_count;
+ struct v4l2_format *f = inst->fmt_src;
+ u32 height = f->fmt.pix_mp.height;
+ u32 width = f->fmt.pix_mp.width;
+ bool is_opb = false;
+
+ if (iris_split_mode_enabled(inst))
+ is_opb = true;
+
+ if (inst->codec == V4L2_PIX_FMT_H264)
+ return hfi_buffer_line_h264d(width, height, is_opb, num_vpp_pipes);
+ else if (inst->codec == V4L2_PIX_FMT_HEVC)
+ return hfi_buffer_line_h265d(width, height, is_opb, num_vpp_pipes);
+ else if (inst->codec == V4L2_PIX_FMT_VP9)
+ return hfi_vpu4x_buffer_line_vp9d(width, height, out_min_count, is_opb,
+ num_vpp_pipes);
+
+ return 0;
+}
+
+static u32 hfi_buffer4x_persist_h265d(u32 rpu_enabled)
+{
+ return ALIGN((SIZE_SLIST_BUF_H265 * NUM_SLIST_BUF_H265 + H265_NUM_FRM_INFO *
+ H265_DISPLAY_BUF_SIZE + (H265_NUM_TILE * sizeof(u32)) + (NUM_HW_PIC_BUF *
+ (SIZE_SEI_USERDATA + SIZE_H265D_ARP + SIZE_THREE_DIMENSION_USERDATA)) +
+ rpu_enabled * NUM_HW_PIC_BUF * SIZE_DOLBY_RPU_METADATA), DMA_ALIGNMENT);
+}
+
+static u32 iris_vpu4x_dec_persist_size(struct iris_inst *inst)
+{
+ if (inst->codec == V4L2_PIX_FMT_H264)
+ return hfi_buffer_persist_h264d();
+ else if (inst->codec == V4L2_PIX_FMT_HEVC)
+ return hfi_buffer4x_persist_h265d(0);
+ else if (inst->codec == V4L2_PIX_FMT_VP9)
+ return hfi_buffer_persist_vp9d();
+
+ return 0;
+}
+
+static u32 size_se_lb(u32 standard, u32 num_vpp_pipes_enc,
+ u32 frame_width_coded, u32 frame_height_coded)
+{
+ u32 se_tlb_size = ALIGN(frame_width_coded, DMA_ALIGNMENT);
+ u32 se_llb_size = (standard == HFI_CODEC_ENCODE_HEVC) ?
+ ((frame_height_coded + 32 - 1) / 32) * 4 * 16 :
+ ((frame_height_coded + 16 - 1) / 16) * 5 * 16;
+
+ se_llb_size = ALIGN(se_llb_size, 32);
+
+ if (num_vpp_pipes_enc > 1)
+ se_llb_size = ALIGN(se_llb_size + 512, DMA_ALIGNMENT) * num_vpp_pipes_enc;
+
+ return ALIGN(se_tlb_size + se_llb_size, DMA_ALIGNMENT);
+}
+
+static u32 size_te_lb(bool is_ten_bit, u32 num_vpp_pipes_enc, u32 width_in_lcus,
+ u32 frame_height_coded, u32 frame_width_coded)
+{
+ u32 te_llb_col_rc_size = ALIGN(32 * width_in_lcus / num_vpp_pipes_enc,
+ DMA_ALIGNMENT) * num_vpp_pipes_enc;
+ u32 te_tlb_recon_data_size = ALIGN((is_ten_bit ? 3 : 2) * frame_width_coded,
+ DMA_ALIGNMENT);
+ u32 te_llb_recon_data_size = ((1 + is_ten_bit) * 3 * frame_height_coded +
+ num_vpp_pipes_enc - 1) / num_vpp_pipes_enc;
+ te_llb_recon_data_size = ALIGN(te_llb_recon_data_size, DMA_ALIGNMENT) * num_vpp_pipes_enc;
+
+ return ALIGN(te_llb_recon_data_size + te_llb_col_rc_size + te_tlb_recon_data_size,
+ DMA_ALIGNMENT);
+}
+
+static u32 size_fe_lb(bool is_ten_bit, u32 standard, u32 num_vpp_pipes_enc,
+ u32 frame_height_coded, u32 frame_width_coded)
+{
+ u32 log2_lcu_size, num_cu_in_height_pipe, num_cu_in_width,
+ fb_llb_db_ctrl_size, fb_llb_db_luma_size, fb_llb_db_chroma_size,
+ fb_tlb_db_ctrl_size, fb_tlb_db_luma_size, fb_tlb_db_chroma_size,
+ fb_llb_sao_ctrl_size, fb_llb_sao_luma_size,
+ fb_llb_sao_chroma_size, fb_tlb_sao_ctrl_size,
+ fb_tlb_sao_luma_size, fb_tlb_sao_chroma_size,
+ fb_lb_top_sdc_size, fb_lb_se_ctrl_size, fe_tlb_size,
+ size_per_lcu;
+
+ log2_lcu_size = (standard == HFI_CODEC_ENCODE_HEVC) ? 5 : 4;
+ num_cu_in_height_pipe = ((frame_height_coded >> log2_lcu_size) + num_vpp_pipes_enc - 1) /
+ num_vpp_pipes_enc;
+ num_cu_in_width = frame_width_coded >> log2_lcu_size;
+
+ size_per_lcu = 2;
+ fe_tlb_size = is_ten_bit ? (128 * (size_per_lcu + 1)) : (size_per_lcu * 64);
+ fb_llb_db_ctrl_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_height_pipe;
+ fb_llb_db_ctrl_size = ALIGN(fb_llb_db_ctrl_size, DMA_ALIGNMENT) * num_vpp_pipes_enc;
+
+ size_per_lcu = (1 << (log2_lcu_size - 3));
+ fe_tlb_size = is_ten_bit ? (128 * (size_per_lcu + 1)) : (size_per_lcu * 64);
+ fb_llb_db_luma_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_height_pipe;
+ fb_llb_db_luma_size = ALIGN(fb_llb_db_luma_size, DMA_ALIGNMENT) * num_vpp_pipes_enc;
+
+ size_per_lcu = ((1 << (log2_lcu_size - 4)) * 2);
+ fe_tlb_size = is_ten_bit ? (128 * (size_per_lcu + 1)) : (size_per_lcu * 64);
+ fb_llb_db_chroma_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_height_pipe;
+ fb_llb_db_chroma_size = ALIGN(fb_llb_db_chroma_size, DMA_ALIGNMENT) * num_vpp_pipes_enc;
+
+ size_per_lcu = 1;
+ fe_tlb_size = 1 ? (128 * (size_per_lcu + 1)) : (size_per_lcu * 64);
+ fb_tlb_db_ctrl_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_width;
+
+ size_per_lcu = ((1 << (log2_lcu_size - 3)) + 1);
+ fe_tlb_size = is_ten_bit ? (128 * (size_per_lcu + 1)) : (size_per_lcu * 64);
+ fb_tlb_db_luma_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_width;
+
+ size_per_lcu = (2 * ((1 << (log2_lcu_size - 4)) + 1));
+ fe_tlb_size = is_ten_bit ? (128 * (size_per_lcu + 1)) : (size_per_lcu * 64);
+ fb_tlb_db_chroma_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_width;
+
+ size_per_lcu = 1;
+ fe_tlb_size = 1 ? (128 * (size_per_lcu + 1)) : (size_per_lcu * 64);
+ fb_llb_sao_ctrl_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_height_pipe;
+ fb_llb_sao_ctrl_size = fb_llb_sao_ctrl_size * num_vpp_pipes_enc;
+
+ fb_llb_sao_luma_size = 256 * num_vpp_pipes_enc;
+ fb_llb_sao_chroma_size = 256 * num_vpp_pipes_enc;
+
+ size_per_lcu = 1;
+ fe_tlb_size = 1 ? (128 * (size_per_lcu + 1)) : (size_per_lcu * 64);
+ fb_tlb_sao_ctrl_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_width;
+
+ fb_tlb_sao_luma_size = 256;
+ fb_tlb_sao_chroma_size = 256;
+ fb_lb_top_sdc_size = ALIGN((16 * (frame_width_coded >> 5)), DMA_ALIGNMENT);
+
+ fb_lb_se_ctrl_size = ALIGN((2020 * (frame_width_coded >> 5)), DMA_ALIGNMENT);
+
+ return fb_llb_db_ctrl_size + fb_llb_db_luma_size + fb_llb_db_chroma_size +
+ fb_tlb_db_ctrl_size + fb_tlb_db_luma_size + fb_tlb_db_chroma_size +
+ fb_llb_sao_ctrl_size + fb_llb_sao_luma_size + fb_llb_sao_chroma_size +
+ fb_tlb_sao_ctrl_size + fb_tlb_sao_luma_size + fb_tlb_sao_chroma_size +
+ fb_lb_top_sdc_size + fb_lb_se_ctrl_size;
+}
+
+static u32 size_md_lb(u32 standard, u32 frame_width_coded,
+ u32 frame_height_coded, u32 num_vpp_pipes_enc)
+{
+ u32 md_tlb_size = ALIGN(frame_width_coded, DMA_ALIGNMENT);
+ u32 md_llb_size = (standard == HFI_CODEC_ENCODE_HEVC) ?
+ ((frame_height_coded + 32 - 1) / 32) * 4 * 16 :
+ ((frame_height_coded + 16 - 1) / 16) * 5 * 16;
+
+ md_llb_size = ALIGN(md_llb_size, 32);
+
+ if (num_vpp_pipes_enc > 1)
+ md_llb_size = ALIGN(md_llb_size + 512, DMA_ALIGNMENT) * num_vpp_pipes_enc;
+
+ md_llb_size = ALIGN(md_llb_size, DMA_ALIGNMENT);
+
+ return ALIGN(md_tlb_size + md_llb_size, DMA_ALIGNMENT);
+}
+
+static u32 size_dma_opb_lb(u32 num_vpp_pipes_enc, u32 frame_width_coded,
+ u32 frame_height_coded)
+{
+ u32 dma_opb_wr_tlb_y_size = ((frame_width_coded + 15) >> 4) << 7;
+ u32 dma_opb_wr_tlb_uv_size = ((frame_width_coded + 15) >> 4) << 7;
+ u32 dma_opb_wr2_tlb_y_size = ALIGN((2 * 6 * 64 * frame_height_coded / 8), DMA_ALIGNMENT) *
+ num_vpp_pipes_enc;
+ u32 dma_opb_wr2_tlb_uv_size = ALIGN((2 * 6 * 64 * frame_height_coded / 8), DMA_ALIGNMENT) *
+ num_vpp_pipes_enc;
+
+ dma_opb_wr2_tlb_y_size = max(dma_opb_wr2_tlb_y_size, dma_opb_wr_tlb_y_size << 1);
+ dma_opb_wr2_tlb_uv_size = max(dma_opb_wr2_tlb_uv_size, dma_opb_wr_tlb_uv_size << 1);
+
+ return ALIGN(dma_opb_wr_tlb_y_size + dma_opb_wr_tlb_uv_size + dma_opb_wr2_tlb_y_size +
+ dma_opb_wr2_tlb_uv_size, DMA_ALIGNMENT);
+}
+
+static u32 hfi_vpu4x_buffer_line_enc(u32 frame_width, u32 frame_height,
+ bool is_ten_bit, u32 num_vpp_pipes_enc,
+ u32 lcu_size, u32 standard)
+{
+ u32 width_in_lcus = (frame_width + lcu_size - 1) / lcu_size;
+ u32 height_in_lcus = (frame_height + lcu_size - 1) / lcu_size;
+ u32 frame_width_coded = width_in_lcus * lcu_size;
+ u32 frame_height_coded = height_in_lcus * lcu_size;
+
+ u32 se_lb_size = size_se_lb(standard, num_vpp_pipes_enc, frame_width_coded,
+ frame_height_coded);
+ u32 te_lb_size = size_te_lb(is_ten_bit, num_vpp_pipes_enc, width_in_lcus,
+ frame_height_coded, frame_width_coded);
+ u32 fe_lb_size = size_fe_lb(is_ten_bit, standard, num_vpp_pipes_enc, frame_height_coded,
+ frame_width_coded);
+ u32 md_lb_size = size_md_lb(standard, frame_width_coded, frame_height_coded,
+ num_vpp_pipes_enc);
+ u32 dma_opb_lb_size = size_dma_opb_lb(num_vpp_pipes_enc, frame_width_coded,
+ frame_height_coded);
+ u32 dse_lb_size = ALIGN((256 + (16 * (frame_width_coded >> 4))), DMA_ALIGNMENT);
+ u32 size_vpss_lb_enc = size_vpss_line_buf_vpu33(num_vpp_pipes_enc, frame_width_coded,
+ frame_height_coded);
+ u32 size = se_lb_size + te_lb_size + fe_lb_size + md_lb_size + dma_opb_lb_size +
+ dse_lb_size + size_vpss_lb_enc;
+ size = size << 1;
+
+ return size;
+}
+
+static u32 iris_vpu4x_enc_line_size(struct iris_inst *inst)
+{
+ u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
+ u32 lcu_size = inst->codec == V4L2_PIX_FMT_HEVC ? 32 : 16;
+ struct v4l2_format *f = inst->fmt_dst;
+ u32 height = f->fmt.pix_mp.height;
+ u32 width = f->fmt.pix_mp.width;
+
+ return hfi_vpu4x_buffer_line_enc(width, height, 0, num_vpp_pipes,
+ lcu_size, inst->codec);
+}
+
static int output_min_count(struct iris_inst *inst)
{
int output_min_count = 4;
@@ -1503,6 +1748,50 @@ u32 iris_vpu33_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_typ
return size;
}
+u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type)
+{
+ const struct iris_vpu_buf_type_handle *buf_type_handle_arr = NULL;
+ u32 size = 0, buf_type_handle_size = 0, i;
+
+ static const struct iris_vpu_buf_type_handle dec_internal_buf_type_handle[] = {
+ {BUF_BIN, iris_vpu_dec_bin_size },
+ {BUF_COMV, iris_vpu_dec_comv_size },
+ {BUF_NON_COMV, iris_vpu_dec_non_comv_size },
+ {BUF_LINE, iris_vpu4x_dec_line_size },
+ {BUF_PERSIST, iris_vpu4x_dec_persist_size },
+ {BUF_DPB, iris_vpu_dec_dpb_size },
+ {BUF_SCRATCH_1, iris_vpu_dec_scratch1_size },
+ };
+
+ static const struct iris_vpu_buf_type_handle enc_internal_buf_type_handle[] = {
+ {BUF_BIN, iris_vpu_enc_bin_size },
+ {BUF_COMV, iris_vpu_enc_comv_size },
+ {BUF_NON_COMV, iris_vpu_enc_non_comv_size },
+ {BUF_LINE, iris_vpu4x_enc_line_size },
+ {BUF_ARP, iris_vpu_enc_arp_size },
+ {BUF_VPSS, iris_vpu_enc_vpss_size },
+ {BUF_SCRATCH_1, iris_vpu_enc_scratch1_size },
+ {BUF_SCRATCH_2, iris_vpu_enc_scratch2_size },
+ };
+
+ if (inst->domain == DECODER) {
+ buf_type_handle_size = ARRAY_SIZE(dec_internal_buf_type_handle);
+ buf_type_handle_arr = dec_internal_buf_type_handle;
+ } else if (inst->domain == ENCODER) {
+ buf_type_handle_size = ARRAY_SIZE(enc_internal_buf_type_handle);
+ buf_type_handle_arr = enc_internal_buf_type_handle;
+ }
+
+ for (i = 0; i < buf_type_handle_size; i++) {
+ if (buf_type_handle_arr[i].type == buffer_type) {
+ size = buf_type_handle_arr[i].handle(inst);
+ break;
+ }
+ }
+
+ return size;
+}
+
static u32 internal_buffer_count(struct iris_inst *inst,
enum iris_buffer_type buffer_type)
{
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h
index 04f0b7400a1e4e1d274d690a2761b9e57778e8b7..fb544e8b3bf6b9ce86920a18537fd0a2c21cdc31 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h
+++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h
@@ -46,7 +46,7 @@ struct iris_inst;
#define VP9_NUM_FRAME_INFO_BUF 32
#define VP9_NUM_PROBABILITY_TABLE_BUF (VP9_NUM_FRAME_INFO_BUF + 4)
#define VP9_PROB_TABLE_SIZE (3840)
-#define VP9_FRAME_INFO_BUF_SIZE (6144)
+#define VP9_FRAME_INFO_BUF_SIZE (6400)
#define BUFFER_ALIGNMENT_32_BYTES 32
#define CCE_TILE_OFFSET_SIZE ALIGN(32 * 4 * 4, BUFFER_ALIGNMENT_32_BYTES)
#define MAX_SUPERFRAME_HEADER_LEN (34)
@@ -66,6 +66,8 @@ struct iris_inst;
#define H265_CABAC_HDR_RATIO_HD_TOT 2
#define H265_CABAC_RES_RATIO_HD_TOT 2
#define SIZE_H265D_VPP_CMD_PER_BUF (256)
+#define SIZE_THREE_DIMENSION_USERDATA 768
+#define SIZE_H265D_ARP 9728
#define VPX_DECODER_FRAME_CONCURENCY_LVL (2)
#define VPX_DECODER_FRAME_BIN_HDR_BUDGET 1
@@ -148,6 +150,7 @@ static inline u32 size_h264d_qp(u32 frame_width, u32 frame_height)
u32 iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
u32 iris_vpu33_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
+u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
int iris_vpu_buf_count(struct iris_inst *inst, enum iris_buffer_type buffer_type);
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH 4/8] media: iris: Introduce buffer size calculations for vpu4
2025-09-24 23:14 ` [PATCH 4/8] media: iris: Introduce buffer size calculations for vpu4 Vikash Garodia
@ 2025-09-26 13:00 ` Bryan O'Donoghue
2025-10-02 10:06 ` Vikash Garodia
0 siblings, 1 reply; 54+ messages in thread
From: Bryan O'Donoghue @ 2025-09-26 13:00 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 25/09/2025 00:14, Vikash Garodia wrote:
> +{
> + u32 dma_opb_wr_tlb_y_size = ((frame_width_coded + 15) >> 4) << 7;
> + u32 dma_opb_wr_tlb_uv_size = ((frame_width_coded + 15) >> 4) << 7;
> + u32 dma_opb_wr2_tlb_y_size = ALIGN((2 * 6 * 64 * frame_height_coded / 8), DMA_ALIGNMENT) *
> + num_vpp_pipes_enc;
> + u32 dma_opb_wr2_tlb_uv_size = ALIGN((2 * 6 * 64 * frame_height_coded / 8), DMA_ALIGNMENT) *
> + num_vpp_pipes_enc;
I find these calculations pretty nebulous and not very obvious to look at.
A define of some sort with a comment would definitely help other
programmers reviewing and supporting this code in the future.
(+ 15 >> 4) << 7 - I'm sure it makes sense when you are looking at a
register spec in front of your eyes but if you don't have that detail
its pretty hard to say the values are correct.
/*
* SET_Y_SIZE(x)
* - Add 15 because
* - Shift 4 to lower nibble because
* - Shift the result up 7 because
*/
#define SET_Y_SIZE(x)
---
bod
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH 4/8] media: iris: Introduce buffer size calculations for vpu4
2025-09-26 13:00 ` Bryan O'Donoghue
@ 2025-10-02 10:06 ` Vikash Garodia
0 siblings, 0 replies; 54+ messages in thread
From: Vikash Garodia @ 2025-10-02 10:06 UTC (permalink / raw)
To: Bryan O'Donoghue, Dikshita Agarwal, Abhinav Kumar,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 9/26/2025 6:30 PM, Bryan O'Donoghue wrote:
> On 25/09/2025 00:14, Vikash Garodia wrote:
>> +{
>> + u32 dma_opb_wr_tlb_y_size = ((frame_width_coded + 15) >> 4) << 7;
>> + u32 dma_opb_wr_tlb_uv_size = ((frame_width_coded + 15) >> 4) << 7;
>> + u32 dma_opb_wr2_tlb_y_size = ALIGN((2 * 6 * 64 * frame_height_coded / 8),
>> DMA_ALIGNMENT) *
>> + num_vpp_pipes_enc;
>> + u32 dma_opb_wr2_tlb_uv_size = ALIGN((2 * 6 * 64 * frame_height_coded /
>> 8), DMA_ALIGNMENT) *
>> + num_vpp_pipes_enc;
>
> I find these calculations pretty nebulous and not very obvious to look at.
>
> A define of some sort with a comment would definitely help other programmers
> reviewing and supporting this code in the future.
>
> (+ 15 >> 4) << 7 - I'm sure it makes sense when you are looking at a register
> spec in front of your eyes but if you don't have that detail its pretty hard to
> say the values are correct.
>
> /*
> * SET_Y_SIZE(x)
> * - Add 15 because
> * - Shift 4 to lower nibble because
> * - Shift the result up 7 because
> */
> #define SET_Y_SIZE(x)
>
Sure, i would trying to gather and explain as much info feasible from my side.
At the same time, these calculation for hardware internal buffers have been
there for vpu2/3x, and is being extended for vpu4 in a similar way.
Regards,
Vikash
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH 5/8] media: iris: Move vpu register defines to common header file
2025-09-24 23:14 [PATCH 0/8] media: iris: add support for video codecs on Qcom kaanapali platform Vikash Garodia
` (3 preceding siblings ...)
2025-09-24 23:14 ` [PATCH 4/8] media: iris: Introduce buffer size calculations for vpu4 Vikash Garodia
@ 2025-09-24 23:14 ` Vikash Garodia
2025-09-25 9:10 ` Konrad Dybcio
2025-10-16 13:47 ` Dmitry Baryshkov
2025-09-24 23:14 ` [PATCH 6/8] media: iris: Move vpu35 specific api to common to use for vpu4 Vikash Garodia
` (2 subsequent siblings)
7 siblings, 2 replies; 54+ messages in thread
From: Vikash Garodia @ 2025-09-24 23:14 UTC (permalink / raw)
To: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy, Vikash Garodia
Some of vpu4 register defines are common with vpu3x. Move those into the
common register defines header. This is done to reuse the defines for
vpu4 in subsequent patch which enables the power sequence for vpu4.
Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_vpu3x.c | 36 ----------------------
drivers/media/platform/qcom/iris/iris_vpu_common.c | 23 --------------
.../platform/qcom/iris/iris_vpu_register_defines.h | 29 +++++++++++++++++
3 files changed, 29 insertions(+), 59 deletions(-)
diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c
index 339776a0b4672e246848c3a6a260eb83c7da6a60..0ac6373c33b7ced75ac94ac86a1a8fc303f28b5d 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu3x.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c
@@ -11,48 +11,12 @@
#include "iris_vpu_common.h"
#include "iris_vpu_register_defines.h"
-#define WRAPPER_TZ_BASE_OFFS 0x000C0000
-#define AON_BASE_OFFS 0x000E0000
-#define AON_MVP_NOC_RESET 0x0001F000
-
-#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
-#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
-#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
-#define REQ_POWER_DOWN_PREP BIT(0)
-#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
-#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */
-#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */
-#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */
-#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88)
#define CORE_CLK_RUN 0x0
/* VPU v3.5 */
#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78)
-#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
-#define CTL_AXI_CLK_HALT BIT(0)
-#define CTL_CLK_HALT BIT(1)
-
-#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
-#define RESET_HIGH BIT(0)
-
-#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160)
-#define CORE_BRIDGE_SW_RESET BIT(0)
-#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1)
-
-#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
-#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
-#define MSK_CORE_POWER_ON BIT(1)
-
-#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000)
#define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1))
-#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004)
-
-#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70)
-
-#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
-#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
-
#define AON_WRAPPER_MVP_NOC_CORE_SW_RESET (AON_BASE_OFFS + 0x18)
#define SW_RESET BIT(0)
#define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL (AON_BASE_OFFS + 0x20)
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
index bbd999a41236dca5cf5700e452a6fed69f4fc922..a7b1fb8173e02d22e6f2af4ea170738c6408f65b 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
@@ -11,9 +11,6 @@
#include "iris_vpu_common.h"
#include "iris_vpu_register_defines.h"
-#define WRAPPER_TZ_BASE_OFFS 0x000C0000
-#define AON_BASE_OFFS 0x000E0000
-
#define CPU_IC_BASE_OFFS (CPU_BASE_OFFS)
#define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE_OFFS + 0x1C)
@@ -38,10 +35,6 @@
#define CPU_CS_H2XSOFTINTEN (CPU_CS_BASE_OFFS + 0x148)
#define HOST2XTENSA_INTR_ENABLE BIT(0)
-#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
-#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
-#define MSK_CORE_POWER_ON BIT(1)
-
#define CPU_IC_SOFTINT (CPU_IC_BASE_OFFS + 0x150)
#define CPU_IC_SOFTINT_H2A_SHFT 0x0
@@ -53,23 +46,7 @@
#define WRAPPER_INTR_MASK_A2HWD_BMSK BIT(3)
#define WRAPPER_INTR_MASK_A2HCPU_BMSK BIT(2)
-#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
-#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
-#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
-#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
-
#define WRAPPER_TZ_CPU_STATUS (WRAPPER_TZ_BASE_OFFS + 0x10)
-#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
-#define CTL_AXI_CLK_HALT BIT(0)
-#define CTL_CLK_HALT BIT(1)
-
-#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
-#define RESET_HIGH BIT(0)
-
-#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
-#define REQ_POWER_DOWN_PREP BIT(0)
-
-#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
static void iris_vpu_interrupt_init(struct iris_core *core)
{
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
index fe8a39e5e5a3fc68dc3a706ffdba07a5558163cf..6474f561c8dc29d1975bb44792595d86f16b6cff 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
+++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
@@ -9,9 +9,38 @@
#define VCODEC_BASE_OFFS 0x00000000
#define CPU_BASE_OFFS 0x000A0000
#define WRAPPER_BASE_OFFS 0x000B0000
+#define AON_BASE_OFFS 0x000E0000
+#define WRAPPER_TZ_BASE_OFFS 0x000C0000
+#define AON_MVP_NOC_RESET 0x0001F000
#define CPU_CS_BASE_OFFS (CPU_BASE_OFFS)
#define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS + 0x80)
+#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88)
+#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
+#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
+#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
+#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
+#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
+#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
+#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160)
+#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
+#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000)
+#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004)
+#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70)
+#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
+#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
+
+#define CORE_BRIDGE_SW_RESET BIT(0)
+#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1)
+#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
+#define MSK_CORE_POWER_ON BIT(1)
+#define CTL_AXI_CLK_HALT BIT(0)
+#define CTL_CLK_HALT BIT(1)
+#define REQ_POWER_DOWN_PREP BIT(0)
+#define RESET_HIGH BIT(0)
+#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */
+#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */
+#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH 5/8] media: iris: Move vpu register defines to common header file
2025-09-24 23:14 ` [PATCH 5/8] media: iris: Move vpu register defines to common header file Vikash Garodia
@ 2025-09-25 9:10 ` Konrad Dybcio
2025-09-29 5:44 ` Vishnu Reddy
2025-10-02 9:35 ` Vikash Garodia
2025-10-16 13:47 ` Dmitry Baryshkov
1 sibling, 2 replies; 54+ messages in thread
From: Konrad Dybcio @ 2025-09-25 9:10 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 9/25/25 1:14 AM, Vikash Garodia wrote:
> Some of vpu4 register defines are common with vpu3x. Move those into the
> common register defines header. This is done to reuse the defines for
> vpu4 in subsequent patch which enables the power sequence for vpu4.
>
> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/iris/iris_vpu3x.c | 36 ----------------------
> drivers/media/platform/qcom/iris/iris_vpu_common.c | 23 --------------
> .../platform/qcom/iris/iris_vpu_register_defines.h | 29 +++++++++++++++++
This is a slippery slope. I think it's better if you explicitly say
the header file contains the register map of VPU3 instead, as let's say
VPU5 may add a random register in the middle (pushing some existing ones
+0x4 down). Such changes are annoying to debug, and we've unfortunately
been there on Adreno..
Because you're using this for a single common function that is both acting
upon the same registers and performing the same operations on them across
VPU35 and VPU4, it's okay to de-static-ize the function from iris_vpu3.c and
refer to it from vpu4 ops, keeping the register map private to the former
file which I think will end up less error-prone for the future.
Konrad
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH 5/8] media: iris: Move vpu register defines to common header file
2025-09-25 9:10 ` Konrad Dybcio
@ 2025-09-29 5:44 ` Vishnu Reddy
2025-10-07 13:23 ` Konrad Dybcio
2025-10-02 9:35 ` Vikash Garodia
1 sibling, 1 reply; 54+ messages in thread
From: Vishnu Reddy @ 2025-09-29 5:44 UTC (permalink / raw)
To: Konrad Dybcio, Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel
On 9/25/2025 2:40 PM, Konrad Dybcio wrote:
> On 9/25/25 1:14 AM, Vikash Garodia wrote:
>> Some of vpu4 register defines are common with vpu3x. Move those into the
>> common register defines header. This is done to reuse the defines for
>> vpu4 in subsequent patch which enables the power sequence for vpu4.
>>
>> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
>> ---
>> drivers/media/platform/qcom/iris/iris_vpu3x.c | 36 ----------------------
>> drivers/media/platform/qcom/iris/iris_vpu_common.c | 23 --------------
>> .../platform/qcom/iris/iris_vpu_register_defines.h | 29 +++++++++++++++++
>
> This is a slippery slope. I think it's better if you explicitly say
> the header file contains the register map of VPU3 instead, as let's say
> VPU5 may add a random register in the middle (pushing some existing ones
> +0x4 down). Such changes are annoying to debug, and we've unfortunately
> been there on Adreno..
>
> Because you're using this for a single common function that is both acting
> upon the same registers and performing the same operations on them across
> VPU35 and VPU4, it's okay to de-static-ize the function from iris_vpu3.c and
> refer to it from vpu4 ops, keeping the register map private to the former
> file which I think will end up less error-prone for the future.
>
> Konrad
Just to confirm
1. You’re saying it’s better to keep the register definitions for each
VPU generation in their own source files, instead of keeping them all
in a shared header. Is that right?
2. The vpu functions (power on controller, power off controller and
etc.) which are common for vpu3x and vpu4x are moved to
iris_vpu_common.c and de-static-ize to use for both vpu3x and vpu4x.
(This code changes are there in [PATCH 6/8] media: iris: Move vpu35
specific api to common to use for vpu4)
Will this 2nd point is fine or Do I need the keep the functions also
in the platform specific file and reuse for vpu4x by de-static-ize the
function in iris_vpu3x.c?
Thanks and regards,
Vishnu Reddy
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH 5/8] media: iris: Move vpu register defines to common header file
2025-09-29 5:44 ` Vishnu Reddy
@ 2025-10-07 13:23 ` Konrad Dybcio
0 siblings, 0 replies; 54+ messages in thread
From: Konrad Dybcio @ 2025-10-07 13:23 UTC (permalink / raw)
To: Vishnu Reddy, Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel
On 9/29/25 7:44 AM, Vishnu Reddy wrote:
>
>
> On 9/25/2025 2:40 PM, Konrad Dybcio wrote:
>> On 9/25/25 1:14 AM, Vikash Garodia wrote:
>>> Some of vpu4 register defines are common with vpu3x. Move those into the
>>> common register defines header. This is done to reuse the defines for
>>> vpu4 in subsequent patch which enables the power sequence for vpu4.
>>>
>>> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>>> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>>> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
>>> ---
>>> drivers/media/platform/qcom/iris/iris_vpu3x.c | 36 ----------------------
>>> drivers/media/platform/qcom/iris/iris_vpu_common.c | 23 --------------
>>> .../platform/qcom/iris/iris_vpu_register_defines.h | 29 +++++++++++++++++
>>
>> This is a slippery slope. I think it's better if you explicitly say
>> the header file contains the register map of VPU3 instead, as let's say
>> VPU5 may add a random register in the middle (pushing some existing ones
>> +0x4 down). Such changes are annoying to debug, and we've unfortunately
>> been there on Adreno..
>>
>> Because you're using this for a single common function that is both acting
>> upon the same registers and performing the same operations on them across
>> VPU35 and VPU4, it's okay to de-static-ize the function from iris_vpu3.c and
>> refer to it from vpu4 ops, keeping the register map private to the former
>> file which I think will end up less error-prone for the future.
>>
>> Konrad
>
> Just to confirm
> 1. You’re saying it’s better to keep the register definitions for each
> VPU generation in their own source files, instead of keeping them all
> in a shared header. Is that right?
>
> 2. The vpu functions (power on controller, power off controller and
> etc.) which are common for vpu3x and vpu4x are moved to
> iris_vpu_common.c and de-static-ize to use for both vpu3x and vpu4x.
> (This code changes are there in [PATCH 6/8] media: iris: Move vpu35
> specific api to common to use for vpu4)
>
> Will this 2nd point is fine or Do I need the keep the functions also
> in the platform specific file and reuse for vpu4x by de-static-ize the
> function in iris_vpu3x.c?
I think we can drop this since Vikash said it's not going to change
much for the forseeable future
Konrad
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH 5/8] media: iris: Move vpu register defines to common header file
2025-09-25 9:10 ` Konrad Dybcio
2025-09-29 5:44 ` Vishnu Reddy
@ 2025-10-02 9:35 ` Vikash Garodia
2025-10-07 13:22 ` Konrad Dybcio
1 sibling, 1 reply; 54+ messages in thread
From: Vikash Garodia @ 2025-10-02 9:35 UTC (permalink / raw)
To: Konrad Dybcio, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 9/25/2025 2:40 PM, Konrad Dybcio wrote:
> On 9/25/25 1:14 AM, Vikash Garodia wrote:
>> Some of vpu4 register defines are common with vpu3x. Move those into the
>> common register defines header. This is done to reuse the defines for
>> vpu4 in subsequent patch which enables the power sequence for vpu4.
>>
>> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
>> ---
>> drivers/media/platform/qcom/iris/iris_vpu3x.c | 36 ----------------------
>> drivers/media/platform/qcom/iris/iris_vpu_common.c | 23 --------------
>> .../platform/qcom/iris/iris_vpu_register_defines.h | 29 +++++++++++++++++
>
> This is a slippery slope. I think it's better if you explicitly say
> the header file contains the register map of VPU3 instead, as let's say
> VPU5 may add a random register in the middle (pushing some existing ones
> +0x4 down). Such changes are annoying to debug, and we've unfortunately
> been there on Adreno..
>
> Because you're using this for a single common function that is both acting
> upon the same registers and performing the same operations on them across
> VPU35 and VPU4, it's okay to de-static-ize the function from iris_vpu3.c and
> refer to it from vpu4 ops, keeping the register map private to the former
> file which I think will end up less error-prone for the future.
Appreciate your thoughts on this and trying to bring the design issues faced in
adreno. I peeked into vpu5 register map, and it follows the offsets from vpu4
and should reuse them from "iris_vpu_register_defines.h". IMO, we should be good
in reusing them for vpu4 and atleast for next generation.
Regards,
Vikash
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH 5/8] media: iris: Move vpu register defines to common header file
2025-10-02 9:35 ` Vikash Garodia
@ 2025-10-07 13:22 ` Konrad Dybcio
0 siblings, 0 replies; 54+ messages in thread
From: Konrad Dybcio @ 2025-10-07 13:22 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 10/2/25 11:35 AM, Vikash Garodia wrote:
>
> On 9/25/2025 2:40 PM, Konrad Dybcio wrote:
>> On 9/25/25 1:14 AM, Vikash Garodia wrote:
>>> Some of vpu4 register defines are common with vpu3x. Move those into the
>>> common register defines header. This is done to reuse the defines for
>>> vpu4 in subsequent patch which enables the power sequence for vpu4.
>>>
>>> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>>> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>>> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
>>> ---
>>> drivers/media/platform/qcom/iris/iris_vpu3x.c | 36 ----------------------
>>> drivers/media/platform/qcom/iris/iris_vpu_common.c | 23 --------------
>>> .../platform/qcom/iris/iris_vpu_register_defines.h | 29 +++++++++++++++++
>>
>> This is a slippery slope. I think it's better if you explicitly say
>> the header file contains the register map of VPU3 instead, as let's say
>> VPU5 may add a random register in the middle (pushing some existing ones
>> +0x4 down). Such changes are annoying to debug, and we've unfortunately
>> been there on Adreno..
>>
>> Because you're using this for a single common function that is both acting
>> upon the same registers and performing the same operations on them across
>> VPU35 and VPU4, it's okay to de-static-ize the function from iris_vpu3.c and
>> refer to it from vpu4 ops, keeping the register map private to the former
>> file which I think will end up less error-prone for the future.
>
> Appreciate your thoughts on this and trying to bring the design issues faced in
> adreno. I peeked into vpu5 register map, and it follows the offsets from vpu4
> and should reuse them from "iris_vpu_register_defines.h". IMO, we should be good
> in reusing them for vpu4 and atleast for next generation.
If you're confident in that, go ahead with the current approach
Konrad
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH 5/8] media: iris: Move vpu register defines to common header file
2025-09-24 23:14 ` [PATCH 5/8] media: iris: Move vpu register defines to common header file Vikash Garodia
2025-09-25 9:10 ` Konrad Dybcio
@ 2025-10-16 13:47 ` Dmitry Baryshkov
2025-10-16 18:37 ` Vikash Garodia
1 sibling, 1 reply; 54+ messages in thread
From: Dmitry Baryshkov @ 2025-10-16 13:47 UTC (permalink / raw)
To: Vikash Garodia
Cc: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, linux-arm-msm, linux-media,
devicetree, linux-kernel, Vishnu Reddy
On Thu, Sep 25, 2025 at 04:44:43AM +0530, Vikash Garodia wrote:
> Some of vpu4 register defines are common with vpu3x. Move those into the
> common register defines header. This is done to reuse the defines for
> vpu4 in subsequent patch which enables the power sequence for vpu4.
>
> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/iris/iris_vpu3x.c | 36 ----------------------
> drivers/media/platform/qcom/iris/iris_vpu_common.c | 23 --------------
> .../platform/qcom/iris/iris_vpu_register_defines.h | 29 +++++++++++++++++
> 3 files changed, 29 insertions(+), 59 deletions(-)
>
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c
> index 339776a0b4672e246848c3a6a260eb83c7da6a60..0ac6373c33b7ced75ac94ac86a1a8fc303f28b5d 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c
> @@ -11,48 +11,12 @@
> #include "iris_vpu_common.h"
> #include "iris_vpu_register_defines.h"
>
> -#define WRAPPER_TZ_BASE_OFFS 0x000C0000
> -#define AON_BASE_OFFS 0x000E0000
> -#define AON_MVP_NOC_RESET 0x0001F000
> -
> -#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
> -#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
> -#define REQ_POWER_DOWN_PREP BIT(0)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
> -#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */
> -#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */
> -#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */
> -#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88)
> #define CORE_CLK_RUN 0x0
> /* VPU v3.5 */
> #define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78)
>
> -#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
> -#define CTL_AXI_CLK_HALT BIT(0)
> -#define CTL_CLK_HALT BIT(1)
> -
> -#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
> -#define RESET_HIGH BIT(0)
> -
> -#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160)
> -#define CORE_BRIDGE_SW_RESET BIT(0)
> -#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1)
> -
> -#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
> -#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
> -#define MSK_CORE_POWER_ON BIT(1)
> -
> -#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000)
> #define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1))
>
> -#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004)
> -
> -#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70)
> -
> -#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
> -#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
> -
> #define AON_WRAPPER_MVP_NOC_CORE_SW_RESET (AON_BASE_OFFS + 0x18)
> #define SW_RESET BIT(0)
> #define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL (AON_BASE_OFFS + 0x20)
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> index bbd999a41236dca5cf5700e452a6fed69f4fc922..a7b1fb8173e02d22e6f2af4ea170738c6408f65b 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> @@ -11,9 +11,6 @@
> #include "iris_vpu_common.h"
> #include "iris_vpu_register_defines.h"
>
> -#define WRAPPER_TZ_BASE_OFFS 0x000C0000
> -#define AON_BASE_OFFS 0x000E0000
> -
> #define CPU_IC_BASE_OFFS (CPU_BASE_OFFS)
>
> #define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE_OFFS + 0x1C)
> @@ -38,10 +35,6 @@
> #define CPU_CS_H2XSOFTINTEN (CPU_CS_BASE_OFFS + 0x148)
> #define HOST2XTENSA_INTR_ENABLE BIT(0)
>
> -#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
> -#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
> -#define MSK_CORE_POWER_ON BIT(1)
> -
> #define CPU_IC_SOFTINT (CPU_IC_BASE_OFFS + 0x150)
> #define CPU_IC_SOFTINT_H2A_SHFT 0x0
>
> @@ -53,23 +46,7 @@
> #define WRAPPER_INTR_MASK_A2HWD_BMSK BIT(3)
> #define WRAPPER_INTR_MASK_A2HCPU_BMSK BIT(2)
>
> -#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
> -#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
> -
> #define WRAPPER_TZ_CPU_STATUS (WRAPPER_TZ_BASE_OFFS + 0x10)
> -#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
> -#define CTL_AXI_CLK_HALT BIT(0)
> -#define CTL_CLK_HALT BIT(1)
> -
> -#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
> -#define RESET_HIGH BIT(0)
> -
> -#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
> -#define REQ_POWER_DOWN_PREP BIT(0)
> -
> -#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
>
> static void iris_vpu_interrupt_init(struct iris_core *core)
> {
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> index fe8a39e5e5a3fc68dc3a706ffdba07a5558163cf..6474f561c8dc29d1975bb44792595d86f16b6cff 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> @@ -9,9 +9,38 @@
> #define VCODEC_BASE_OFFS 0x00000000
> #define CPU_BASE_OFFS 0x000A0000
> #define WRAPPER_BASE_OFFS 0x000B0000
> +#define AON_BASE_OFFS 0x000E0000
> +#define WRAPPER_TZ_BASE_OFFS 0x000C0000
> +#define AON_MVP_NOC_RESET 0x0001F000
>
> #define CPU_CS_BASE_OFFS (CPU_BASE_OFFS)
>
> #define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS + 0x80)
> +#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88)
> +#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
> +#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
> +#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
> +#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
> +#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
> +#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
> +#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160)
> +#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
> +#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000)
> +#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004)
> +#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70)
> +#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
> +#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
Registers here got totally unsorted (they were in the original source
file). Seeing this makes me sad.
> +
> +#define CORE_BRIDGE_SW_RESET BIT(0)
> +#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1)
> +#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
> +#define MSK_CORE_POWER_ON BIT(1)
> +#define CTL_AXI_CLK_HALT BIT(0)
> +#define CTL_CLK_HALT BIT(1)
> +#define REQ_POWER_DOWN_PREP BIT(0)
> +#define RESET_HIGH BIT(0)
> +#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */
> +#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */
> +#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */
Ugh. This mixed all the bits, loosing connection between the register
and the corresponding bits. I'm going to pick up this patch into the
sc7280 series and I will improve it there, keeping the link between
registers and bit fields.
>
> #endif
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH 5/8] media: iris: Move vpu register defines to common header file
2025-10-16 13:47 ` Dmitry Baryshkov
@ 2025-10-16 18:37 ` Vikash Garodia
2025-10-16 18:58 ` Dmitry Baryshkov
0 siblings, 1 reply; 54+ messages in thread
From: Vikash Garodia @ 2025-10-16 18:37 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, linux-arm-msm, linux-media,
devicetree, linux-kernel, Vishnu Reddy
On 10/16/2025 7:17 PM, Dmitry Baryshkov wrote:
>> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
>> index fe8a39e5e5a3fc68dc3a706ffdba07a5558163cf..6474f561c8dc29d1975bb44792595d86f16b6cff 100644
>> --- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
>> +++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
>> @@ -9,9 +9,38 @@
>> #define VCODEC_BASE_OFFS 0x00000000
>> #define CPU_BASE_OFFS 0x000A0000
>> #define WRAPPER_BASE_OFFS 0x000B0000
>> +#define AON_BASE_OFFS 0x000E0000
>> +#define WRAPPER_TZ_BASE_OFFS 0x000C0000
>> +#define AON_MVP_NOC_RESET 0x0001F000
>>
>> #define CPU_CS_BASE_OFFS (CPU_BASE_OFFS)
>>
>> #define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS + 0x80)
>> +#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88)
>> +#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
>> +#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
>> +#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
>> +#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
>> +#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
>> +#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
>> +#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160)
>> +#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
>> +#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000)
>> +#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004)
>> +#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70)
>> +#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
>> +#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
> Registers here got totally unsorted (they were in the original source
> file). Seeing this makes me sad.
>
Sure, i will be improving this part in v2.
>> +
>> +#define CORE_BRIDGE_SW_RESET BIT(0)
>> +#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1)
>> +#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
>> +#define MSK_CORE_POWER_ON BIT(1)
>> +#define CTL_AXI_CLK_HALT BIT(0)
>> +#define CTL_CLK_HALT BIT(1)
>> +#define REQ_POWER_DOWN_PREP BIT(0)
>> +#define RESET_HIGH BIT(0)
>> +#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */
>> +#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */
>> +#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */
> Ugh. This mixed all the bits, loosing connection between the register
> and the corresponding bits. I'm going to pick up this patch into the
> sc7280 series and I will improve it there, keeping the link between
> registers and bit fields.
>
Ok, not updating this part in the next revision of my series. Do you mean
something like
#define CORE_BRIDGE_SW_RESET_BIT0 BIT(0)
#define CORE_BRIDGE_HW_RESET_DISABLE_BIT1 BIT(1)
Regards,
Vikash
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH 5/8] media: iris: Move vpu register defines to common header file
2025-10-16 18:37 ` Vikash Garodia
@ 2025-10-16 18:58 ` Dmitry Baryshkov
0 siblings, 0 replies; 54+ messages in thread
From: Dmitry Baryshkov @ 2025-10-16 18:58 UTC (permalink / raw)
To: Vikash Garodia
Cc: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, linux-arm-msm, linux-media,
devicetree, linux-kernel, Vishnu Reddy
On Thu, 16 Oct 2025 at 21:37, Vikash Garodia
<vikash.garodia@oss.qualcomm.com> wrote:
>
>
> On 10/16/2025 7:17 PM, Dmitry Baryshkov wrote:
> >> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> >> index fe8a39e5e5a3fc68dc3a706ffdba07a5558163cf..6474f561c8dc29d1975bb44792595d86f16b6cff 100644
> >> --- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> >> +++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> >> @@ -9,9 +9,38 @@
> >> #define VCODEC_BASE_OFFS 0x00000000
> >> #define CPU_BASE_OFFS 0x000A0000
> >> #define WRAPPER_BASE_OFFS 0x000B0000
> >> +#define AON_BASE_OFFS 0x000E0000
> >> +#define WRAPPER_TZ_BASE_OFFS 0x000C0000
> >> +#define AON_MVP_NOC_RESET 0x0001F000
> >>
> >> #define CPU_CS_BASE_OFFS (CPU_BASE_OFFS)
> >>
> >> #define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS + 0x80)
> >> +#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88)
> >> +#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
> >> +#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
> >> +#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
> >> +#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
> >> +#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
> >> +#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
> >> +#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160)
> >> +#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
> >> +#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000)
> >> +#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004)
> >> +#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70)
> >> +#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
> >> +#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
> > Registers here got totally unsorted (they were in the original source
> > file). Seeing this makes me sad.
> >
>
> Sure, i will be improving this part in v2.
>
> >> +
> >> +#define CORE_BRIDGE_SW_RESET BIT(0)
> >> +#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1)
> >> +#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
> >> +#define MSK_CORE_POWER_ON BIT(1)
> >> +#define CTL_AXI_CLK_HALT BIT(0)
> >> +#define CTL_CLK_HALT BIT(1)
> >> +#define REQ_POWER_DOWN_PREP BIT(0)
> >> +#define RESET_HIGH BIT(0)
> >> +#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */
> >> +#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */
> >> +#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */
> > Ugh. This mixed all the bits, loosing connection between the register
> > and the corresponding bits. I'm going to pick up this patch into the
> > sc7280 series and I will improve it there, keeping the link between
> > registers and bit fields.
> >
>
> Ok, not updating this part in the next revision of my series. Do you mean
> something like
>
> #define CORE_BRIDGE_SW_RESET_BIT0 BIT(0)
> #define CORE_BRIDGE_HW_RESET_DISABLE_BIT1 BIT(1)
No, just keeping those BIT() definition next to the corresponding
register #define.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH 6/8] media: iris: Move vpu35 specific api to common to use for vpu4
2025-09-24 23:14 [PATCH 0/8] media: iris: add support for video codecs on Qcom kaanapali platform Vikash Garodia
` (4 preceding siblings ...)
2025-09-24 23:14 ` [PATCH 5/8] media: iris: Move vpu register defines to common header file Vikash Garodia
@ 2025-09-24 23:14 ` Vikash Garodia
2025-09-24 23:14 ` [PATCH 7/8] media: iris: Introduce vpu ops for vpu4 with necessary hooks Vikash Garodia
2025-09-24 23:14 ` [PATCH 8/8] media: iris: Add platform data for kaanapali Vikash Garodia
7 siblings, 0 replies; 54+ messages in thread
From: Vikash Garodia @ 2025-09-24 23:14 UTC (permalink / raw)
To: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy, Vikash Garodia
Some of the sequence and calculations for vpu4 is identical to vpu35,
namely power sequence for vpu controller and the clock frequency
calculation. Move those to common file that can be shared for both vpu35
and vpu4. This patch prepares for power sequence for vpu4 which is added
in subsequent patch.
Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_vpu3x.c | 159 +--------------------
drivers/media/platform/qcom/iris/iris_vpu_common.c | 143 ++++++++++++++++++
drivers/media/platform/qcom/iris/iris_vpu_common.h | 4 +
3 files changed, 153 insertions(+), 153 deletions(-)
diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c
index 0ac6373c33b7ced75ac94ac86a1a8fc303f28b5d..3abfb74dbb10974c8fe3cedaf67e8b4fca421015 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu3x.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c
@@ -12,8 +12,6 @@
#include "iris_vpu_register_defines.h"
#define CORE_CLK_RUN 0x0
-/* VPU v3.5 */
-#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78)
#define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1))
@@ -22,8 +20,6 @@
#define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL (AON_BASE_OFFS + 0x20)
#define NOC_HALT BIT(0)
#define AON_WRAPPER_SPARE (AON_BASE_OFFS + 0x28)
-#define AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL (AON_BASE_OFFS + 0x2C)
-#define AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS (AON_BASE_OFFS + 0x30)
static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core)
{
@@ -268,155 +264,12 @@ static void iris_vpu35_power_off_hw(struct iris_core *core)
iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
}
-static int iris_vpu35_power_off_controller(struct iris_core *core)
-{
- u32 clk_rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size;
- unsigned int count = 0;
- u32 val = 0;
- bool handshake_done, handshake_busy;
- int ret;
-
- writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CPU_CS_X2RPMH);
-
- writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);
-
- ret = readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STATUS,
- val, val & BIT(0), 200, 2000);
- if (ret)
- goto disable_power;
-
- writel(0, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);
-
- /* Retry up to 1000 times as recommended by hardware documentation */
- do {
- /* set MNoC to low power */
- writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL);
-
- udelay(15);
-
- val = readl(core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS);
-
- handshake_done = val & NOC_LPI_STATUS_DONE;
- handshake_busy = val & (NOC_LPI_STATUS_DENY | NOC_LPI_STATUS_ACTIVE);
-
- if (handshake_done || !handshake_busy)
- break;
-
- writel(0, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL);
-
- udelay(15);
-
- } while (++count < 1000);
-
- if (!handshake_done && handshake_busy)
- dev_err(core->dev, "LPI handshake timeout\n");
-
- ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS,
- val, val & BIT(0), 200, 2000);
- if (ret)
- goto disable_power;
-
- writel(0, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL);
-
- writel(0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL);
-
- ret = readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STATUS,
- val, val == 0, 200, 2000);
- if (ret)
- goto disable_power;
-
-disable_power:
- iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
- iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK);
- iris_disable_unprepare_clock(core, IRIS_AXI1_CLK);
-
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
-
- reset_control_bulk_reset(clk_rst_tbl_size, core->resets);
-
- return 0;
-}
-
-static int iris_vpu35_power_on_controller(struct iris_core *core)
-{
- int ret;
-
- ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
- if (ret)
- return ret;
-
- ret = iris_prepare_enable_clock(core, IRIS_AXI1_CLK);
- if (ret)
- goto err_disable_power;
-
- ret = iris_prepare_enable_clock(core, IRIS_CTRL_FREERUN_CLK);
- if (ret)
- goto err_disable_axi1_clk;
-
- ret = iris_prepare_enable_clock(core, IRIS_CTRL_CLK);
- if (ret)
- goto err_disable_ctrl_free_clk;
-
- return 0;
-
-err_disable_ctrl_free_clk:
- iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK);
-err_disable_axi1_clk:
- iris_disable_unprepare_clock(core, IRIS_AXI1_CLK);
-err_disable_power:
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
-
- return ret;
-}
-
-static void iris_vpu35_program_bootup_registers(struct iris_core *core)
-{
- writel(0x1, core->reg_base + WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0);
-}
-
-static u64 iris_vpu3x_calculate_frequency(struct iris_inst *inst, size_t data_size)
-{
- struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
- struct v4l2_format *inp_f = inst->fmt_src;
- u32 height, width, mbs_per_second, mbpf;
- u64 fw_cycles, fw_vpp_cycles;
- u64 vsp_cycles, vpp_cycles;
- u32 fps = DEFAULT_FPS;
-
- width = max(inp_f->fmt.pix_mp.width, inst->crop.width);
- height = max(inp_f->fmt.pix_mp.height, inst->crop.height);
-
- mbpf = NUM_MBS_PER_FRAME(height, width);
- mbs_per_second = mbpf * fps;
-
- fw_cycles = fps * caps->mb_cycles_fw;
- fw_vpp_cycles = fps * caps->mb_cycles_fw_vpp;
-
- vpp_cycles = mult_frac(mbs_per_second, caps->mb_cycles_vpp, (u32)inst->fw_caps[PIPE].value);
- /* 21 / 20 is minimum overhead factor */
- vpp_cycles += max(div_u64(vpp_cycles, 20), fw_vpp_cycles);
-
- /* 1.059 is multi-pipe overhead */
- if (inst->fw_caps[PIPE].value > 1)
- vpp_cycles += div_u64(vpp_cycles * 59, 1000);
-
- vsp_cycles = fps * data_size * 8;
- vsp_cycles = div_u64(vsp_cycles, 2);
- /* VSP FW overhead 1.05 */
- vsp_cycles = div_u64(vsp_cycles * 21, 20);
-
- if (inst->fw_caps[STAGE].value == STAGE_1)
- vsp_cycles = vsp_cycles * 3;
-
- return max3(vpp_cycles, vsp_cycles, fw_cycles);
-}
-
const struct vpu_ops iris_vpu3_ops = {
.power_off_hw = iris_vpu3_power_off_hardware,
.power_on_hw = iris_vpu_power_on_hw,
.power_off_controller = iris_vpu_power_off_controller,
.power_on_controller = iris_vpu_power_on_controller,
- .calc_freq = iris_vpu3x_calculate_frequency,
+ .calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
};
const struct vpu_ops iris_vpu33_ops = {
@@ -424,14 +277,14 @@ const struct vpu_ops iris_vpu33_ops = {
.power_on_hw = iris_vpu_power_on_hw,
.power_off_controller = iris_vpu33_power_off_controller,
.power_on_controller = iris_vpu_power_on_controller,
- .calc_freq = iris_vpu3x_calculate_frequency,
+ .calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
};
const struct vpu_ops iris_vpu35_ops = {
.power_off_hw = iris_vpu35_power_off_hw,
.power_on_hw = iris_vpu35_power_on_hw,
- .power_off_controller = iris_vpu35_power_off_controller,
- .power_on_controller = iris_vpu35_power_on_controller,
- .program_bootup_registers = iris_vpu35_program_bootup_registers,
- .calc_freq = iris_vpu3x_calculate_frequency,
+ .power_off_controller = iris_vpu35_vpu4x_power_off_controller,
+ .power_on_controller = iris_vpu35_vpu4x_power_on_controller,
+ .program_bootup_registers = iris_vpu35_vpu4x_program_bootup_registers,
+ .calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
};
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
index a7b1fb8173e02d22e6f2af4ea170738c6408f65b..dd0990d143a624d83e241d9970297ce1abe37f74 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
@@ -8,6 +8,7 @@
#include <linux/reset.h>
#include "iris_core.h"
+#include "iris_instance.h"
#include "iris_vpu_common.h"
#include "iris_vpu_register_defines.h"
@@ -48,6 +49,10 @@
#define WRAPPER_TZ_CPU_STATUS (WRAPPER_TZ_BASE_OFFS + 0x10)
+#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78)
+#define AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL (AON_BASE_OFFS + 0x2C)
+#define AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS (AON_BASE_OFFS + 0x30)
+
static void iris_vpu_interrupt_init(struct iris_core *core)
{
u32 mask_val;
@@ -309,6 +314,144 @@ int iris_vpu_power_on_hw(struct iris_core *core)
return ret;
}
+int iris_vpu35_vpu4x_power_off_controller(struct iris_core *core)
+{
+ u32 clk_rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size;
+ bool handshake_done, handshake_busy;
+ u32 count = 0, val = 0;
+ int ret;
+
+ writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CPU_CS_X2RPMH);
+
+ writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);
+
+ ret = readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STATUS,
+ val, val & BIT(0), 200, 2000);
+ if (ret)
+ goto disable_power;
+
+ writel(0, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);
+
+ /* Retry up to 1000 times as recommended by hardware documentation */
+ do {
+ /* set MNoC to low power */
+ writel(REQ_POWER_DOWN_PREP, core->reg_base +
+ AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL);
+ usleep_range(10, 20);
+ val = readl(core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS);
+
+ handshake_done = val & NOC_LPI_STATUS_DONE;
+ handshake_busy = val & (NOC_LPI_STATUS_DENY | NOC_LPI_STATUS_ACTIVE);
+
+ if (handshake_done || !handshake_busy)
+ break;
+
+ writel(0, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL);
+ usleep_range(10, 20);
+
+ } while (++count < 1000);
+
+ if (!handshake_done && handshake_busy)
+ dev_err(core->dev, "LPI handshake timeout\n");
+
+ ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS,
+ val, val & BIT(0), 200, 2000);
+ if (ret)
+ goto disable_power;
+
+ writel(0, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL);
+
+ writel(0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL);
+
+ readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STATUS,
+ val, val == 0, 200, 2000);
+
+disable_power:
+ iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
+ iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK);
+ iris_disable_unprepare_clock(core, IRIS_AXI1_CLK);
+
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
+
+ reset_control_bulk_reset(clk_rst_tbl_size, core->resets);
+
+ return 0;
+}
+
+int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core)
+{
+ int ret;
+
+ ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
+ if (ret)
+ return ret;
+
+ ret = iris_prepare_enable_clock(core, IRIS_AXI1_CLK);
+ if (ret)
+ goto err_disable_power;
+
+ ret = iris_prepare_enable_clock(core, IRIS_CTRL_FREERUN_CLK);
+ if (ret)
+ goto err_disable_axi1_clk;
+
+ ret = iris_prepare_enable_clock(core, IRIS_CTRL_CLK);
+ if (ret)
+ goto err_disable_ctrl_free_clk;
+
+ return 0;
+
+err_disable_ctrl_free_clk:
+ iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK);
+err_disable_axi1_clk:
+ iris_disable_unprepare_clock(core, IRIS_AXI1_CLK);
+err_disable_power:
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
+
+ return ret;
+}
+
+void iris_vpu35_vpu4x_program_bootup_registers(struct iris_core *core)
+{
+ writel(0x1, core->reg_base + WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0);
+}
+
+u64 iris_vpu3x_vpu4x_calculate_frequency(struct iris_inst *inst, size_t data_size)
+{
+ struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
+ struct v4l2_format *inp_f = inst->fmt_src;
+ u32 height, width, mbs_per_second, mbpf;
+ u64 fw_cycles, fw_vpp_cycles;
+ u64 vsp_cycles, vpp_cycles;
+ u32 fps = DEFAULT_FPS;
+
+ width = max(inp_f->fmt.pix_mp.width, inst->crop.width);
+ height = max(inp_f->fmt.pix_mp.height, inst->crop.height);
+
+ mbpf = NUM_MBS_PER_FRAME(height, width);
+ mbs_per_second = mbpf * fps;
+
+ fw_cycles = fps * caps->mb_cycles_fw;
+ fw_vpp_cycles = fps * caps->mb_cycles_fw_vpp;
+
+ vpp_cycles = mult_frac(mbs_per_second, caps->mb_cycles_vpp, (u32)inst->fw_caps[PIPE].value);
+ /* 21 / 20 is minimum overhead factor */
+ vpp_cycles += max(div_u64(vpp_cycles, 20), fw_vpp_cycles);
+
+ /* 1.059 is multi-pipe overhead */
+ if (inst->fw_caps[PIPE].value > 1)
+ vpp_cycles += div_u64(vpp_cycles * 59, 1000);
+
+ vsp_cycles = fps * data_size * 8;
+ vsp_cycles = div_u64(vsp_cycles, 2);
+ /* VSP FW overhead 1.05 */
+ vsp_cycles = div_u64(vsp_cycles * 21, 20);
+
+ if (inst->fw_caps[STAGE].value == STAGE_1)
+ vsp_cycles = vsp_cycles * 3;
+
+ return max3(vpp_cycles, vsp_cycles, fw_cycles);
+}
+
int iris_vpu_power_on(struct iris_core *core)
{
u32 freq;
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h
index d636e287457adf0c44540af5c85cfa69decbca8b..7cf4304604cca590544a938c7e811c202cea3d93 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.h
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h
@@ -33,5 +33,9 @@ int iris_vpu_power_on(struct iris_core *core);
int iris_vpu_power_off_controller(struct iris_core *core);
void iris_vpu_power_off_hw(struct iris_core *core);
void iris_vpu_power_off(struct iris_core *core);
+int iris_vpu35_vpu4x_power_off_controller(struct iris_core *core);
+int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core);
+void iris_vpu35_vpu4x_program_bootup_registers(struct iris_core *core);
+u64 iris_vpu3x_vpu4x_calculate_frequency(struct iris_inst *inst, size_t data_size);
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH 7/8] media: iris: Introduce vpu ops for vpu4 with necessary hooks
2025-09-24 23:14 [PATCH 0/8] media: iris: add support for video codecs on Qcom kaanapali platform Vikash Garodia
` (5 preceding siblings ...)
2025-09-24 23:14 ` [PATCH 6/8] media: iris: Move vpu35 specific api to common to use for vpu4 Vikash Garodia
@ 2025-09-24 23:14 ` Vikash Garodia
2025-09-25 9:18 ` Konrad Dybcio
2025-09-24 23:14 ` [PATCH 8/8] media: iris: Add platform data for kaanapali Vikash Garodia
7 siblings, 1 reply; 54+ messages in thread
From: Vikash Garodia @ 2025-09-24 23:14 UTC (permalink / raw)
To: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy, Vikash Garodia
Add power sequence for vpu4 by reusing from previous generation wherever
possible. Hook up vpu4 op with vpu4 specific implemtation or resue from
earlier generation wherever feasible, like clock calculation in this
case.
Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/Makefile | 1 +
.../platform/qcom/iris/iris_platform_common.h | 7 +
drivers/media/platform/qcom/iris/iris_vpu4x.c | 367 +++++++++++++++++++++
drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 +
4 files changed, 376 insertions(+)
diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile
index 13270cd6d899852dded675b33d37f5919b81ccba..1446f5732ab51db85ea4f52636d29e36d82b7a8f 100644
--- a/drivers/media/platform/qcom/iris/Makefile
+++ b/drivers/media/platform/qcom/iris/Makefile
@@ -22,6 +22,7 @@ qcom-iris-objs += iris_buffer.o \
iris_venc.o \
iris_vpu2.o \
iris_vpu3x.o \
+ iris_vpu4x.o \
iris_vpu_buffer.o \
iris_vpu_common.o \
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index ae49e95ba2252fc1442f7c81d8010dbfd86da0da..d6d4a9fdfc189797f903dfeb56d931741b405ee2 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -54,6 +54,10 @@ enum platform_clk_type {
IRIS_AXI1_CLK,
IRIS_CTRL_FREERUN_CLK,
IRIS_HW_FREERUN_CLK,
+ IRIS_BSE_HW_CLK,
+ IRIS_VPP0_HW_CLK,
+ IRIS_VPP1_HW_CLK,
+ IRIS_APV_HW_CLK,
};
struct platform_clk_data {
@@ -188,6 +192,9 @@ struct icc_vote_data {
enum platform_pm_domain_type {
IRIS_CTRL_POWER_DOMAIN,
IRIS_HW_POWER_DOMAIN,
+ IRIS_VPP0_HW_POWER_DOMAIN,
+ IRIS_VPP1_HW_POWER_DOMAIN,
+ IRIS_APV_HW_POWER_DOMAIN,
};
struct iris_platform_data {
diff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/platform/qcom/iris/iris_vpu4x.c
new file mode 100644
index 0000000000000000000000000000000000000000..5585ed84d498be057c20927725b02a5409d18867
--- /dev/null
+++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c
@@ -0,0 +1,367 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/iopoll.h>
+#include <linux/reset.h>
+#include "iris_instance.h"
+#include "iris_vpu_common.h"
+#include "iris_vpu_register_defines.h"
+
+#define WRAPPER_EFUSE_MONITOR (WRAPPER_BASE_OFFS + 0x08)
+#define AON_WRAPPER_MVP_NOC_RESET_SYNCRST (AON_MVP_NOC_RESET + 0x08)
+#define CPU_CS_APV_BRIDGE_SYNC_RESET (CPU_BASE_OFFS + 0x174)
+#define DISABLE_VIDEO_APV_BIT BIT(27)
+#define DISABLE_VIDEO_VPP1_BIT BIT(28)
+#define DISABLE_VIDEO_VPP0_BIT BIT(29)
+#define CORE_CLK_HALT BIT(0)
+#define APV_CLK_HALT BIT(1)
+#define CORE_PWR_ON BIT(1)
+
+static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode)
+{
+ u32 value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR);
+ int ret;
+
+ ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], hw_mode);
+ if (ret)
+ return ret;
+
+ if (!(value & DISABLE_VIDEO_VPP0_BIT)) {
+ ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs
+ [IRIS_VPP0_HW_POWER_DOMAIN], hw_mode);
+ if (ret)
+ goto restore_hw_domain_mode;
+ }
+
+ if (!(value & DISABLE_VIDEO_VPP1_BIT)) {
+ ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs
+ [IRIS_VPP1_HW_POWER_DOMAIN], hw_mode);
+ if (ret)
+ goto restore_vpp0_domain_mode;
+ }
+
+ if (!(value & DISABLE_VIDEO_APV_BIT)) {
+ ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs
+ [IRIS_APV_HW_POWER_DOMAIN], hw_mode);
+ if (ret)
+ goto restore_vpp1_domain_mode;
+ }
+
+ return 0;
+
+restore_vpp1_domain_mode:
+ if (!(value & DISABLE_VIDEO_VPP1_BIT))
+ dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP1_HW_POWER_DOMAIN],
+ !hw_mode);
+restore_vpp0_domain_mode:
+ if (!(value & DISABLE_VIDEO_VPP0_BIT))
+ dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP0_HW_POWER_DOMAIN],
+ !hw_mode);
+restore_hw_domain_mode:
+ dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], !hw_mode);
+
+ return ret;
+}
+
+static int iris_vpu4x_power_on_apv(struct iris_core *core)
+{
+ u32 value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR);
+ int ret;
+
+ if (value & DISABLE_VIDEO_APV_BIT)
+ return 0;
+
+ ret = iris_enable_power_domains(core,
+ core->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]);
+ if (ret)
+ return ret;
+
+ ret = iris_prepare_enable_clock(core, IRIS_APV_HW_CLK);
+ if (ret)
+ goto disable_apv_hw_power_domain;
+
+ return 0;
+
+disable_apv_hw_power_domain:
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]);
+
+ return ret;
+}
+
+static void iris_vpu4x_power_off_apv(struct iris_core *core)
+{
+ bool handshake_done, handshake_busy;
+ u32 value, count = 0;
+
+ value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR);
+
+ if (value & DISABLE_VIDEO_APV_BIT)
+ return;
+
+ value = readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG);
+
+ if (value & APV_CLK_HALT)
+ writel(0x0, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG);
+
+ do {
+ writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
+ usleep_range(10, 20);
+ value = readl(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS);
+
+ handshake_done = value & NOC_LPI_STATUS_DONE;
+ handshake_busy = value & (NOC_LPI_STATUS_DENY | NOC_LPI_STATUS_ACTIVE);
+
+ if (handshake_done || !handshake_busy)
+ break;
+
+ writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
+ usleep_range(10, 20);
+
+ } while (++count < 1000);
+
+ if (!handshake_done && handshake_busy)
+ dev_err(core->dev, "LPI handshake timeout\n");
+
+ writel(0x080200, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ);
+ readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK,
+ value, value & 0x080200, 200, 2000);
+
+ writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_SYNCRST);
+ writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ);
+ readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK,
+ value, value == 0x0, 200, 2000);
+
+ writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base +
+ CPU_CS_APV_BRIDGE_SYNC_RESET);
+ writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_APV_BRIDGE_SYNC_RESET);
+ writel(0x0, core->reg_base + CPU_CS_APV_BRIDGE_SYNC_RESET);
+
+ iris_disable_unprepare_clock(core, IRIS_APV_HW_CLK);
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]);
+}
+
+static void iris_vpu4x_ahb_sync_reset_apv(struct iris_core *core)
+{
+ u32 value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR);
+
+ if (value & DISABLE_VIDEO_APV_BIT)
+ return;
+
+ writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base +
+ CPU_CS_APV_BRIDGE_SYNC_RESET);
+ writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_APV_BRIDGE_SYNC_RESET);
+ writel(0x0, core->reg_base + CPU_CS_APV_BRIDGE_SYNC_RESET);
+}
+
+static void iris_vpu4x_ahb_sync_reset_hardware(struct iris_core *core)
+{
+ writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base +
+ CPU_CS_AHB_BRIDGE_SYNC_RESET);
+ writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
+ writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
+}
+
+static int iris_vpu4x_enable_hardware_clocks(struct iris_core *core)
+{
+ u32 value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR);
+ int ret;
+
+ ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK);
+ if (ret)
+ return ret;
+
+ ret = iris_prepare_enable_clock(core, IRIS_HW_FREERUN_CLK);
+ if (ret)
+ goto disable_axi_clock;
+
+ ret = iris_prepare_enable_clock(core, IRIS_HW_CLK);
+ if (ret)
+ goto disable_hw_free_run_clock;
+
+ ret = iris_prepare_enable_clock(core, IRIS_BSE_HW_CLK);
+ if (ret)
+ goto disable_hw_clock;
+
+ if (!(value & DISABLE_VIDEO_VPP0_BIT)) {
+ ret = iris_prepare_enable_clock(core, IRIS_VPP0_HW_CLK);
+ if (ret)
+ goto disable_bse_hw_clock;
+ }
+
+ if (!(value & DISABLE_VIDEO_VPP1_BIT)) {
+ ret = iris_prepare_enable_clock(core, IRIS_VPP1_HW_CLK);
+ if (ret)
+ goto disable_vpp0_hw_clock;
+ }
+
+ return 0;
+
+disable_vpp0_hw_clock:
+ iris_disable_unprepare_clock(core, IRIS_VPP0_HW_CLK);
+disable_bse_hw_clock:
+ iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK);
+disable_hw_clock:
+ iris_disable_unprepare_clock(core, IRIS_HW_CLK);
+disable_hw_free_run_clock:
+ iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK);
+disable_axi_clock:
+ iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
+
+ return ret;
+}
+
+static void iris_vpu4x_disable_hardware_clocks(struct iris_core *core)
+{
+ u32 value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR);
+
+ if (!(value & DISABLE_VIDEO_VPP1_BIT))
+ iris_disable_unprepare_clock(core, IRIS_VPP1_HW_CLK);
+
+ if (!(value & DISABLE_VIDEO_VPP0_BIT))
+ iris_disable_unprepare_clock(core, IRIS_VPP0_HW_CLK);
+
+ iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK);
+ iris_disable_unprepare_clock(core, IRIS_HW_CLK);
+ iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK);
+ iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
+}
+
+static int iris_vpu4x_power_on_hardware(struct iris_core *core)
+{
+ u32 value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR);
+ int ret;
+
+ ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+ if (ret)
+ return ret;
+
+ if (!(value & DISABLE_VIDEO_VPP0_BIT)) {
+ ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs
+ [IRIS_VPP0_HW_POWER_DOMAIN]);
+ if (ret)
+ goto disable_hw_power_domain;
+ }
+
+ if (!(value & DISABLE_VIDEO_VPP1_BIT)) {
+ ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs
+ [IRIS_VPP1_HW_POWER_DOMAIN]);
+ if (ret)
+ goto disable_vpp0_power_domain;
+ }
+
+ ret = iris_vpu4x_enable_hardware_clocks(core);
+ if (ret)
+ goto disable_vpp1_power_domain;
+
+ ret = iris_vpu4x_power_on_apv(core);
+ if (ret)
+ goto disable_hw_clocks;
+
+ iris_vpu4x_ahb_sync_reset_apv(core);
+ iris_vpu4x_ahb_sync_reset_hardware(core);
+
+ ret = iris_vpu4x_genpd_set_hwmode(core, true);
+ if (ret)
+ goto disable_apv_power_domain;
+
+ return 0;
+
+disable_apv_power_domain:
+ iris_vpu4x_power_off_apv(core);
+disable_hw_clocks:
+ iris_vpu4x_disable_hardware_clocks(core);
+disable_vpp1_power_domain:
+ if (!(value & DISABLE_VIDEO_VPP1_BIT))
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs
+ [IRIS_VPP1_HW_POWER_DOMAIN]);
+disable_vpp0_power_domain:
+ if (!(value & DISABLE_VIDEO_VPP0_BIT))
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs
+ [IRIS_VPP0_HW_POWER_DOMAIN]);
+disable_hw_power_domain:
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+
+ return ret;
+}
+
+static void iris_vpu4x_power_off_hardware(struct iris_core *core)
+{
+ bool handshake_done, handshake_busy;
+ u32 value, count = 0;
+
+ iris_vpu4x_genpd_set_hwmode(core, false);
+
+ iris_vpu4x_power_off_apv(core);
+
+ value = readl(core->reg_base + WRAPPER_CORE_POWER_STATUS);
+
+ if (!(value & CORE_PWR_ON))
+ goto disable_clocks_and_power;
+
+ value = readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG);
+
+ if (value & CORE_CLK_HALT)
+ writel(0x0, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG);
+
+ readl_poll_timeout(core->reg_base + VCODEC_SS_IDLE_STATUSN, value,
+ value & 0x7103, 2000, 20000);
+
+ do {
+ writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
+ usleep_range(10, 20);
+ value = readl(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS);
+
+ handshake_done = value & NOC_LPI_STATUS_DONE;
+ handshake_busy = value & (NOC_LPI_STATUS_DENY | NOC_LPI_STATUS_ACTIVE);
+
+ if (handshake_done || !handshake_busy)
+ break;
+
+ writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
+ usleep_range(10, 20);
+
+ } while (++count < 1000);
+
+ if (!handshake_done && handshake_busy)
+ dev_err(core->dev, "LPI handshake timeout\n");
+
+ writel(0x070103, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ);
+ readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK,
+ value, value == 0x070103, 200, 2000);
+
+ writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_SYNCRST);
+ writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ);
+ readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK,
+ value, value == 0x0, 200, 2000);
+
+ writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base +
+ CPU_CS_AHB_BRIDGE_SYNC_RESET);
+ writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
+ writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
+
+disable_clocks_and_power:
+ iris_vpu4x_disable_hardware_clocks(core);
+
+ value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR);
+
+ if (!(value & DISABLE_VIDEO_VPP1_BIT))
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs
+ [IRIS_VPP1_HW_POWER_DOMAIN]);
+
+ if (!(value & DISABLE_VIDEO_VPP0_BIT))
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs
+ [IRIS_VPP0_HW_POWER_DOMAIN]);
+
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+}
+
+const struct vpu_ops iris_vpu4x_ops = {
+ .power_off_hw = iris_vpu4x_power_off_hardware,
+ .power_on_hw = iris_vpu4x_power_on_hardware,
+ .power_off_controller = iris_vpu35_vpu4x_power_off_controller,
+ .power_on_controller = iris_vpu35_vpu4x_power_on_controller,
+ .program_bootup_registers = iris_vpu35_vpu4x_program_bootup_registers,
+ .calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
+};
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h
index 7cf4304604cca590544a938c7e811c202cea3d93..f6dffc613b822341fb21e12de6b1395202f62cde 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.h
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h
@@ -12,6 +12,7 @@ extern const struct vpu_ops iris_vpu2_ops;
extern const struct vpu_ops iris_vpu3_ops;
extern const struct vpu_ops iris_vpu33_ops;
extern const struct vpu_ops iris_vpu35_ops;
+extern const struct vpu_ops iris_vpu4x_ops;
struct vpu_ops {
void (*power_off_hw)(struct iris_core *core);
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH 7/8] media: iris: Introduce vpu ops for vpu4 with necessary hooks
2025-09-24 23:14 ` [PATCH 7/8] media: iris: Introduce vpu ops for vpu4 with necessary hooks Vikash Garodia
@ 2025-09-25 9:18 ` Konrad Dybcio
2025-09-29 5:45 ` Vishnu Reddy
0 siblings, 1 reply; 54+ messages in thread
From: Konrad Dybcio @ 2025-09-25 9:18 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 9/25/25 1:14 AM, Vikash Garodia wrote:
> Add power sequence for vpu4 by reusing from previous generation wherever
> possible. Hook up vpu4 op with vpu4 specific implemtation or resue from
> earlier generation wherever feasible, like clock calculation in this
> case.
>
> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> ---
[...]
> +#include <linux/iopoll.h>
> +#include <linux/reset.h>
> +#include "iris_instance.h"
> +#include "iris_vpu_common.h"
> +#include "iris_vpu_register_defines.h"
> +
> +#define WRAPPER_EFUSE_MONITOR (WRAPPER_BASE_OFFS + 0x08)
> +#define AON_WRAPPER_MVP_NOC_RESET_SYNCRST (AON_MVP_NOC_RESET + 0x08)
> +#define CPU_CS_APV_BRIDGE_SYNC_RESET (CPU_BASE_OFFS + 0x174)
> +#define DISABLE_VIDEO_APV_BIT BIT(27)
> +#define DISABLE_VIDEO_VPP1_BIT BIT(28)
> +#define DISABLE_VIDEO_VPP0_BIT BIT(29)
> +#define CORE_CLK_HALT BIT(0)
> +#define APV_CLK_HALT BIT(1)
> +#define CORE_PWR_ON BIT(1)
> +
> +static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode)
> +{
> + u32 value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR);
I think this could use some explanations.
I'll go ahead and assume that the eFuse tells us that parts of the
IP are disables (hopefully not all three at once.. we shouldn't
advertise the v4l2 device then, probably)
You read back the fuse register a lot, even though I presume it's not
supposed to change at runtime. How about we add:
bool vpp0_fused_off
bool vpp1_fused_off
bool apv_fused_off
instead?
[...]
> + if (!(value & DISABLE_VIDEO_VPP0_BIT)) {
> + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs
> + [IRIS_VPP0_HW_POWER_DOMAIN]);
Maybe the iris_en/disable_foo functions could get a wrapper like:
int iris_enable_power_domains_if(core, pd_devs[IRIS_VPP0_HW_POWER_DOMAIN],
!foo->vpp0_fused_off)
I'm not super sure about it, but that's something to consider
[...]
> + readl_poll_timeout(core->reg_base + VCODEC_SS_IDLE_STATUSN, value,
> + value & 0x7103, 2000, 20000);
That's a nice magic number.. but what does it mean?
[...]
> + writel(0x070103, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ);
> + readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK,
> + value, value == 0x070103, 200, 2000);
That's a slightly different magic number, but it's oddly similar to
the one above
Konrad
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH 7/8] media: iris: Introduce vpu ops for vpu4 with necessary hooks
2025-09-25 9:18 ` Konrad Dybcio
@ 2025-09-29 5:45 ` Vishnu Reddy
2025-10-02 9:41 ` Vikash Garodia
2025-10-07 13:21 ` Konrad Dybcio
0 siblings, 2 replies; 54+ messages in thread
From: Vishnu Reddy @ 2025-09-29 5:45 UTC (permalink / raw)
To: Konrad Dybcio, Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel
On 9/25/2025 2:48 PM, Konrad Dybcio wrote:
> On 9/25/25 1:14 AM, Vikash Garodia wrote:
>> Add power sequence for vpu4 by reusing from previous generation wherever
>> possible. Hook up vpu4 op with vpu4 specific implemtation or resue from
>> earlier generation wherever feasible, like clock calculation in this
>> case.
>>
>> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
>> ---
>
> [...]
>
>> +#include <linux/iopoll.h>
>> +#include <linux/reset.h>
>> +#include "iris_instance.h"
>> +#include "iris_vpu_common.h"
>> +#include "iris_vpu_register_defines.h"
>> +
>> +#define WRAPPER_EFUSE_MONITOR (WRAPPER_BASE_OFFS + 0x08)
>> +#define AON_WRAPPER_MVP_NOC_RESET_SYNCRST (AON_MVP_NOC_RESET + 0x08)
>> +#define CPU_CS_APV_BRIDGE_SYNC_RESET (CPU_BASE_OFFS + 0x174)
>> +#define DISABLE_VIDEO_APV_BIT BIT(27)
>> +#define DISABLE_VIDEO_VPP1_BIT BIT(28)
>> +#define DISABLE_VIDEO_VPP0_BIT BIT(29)
>> +#define CORE_CLK_HALT BIT(0)
>> +#define APV_CLK_HALT BIT(1)
>> +#define CORE_PWR_ON BIT(1)
>> +
>> +static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode)
>> +{
>> + u32 value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR);
>
> I think this could use some explanations.
>
> I'll go ahead and assume that the eFuse tells us that parts of the
> IP are disables (hopefully not all three at once.. we shouldn't
> advertise the v4l2 device then, probably)
>
> You read back the fuse register a lot, even though I presume it's not
> supposed to change at runtime. How about we add:
>
> bool vpp0_fused_off
> bool vpp1_fused_off
> bool apv_fused_off
>
> instead?
>
Hi Konrad, Thanks for your review and suggestion.
The poweroff and poweron ops will be called in each test. There is no
ops available that called onetime only to cache these values.
And, to create any variable, Need to add as static global in this file
because these are specific to this platform and I feel it's not
recommended code to add into any common structures as a member.
Do you have any suggestion from your side how this can be do it in a
simple way?
> [...]
>
>> + if (!(value & DISABLE_VIDEO_VPP0_BIT)) {
>> + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs
>> + [IRIS_VPP0_HW_POWER_DOMAIN]);
>
> Maybe the iris_en/disable_foo functions could get a wrapper like:
>
> int iris_enable_power_domains_if(core, pd_devs[IRIS_VPP0_HW_POWER_DOMAIN],
> !foo->vpp0_fused_off)
>
> I'm not super sure about it, but that's something to consider
>
> [...]
>
>> + readl_poll_timeout(core->reg_base + VCODEC_SS_IDLE_STATUSN, value,
>> + value & 0x7103, 2000, 20000);
>
> That's a nice magic number.. but what does it mean?
>
ACK, Will add macro definitions for these numbers.
> [...]
>
>> + writel(0x070103, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ);
>> + readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK,
>> + value, value == 0x070103, 200, 2000);
>
> That's a slightly different magic number, but it's oddly similar to
> the one above
>
ACK.
Thanks and regards,
Vishnu Reddy
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH 7/8] media: iris: Introduce vpu ops for vpu4 with necessary hooks
2025-09-29 5:45 ` Vishnu Reddy
@ 2025-10-02 9:41 ` Vikash Garodia
2025-10-07 13:21 ` Konrad Dybcio
1 sibling, 0 replies; 54+ messages in thread
From: Vikash Garodia @ 2025-10-02 9:41 UTC (permalink / raw)
To: Vishnu Reddy, Konrad Dybcio, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel
On 9/29/2025 11:15 AM, Vishnu Reddy wrote:
>
>
> On 9/25/2025 2:48 PM, Konrad Dybcio wrote:
>> On 9/25/25 1:14 AM, Vikash Garodia wrote:
>>> Add power sequence for vpu4 by reusing from previous generation wherever
>>> possible. Hook up vpu4 op with vpu4 specific implemtation or resue from
>>> earlier generation wherever feasible, like clock calculation in this
>>> case.
>>>
>>> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>>> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>>> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
>>> ---
>>
>> [...]
>>
>>> +#include <linux/iopoll.h>
>>> +#include <linux/reset.h>
>>> +#include "iris_instance.h"
>>> +#include "iris_vpu_common.h"
>>> +#include "iris_vpu_register_defines.h"
>>> +
>>> +#define WRAPPER_EFUSE_MONITOR (WRAPPER_BASE_OFFS + 0x08)
>>> +#define AON_WRAPPER_MVP_NOC_RESET_SYNCRST (AON_MVP_NOC_RESET + 0x08)
>>> +#define CPU_CS_APV_BRIDGE_SYNC_RESET (CPU_BASE_OFFS + 0x174)
>>> +#define DISABLE_VIDEO_APV_BIT BIT(27)
>>> +#define DISABLE_VIDEO_VPP1_BIT BIT(28)
>>> +#define DISABLE_VIDEO_VPP0_BIT BIT(29)
>>> +#define CORE_CLK_HALT BIT(0)
>>> +#define APV_CLK_HALT BIT(1)
>>> +#define CORE_PWR_ON BIT(1)
>>> +
>>> +static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode)
>>> +{
>>> + u32 value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR);
>>
>> I think this could use some explanations.
>>
>> I'll go ahead and assume that the eFuse tells us that parts of the
>> IP are disables (hopefully not all three at once.. we shouldn't
>> advertise the v4l2 device then, probably)
>>
>> You read back the fuse register a lot, even though I presume it's not
>> supposed to change at runtime. How about we add:
>>
>> bool vpp0_fused_off
>> bool vpp1_fused_off
>> bool apv_fused_off
>>
>> instead?
>>
>
> Hi Konrad, Thanks for your review and suggestion.
>
> The poweroff and poweron ops will be called in each test. There is no
> ops available that called onetime only to cache these values.
> And, to create any variable, Need to add as static global in this file
> because these are specific to this platform and I feel it's not
> recommended code to add into any common structures as a member.
>
> Do you have any suggestion from your side how this can be do it in a
> simple way?
IMO, its a fair point from Konrad to avoid register read multiple times. We will
recheck this and optimize it to the extent possible.
Regards,
Vikash
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH 7/8] media: iris: Introduce vpu ops for vpu4 with necessary hooks
2025-09-29 5:45 ` Vishnu Reddy
2025-10-02 9:41 ` Vikash Garodia
@ 2025-10-07 13:21 ` Konrad Dybcio
1 sibling, 0 replies; 54+ messages in thread
From: Konrad Dybcio @ 2025-10-07 13:21 UTC (permalink / raw)
To: Vishnu Reddy, Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel
On 9/29/25 7:45 AM, Vishnu Reddy wrote:
>
>
> On 9/25/2025 2:48 PM, Konrad Dybcio wrote:
>> On 9/25/25 1:14 AM, Vikash Garodia wrote:
>>> Add power sequence for vpu4 by reusing from previous generation wherever
>>> possible. Hook up vpu4 op with vpu4 specific implemtation or resue from
>>> earlier generation wherever feasible, like clock calculation in this
>>> case.
>>>
>>> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>>> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>>> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
>>> ---
>>
>> [...]
>>
>>> +#include <linux/iopoll.h>
>>> +#include <linux/reset.h>
>>> +#include "iris_instance.h"
>>> +#include "iris_vpu_common.h"
>>> +#include "iris_vpu_register_defines.h"
>>> +
>>> +#define WRAPPER_EFUSE_MONITOR (WRAPPER_BASE_OFFS + 0x08)
>>> +#define AON_WRAPPER_MVP_NOC_RESET_SYNCRST (AON_MVP_NOC_RESET + 0x08)
>>> +#define CPU_CS_APV_BRIDGE_SYNC_RESET (CPU_BASE_OFFS + 0x174)
>>> +#define DISABLE_VIDEO_APV_BIT BIT(27)
>>> +#define DISABLE_VIDEO_VPP1_BIT BIT(28)
>>> +#define DISABLE_VIDEO_VPP0_BIT BIT(29)
>>> +#define CORE_CLK_HALT BIT(0)
>>> +#define APV_CLK_HALT BIT(1)
>>> +#define CORE_PWR_ON BIT(1)
>>> +
>>> +static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode)
>>> +{
>>> + u32 value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR);
>>
>> I think this could use some explanations.
>>
>> I'll go ahead and assume that the eFuse tells us that parts of the
>> IP are disables (hopefully not all three at once.. we shouldn't
>> advertise the v4l2 device then, probably)
>>
>> You read back the fuse register a lot, even though I presume it's not
>> supposed to change at runtime. How about we add:
>>
>> bool vpp0_fused_off
>> bool vpp1_fused_off
>> bool apv_fused_off
>>
>> instead?
>>
>
> Hi Konrad, Thanks for your review and suggestion.
>
> The poweroff and poweron ops will be called in each test. There is no
> ops available that called onetime only to cache these values.
> And, to create any variable, Need to add as static global in this file
> because these are specific to this platform and I feel it's not
> recommended code to add into any common structures as a member.
>
> Do you have any suggestion from your side how this can be do it in a
> simple way?
Can we not just read it at probe / fw loading time and store the data in
iris_core?
Konrad
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH 8/8] media: iris: Add platform data for kaanapali
2025-09-24 23:14 [PATCH 0/8] media: iris: add support for video codecs on Qcom kaanapali platform Vikash Garodia
` (6 preceding siblings ...)
2025-09-24 23:14 ` [PATCH 7/8] media: iris: Introduce vpu ops for vpu4 with necessary hooks Vikash Garodia
@ 2025-09-24 23:14 ` Vikash Garodia
2025-09-25 2:44 ` Dmitry Baryshkov
` (2 more replies)
7 siblings, 3 replies; 54+ messages in thread
From: Vikash Garodia @ 2025-09-24 23:14 UTC (permalink / raw)
To: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy, Vikash Garodia
Add support for the kaanapali platform by re-using the SM8550
definitions and using the vpu4 ops.
Move the configurations that differs in a per-SoC platform
header, that will contain SoC specific data.
Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
---
.../platform/qcom/iris/iris_platform_common.h | 1 +
.../media/platform/qcom/iris/iris_platform_gen2.c | 86 ++++++++++++++++++++++
.../platform/qcom/iris/iris_platform_kaanapali.h | 63 ++++++++++++++++
drivers/media/platform/qcom/iris/iris_probe.c | 4 +
4 files changed, 154 insertions(+)
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index d6d4a9fdfc189797f903dfeb56d931741b405ee2..465943db0c6671e9b564b40e31ce6ba2d645a84c 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -46,6 +46,7 @@ extern struct iris_platform_data sm8250_data;
extern struct iris_platform_data sm8550_data;
extern struct iris_platform_data sm8650_data;
extern struct iris_platform_data sm8750_data;
+extern struct iris_platform_data kaanapali_data;
enum platform_clk_type {
IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */
diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
index 00c6b9021b98aac80612b1bb9734c8dac8146bd9..142b7d84ee00a9b65420158ac1f168515b56f4a3 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
@@ -15,6 +15,7 @@
#include "iris_platform_qcs8300.h"
#include "iris_platform_sm8650.h"
#include "iris_platform_sm8750.h"
+#include "iris_platform_kaanapali.h"
#define VIDEO_ARCH_LX 1
#define BITRATE_MAX 245000000
@@ -1095,3 +1096,88 @@ struct iris_platform_data qcs8300_data = {
.enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
.enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
};
+
+struct iris_platform_data kaanapali_data = {
+ .get_instance = iris_hfi_gen2_get_instance,
+ .init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
+ .init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
+ .get_vpu_buffer_size = iris_vpu4x_buf_size,
+ .vpu_ops = &iris_vpu4x_ops,
+ .set_preset_registers = iris_set_sm8550_preset_registers,
+ .icc_tbl = sm8550_icc_table,
+ .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
+ .clk_rst_tbl = kaanapali_clk_reset_table,
+ .clk_rst_tbl_size = ARRAY_SIZE(kaanapali_clk_reset_table),
+ .bw_tbl_dec = sm8550_bw_table_dec,
+ .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
+ .pmdomain_tbl = kaanapali_pmdomain_table,
+ .pmdomain_tbl_size = ARRAY_SIZE(kaanapali_pmdomain_table),
+ .opp_pd_tbl = sm8550_opp_pd_table,
+ .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
+ .clk_tbl = kaanapali_clk_table,
+ .clk_tbl_size = ARRAY_SIZE(kaanapali_clk_table),
+ .opp_clk_tbl = kaanapali_opp_clk_table,
+ /* Upper bound of DMA address range */
+ .dma_mask = 0xe0000000 - 1,
+ .fwname = "qcom/vpu/vpu40_p2.mbn",
+ .pas_id = IRIS_PAS_ID,
+ .inst_caps = &platform_inst_cap_sm8550,
+ .inst_fw_caps_dec = inst_fw_cap_sm8550_dec,
+ .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
+ .inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
+ .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
+ .tz_cp_config_data = tz_cp_config_kaanapali,
+ .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_kaanapali),
+ .core_arch = VIDEO_ARCH_LX,
+ .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
+ .ubwc_config = &ubwc_config_sm8550,
+ .num_vpp_pipe = 2,
+ .max_session_count = 16,
+ .max_core_mbpf = NUM_MBS_8K * 2,
+ .max_core_mbps = ((8192 * 4352) / 256) * 60,
+ .dec_input_config_params_default =
+ sm8550_vdec_input_config_params_default,
+ .dec_input_config_params_default_size =
+ ARRAY_SIZE(sm8550_vdec_input_config_params_default),
+ .dec_input_config_params_hevc =
+ sm8550_vdec_input_config_param_hevc,
+ .dec_input_config_params_hevc_size =
+ ARRAY_SIZE(sm8550_vdec_input_config_param_hevc),
+ .dec_input_config_params_vp9 =
+ sm8550_vdec_input_config_param_vp9,
+ .dec_input_config_params_vp9_size =
+ ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
+ .dec_output_config_params =
+ sm8550_vdec_output_config_params,
+ .dec_output_config_params_size =
+ ARRAY_SIZE(sm8550_vdec_output_config_params),
+
+ .enc_input_config_params =
+ sm8550_venc_input_config_params,
+ .enc_input_config_params_size =
+ ARRAY_SIZE(sm8550_venc_input_config_params),
+ .enc_output_config_params =
+ sm8550_venc_output_config_params,
+ .enc_output_config_params_size =
+ ARRAY_SIZE(sm8550_venc_output_config_params),
+
+ .dec_input_prop = sm8550_vdec_subscribe_input_properties,
+ .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties),
+ .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc,
+ .dec_output_prop_avc_size =
+ ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc),
+ .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc,
+ .dec_output_prop_hevc_size =
+ ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc),
+ .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
+ .dec_output_prop_vp9_size =
+ ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
+
+ .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
+ .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),
+ .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,
+ .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),
+
+ .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
+ .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
+};
diff --git a/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h
new file mode 100644
index 0000000000000000000000000000000000000000..247fb9d7cb632d2e9a1e9832d087cb03ac9b7cf3
--- /dev/null
+++ b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef __IRIS_PLATFORM_KAANAPALI_H__
+#define __IRIS_PLATFORM_KAANAPALI_H__
+
+#define VIDEO_REGION_VM0_SECURE_NP_ID 1
+#define VIDEO_REGION_VM0_NONSECURE_NP_ID 5
+
+static const char *const kaanapali_clk_reset_table[] = {
+ "bus0",
+ "bus1",
+ "core_freerun_reset",
+ "vcodec0_core_freerun_reset",
+};
+
+static const char *const kaanapali_pmdomain_table[] = {
+ "venus",
+ "vcodec0",
+ "vpp0",
+ "vpp1",
+ "apv",
+};
+
+static const struct platform_clk_data kaanapali_clk_table[] = {
+ { IRIS_AXI_CLK, "iface" },
+ { IRIS_CTRL_CLK, "core" },
+ { IRIS_HW_CLK, "vcodec0_core" },
+ { IRIS_AXI1_CLK, "iface1" },
+ { IRIS_CTRL_FREERUN_CLK, "core_freerun" },
+ { IRIS_HW_FREERUN_CLK, "vcodec0_core_freerun" },
+ { IRIS_BSE_HW_CLK, "vcodec_bse" },
+ { IRIS_VPP0_HW_CLK, "vcodec_vpp0" },
+ { IRIS_VPP1_HW_CLK, "vcodec_vpp1" },
+ { IRIS_APV_HW_CLK, "vcodec_apv" },
+};
+
+static const char *const kaanapali_opp_clk_table[] = {
+ "vcodec0_core",
+ "vcodec_apv",
+ "vcodec_bse",
+ "core",
+ NULL,
+};
+
+static struct tz_cp_config tz_cp_config_kaanapali[] = {
+ {
+ .cp_start = VIDEO_REGION_VM0_SECURE_NP_ID,
+ .cp_size = 0,
+ .cp_nonpixel_start = 0x01000000,
+ .cp_nonpixel_size = 0x24800000,
+ },
+ {
+ .cp_start = VIDEO_REGION_VM0_NONSECURE_NP_ID,
+ .cp_size = 0,
+ .cp_nonpixel_start = 0x25800000,
+ .cp_nonpixel_size = 0xda400000,
+ },
+};
+
+#endif /* __IRIS_PLATFORM_KAANAPALI_H__ */
diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c
index ad82a62f8b923d818ffe77c131d7eb6da8c34002..9a0db65dbdb2eedf3974bcb8a2327e664b556ccd 100644
--- a/drivers/media/platform/qcom/iris/iris_probe.c
+++ b/drivers/media/platform/qcom/iris/iris_probe.c
@@ -370,6 +370,10 @@ static const struct of_device_id iris_dt_match[] = {
.compatible = "qcom,sm8750-iris",
.data = &sm8750_data,
},
+ {
+ .compatible = "qcom,kaanapali-iris",
+ .data = &kaanapali_data,
+ },
{ },
};
MODULE_DEVICE_TABLE(of, iris_dt_match);
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH 8/8] media: iris: Add platform data for kaanapali
2025-09-24 23:14 ` [PATCH 8/8] media: iris: Add platform data for kaanapali Vikash Garodia
@ 2025-09-25 2:44 ` Dmitry Baryshkov
2025-09-25 8:17 ` Vikash Garodia
2025-10-02 15:10 ` Bryan O'Donoghue
2025-10-02 15:29 ` Bryan O'Donoghue
2 siblings, 1 reply; 54+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 2:44 UTC (permalink / raw)
To: Vikash Garodia
Cc: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, linux-arm-msm, linux-media,
devicetree, linux-kernel, Vishnu Reddy
On Thu, Sep 25, 2025 at 04:44:46AM +0530, Vikash Garodia wrote:
> Add support for the kaanapali platform by re-using the SM8550
> definitions and using the vpu4 ops.
> Move the configurations that differs in a per-SoC platform
> header, that will contain SoC specific data.
>
> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> ---
> .../platform/qcom/iris/iris_platform_common.h | 1 +
> .../media/platform/qcom/iris/iris_platform_gen2.c | 86 ++++++++++++++++++++++
> .../platform/qcom/iris/iris_platform_kaanapali.h | 63 ++++++++++++++++
> drivers/media/platform/qcom/iris/iris_probe.c | 4 +
> 4 files changed, 154 insertions(+)
>
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
> index d6d4a9fdfc189797f903dfeb56d931741b405ee2..465943db0c6671e9b564b40e31ce6ba2d645a84c 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
> @@ -46,6 +46,7 @@ extern struct iris_platform_data sm8250_data;
> extern struct iris_platform_data sm8550_data;
> extern struct iris_platform_data sm8650_data;
> extern struct iris_platform_data sm8750_data;
> +extern struct iris_platform_data kaanapali_data;
Please keep it sorted
>
> enum platform_clk_type {
> IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> index 00c6b9021b98aac80612b1bb9734c8dac8146bd9..142b7d84ee00a9b65420158ac1f168515b56f4a3 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> @@ -15,6 +15,7 @@
> #include "iris_platform_qcs8300.h"
> #include "iris_platform_sm8650.h"
> #include "iris_platform_sm8750.h"
> +#include "iris_platform_kaanapali.h"
And this
>
> #define VIDEO_ARCH_LX 1
> #define BITRATE_MAX 245000000
> @@ -1095,3 +1096,88 @@ struct iris_platform_data qcs8300_data = {
> .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
> .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
> };
> +
> +struct iris_platform_data kaanapali_data = {
Hopefully can also be sorted.
> + .get_instance = iris_hfi_gen2_get_instance,
> diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c
> index ad82a62f8b923d818ffe77c131d7eb6da8c34002..9a0db65dbdb2eedf3974bcb8a2327e664b556ccd 100644
> --- a/drivers/media/platform/qcom/iris/iris_probe.c
> +++ b/drivers/media/platform/qcom/iris/iris_probe.c
> @@ -370,6 +370,10 @@ static const struct of_device_id iris_dt_match[] = {
> .compatible = "qcom,sm8750-iris",
> .data = &sm8750_data,
> },
> + {
> + .compatible = "qcom,kaanapali-iris",
> + .data = &kaanapali_data,
> + },
And this one.
> { },
> };
> MODULE_DEVICE_TABLE(of, iris_dt_match);
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH 8/8] media: iris: Add platform data for kaanapali
2025-09-25 2:44 ` Dmitry Baryshkov
@ 2025-09-25 8:17 ` Vikash Garodia
0 siblings, 0 replies; 54+ messages in thread
From: Vikash Garodia @ 2025-09-25 8:17 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, linux-arm-msm, linux-media,
devicetree, linux-kernel, Vishnu Reddy
On 9/25/2025 8:14 AM, Dmitry Baryshkov wrote:
> On Thu, Sep 25, 2025 at 04:44:46AM +0530, Vikash Garodia wrote:
>> Add support for the kaanapali platform by re-using the SM8550
>> definitions and using the vpu4 ops.
>> Move the configurations that differs in a per-SoC platform
>> header, that will contain SoC specific data.
>>
>> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
>> ---
>> .../platform/qcom/iris/iris_platform_common.h | 1 +
>> .../media/platform/qcom/iris/iris_platform_gen2.c | 86 ++++++++++++++++++++++
>> .../platform/qcom/iris/iris_platform_kaanapali.h | 63 ++++++++++++++++
>> drivers/media/platform/qcom/iris/iris_probe.c | 4 +
>> 4 files changed, 154 insertions(+)
>>
>> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
>> index d6d4a9fdfc189797f903dfeb56d931741b405ee2..465943db0c6671e9b564b40e31ce6ba2d645a84c 100644
>> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
>> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
>> @@ -46,6 +46,7 @@ extern struct iris_platform_data sm8250_data;
>> extern struct iris_platform_data sm8550_data;
>> extern struct iris_platform_data sm8650_data;
>> extern struct iris_platform_data sm8750_data;
>> +extern struct iris_platform_data kaanapali_data;
>
> Please keep it sorted
ACK. Started the development as sm8850 hence was kept at the end, and was missed
when the name was changed to kaanapali.
>
>>
>> enum platform_clk_type {
>> IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */
>> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
>> index 00c6b9021b98aac80612b1bb9734c8dac8146bd9..142b7d84ee00a9b65420158ac1f168515b56f4a3 100644
>> --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
>> +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
>> @@ -15,6 +15,7 @@
>> #include "iris_platform_qcs8300.h"
>> #include "iris_platform_sm8650.h"
>> #include "iris_platform_sm8750.h"
>> +#include "iris_platform_kaanapali.h"
>
> And this
ACK
>
>>
>> #define VIDEO_ARCH_LX 1
>> #define BITRATE_MAX 245000000
>> @@ -1095,3 +1096,88 @@ struct iris_platform_data qcs8300_data = {
>> .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
>> .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
>> };
>> +
>> +struct iris_platform_data kaanapali_data = {
>
> Hopefully can also be sorted.
Yes, this can be as well.
>
>> + .get_instance = iris_hfi_gen2_get_instance,
>> diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c
>> index ad82a62f8b923d818ffe77c131d7eb6da8c34002..9a0db65dbdb2eedf3974bcb8a2327e664b556ccd 100644
>> --- a/drivers/media/platform/qcom/iris/iris_probe.c
>> +++ b/drivers/media/platform/qcom/iris/iris_probe.c
>> @@ -370,6 +370,10 @@ static const struct of_device_id iris_dt_match[] = {
>> .compatible = "qcom,sm8750-iris",
>> .data = &sm8750_data,
>> },
>> + {
>> + .compatible = "qcom,kaanapali-iris",
>> + .data = &kaanapali_data,
>> + },
>
> And this one.
ACK.
Regards,
Vikash
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH 8/8] media: iris: Add platform data for kaanapali
2025-09-24 23:14 ` [PATCH 8/8] media: iris: Add platform data for kaanapali Vikash Garodia
2025-09-25 2:44 ` Dmitry Baryshkov
@ 2025-10-02 15:10 ` Bryan O'Donoghue
2025-10-02 15:29 ` Bryan O'Donoghue
2 siblings, 0 replies; 54+ messages in thread
From: Bryan O'Donoghue @ 2025-10-02 15:10 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 25/09/2025 00:14, Vikash Garodia wrote:
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
> index d6d4a9fdfc189797f903dfeb56d931741b405ee2..465943db0c6671e9b564b40e31ce6ba2d645a84c 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
> @@ -46,6 +46,7 @@ extern struct iris_platform_data sm8250_data;
> extern struct iris_platform_data sm8550_data;
> extern struct iris_platform_data sm8650_data;
> extern struct iris_platform_data sm8750_data;
> +extern struct iris_platform_data kaanapali_data;
I've just noticed, this breaks alphanumeric ordering.
---
bod
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH 8/8] media: iris: Add platform data for kaanapali
2025-09-24 23:14 ` [PATCH 8/8] media: iris: Add platform data for kaanapali Vikash Garodia
2025-09-25 2:44 ` Dmitry Baryshkov
2025-10-02 15:10 ` Bryan O'Donoghue
@ 2025-10-02 15:29 ` Bryan O'Donoghue
2025-10-18 6:55 ` Vishnu Reddy
2 siblings, 1 reply; 54+ messages in thread
From: Bryan O'Donoghue @ 2025-10-02 15:29 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 25/09/2025 00:14, Vikash Garodia wrote:
> Add support for the kaanapali platform by re-using the SM8550
> definitions and using the vpu4 ops.
> Move the configurations that differs in a per-SoC platform
> header, that will contain SoC specific data.
>
> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> ---
> .../platform/qcom/iris/iris_platform_common.h | 1 +
> .../media/platform/qcom/iris/iris_platform_gen2.c | 86 ++++++++++++++++++++++
> .../platform/qcom/iris/iris_platform_kaanapali.h | 63 ++++++++++++++++
> drivers/media/platform/qcom/iris/iris_probe.c | 4 +
> 4 files changed, 154 insertions(+)
>
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
> index d6d4a9fdfc189797f903dfeb56d931741b405ee2..465943db0c6671e9b564b40e31ce6ba2d645a84c 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
> @@ -46,6 +46,7 @@ extern struct iris_platform_data sm8250_data;
> extern struct iris_platform_data sm8550_data;
> extern struct iris_platform_data sm8650_data;
> extern struct iris_platform_data sm8750_data;
> +extern struct iris_platform_data kaanapali_data;
>
> enum platform_clk_type {
> IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> index 00c6b9021b98aac80612b1bb9734c8dac8146bd9..142b7d84ee00a9b65420158ac1f168515b56f4a3 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> @@ -15,6 +15,7 @@
> #include "iris_platform_qcs8300.h"
> #include "iris_platform_sm8650.h"
> #include "iris_platform_sm8750.h"
> +#include "iris_platform_kaanapali.h"
>
> #define VIDEO_ARCH_LX 1
> #define BITRATE_MAX 245000000
> @@ -1095,3 +1096,88 @@ struct iris_platform_data qcs8300_data = {
> .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
> .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
> };
> +
> +struct iris_platform_data kaanapali_data = {
> + .get_instance = iris_hfi_gen2_get_instance,
> + .init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
> + .init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
> + .get_vpu_buffer_size = iris_vpu4x_buf_size,
> + .vpu_ops = &iris_vpu4x_ops,
> + .set_preset_registers = iris_set_sm8550_preset_registers,
> + .icc_tbl = sm8550_icc_table,
> + .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
> + .clk_rst_tbl = kaanapali_clk_reset_table,
> + .clk_rst_tbl_size = ARRAY_SIZE(kaanapali_clk_reset_table),
> + .bw_tbl_dec = sm8550_bw_table_dec,
> + .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
> + .pmdomain_tbl = kaanapali_pmdomain_table,
> + .pmdomain_tbl_size = ARRAY_SIZE(kaanapali_pmdomain_table),
> + .opp_pd_tbl = sm8550_opp_pd_table,
> + .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
> + .clk_tbl = kaanapali_clk_table,
> + .clk_tbl_size = ARRAY_SIZE(kaanapali_clk_table),
> + .opp_clk_tbl = kaanapali_opp_clk_table,
> + /* Upper bound of DMA address range */
> + .dma_mask = 0xe0000000 - 1,
> + .fwname = "qcom/vpu/vpu40_p2.mbn",
> + .pas_id = IRIS_PAS_ID,
> + .inst_caps = &platform_inst_cap_sm8550,
> + .inst_fw_caps_dec = inst_fw_cap_sm8550_dec,
> + .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
> + .inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
> + .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
> + .tz_cp_config_data = tz_cp_config_kaanapali,
> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_kaanapali),
> + .core_arch = VIDEO_ARCH_LX,
> + .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> + .ubwc_config = &ubwc_config_sm8550,
> + .num_vpp_pipe = 2,
> + .max_session_count = 16,
> + .max_core_mbpf = NUM_MBS_8K * 2,
> + .max_core_mbps = ((8192 * 4352) / 256) * 60,
> + .dec_input_config_params_default =
> + sm8550_vdec_input_config_params_default,
> + .dec_input_config_params_default_size =
> + ARRAY_SIZE(sm8550_vdec_input_config_params_default),
> + .dec_input_config_params_hevc =
> + sm8550_vdec_input_config_param_hevc,
> + .dec_input_config_params_hevc_size =
> + ARRAY_SIZE(sm8550_vdec_input_config_param_hevc),
> + .dec_input_config_params_vp9 =
> + sm8550_vdec_input_config_param_vp9,
> + .dec_input_config_params_vp9_size =
> + ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
> + .dec_output_config_params =
> + sm8550_vdec_output_config_params,
> + .dec_output_config_params_size =
> + ARRAY_SIZE(sm8550_vdec_output_config_params),
> +
> + .enc_input_config_params =
> + sm8550_venc_input_config_params,
> + .enc_input_config_params_size =
> + ARRAY_SIZE(sm8550_venc_input_config_params),
> + .enc_output_config_params =
> + sm8550_venc_output_config_params,
> + .enc_output_config_params_size =
> + ARRAY_SIZE(sm8550_venc_output_config_params),
> +
> + .dec_input_prop = sm8550_vdec_subscribe_input_properties,
> + .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties),
> + .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc,
> + .dec_output_prop_avc_size =
> + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc),
> + .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc,
> + .dec_output_prop_hevc_size =
> + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc),
> + .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
> + .dec_output_prop_vp9_size =
> + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
> +
> + .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
> + .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),
> + .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,
> + .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),
> +
> + .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
> + .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
> +};
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..247fb9d7cb632d2e9a1e9832d087cb03ac9b7cf3
> --- /dev/null
> +++ b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h
> @@ -0,0 +1,63 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef __IRIS_PLATFORM_KAANAPALI_H__
> +#define __IRIS_PLATFORM_KAANAPALI_H__
> +
> +#define VIDEO_REGION_VM0_SECURE_NP_ID 1
> +#define VIDEO_REGION_VM0_NONSECURE_NP_ID 5
> +
> +static const char *const kaanapali_clk_reset_table[] = {
> + "bus0",
> + "bus1",
> + "core_freerun_reset",
> + "vcodec0_core_freerun_reset",
> +};
> +
> +static const char *const kaanapali_pmdomain_table[] = {
> + "venus",
> + "vcodec0",
> + "vpp0",
> + "vpp1",
> + "apv",
> +};
> +
> +static const struct platform_clk_data kaanapali_clk_table[] = {
> + { IRIS_AXI_CLK, "iface" },
> + { IRIS_CTRL_CLK, "core" },
> + { IRIS_HW_CLK, "vcodec0_core" },
> + { IRIS_AXI1_CLK, "iface1" },
> + { IRIS_CTRL_FREERUN_CLK, "core_freerun" },
> + { IRIS_HW_FREERUN_CLK, "vcodec0_core_freerun" },
> + { IRIS_BSE_HW_CLK, "vcodec_bse" },
> + { IRIS_VPP0_HW_CLK, "vcodec_vpp0" },
> + { IRIS_VPP1_HW_CLK, "vcodec_vpp1" },
> + { IRIS_APV_HW_CLK, "vcodec_apv" },
> +};
> +
> +static const char *const kaanapali_opp_clk_table[] = {
> + "vcodec0_core",
> + "vcodec_apv",
> + "vcodec_bse",
> + "core",
> + NULL,
> +};
Why are mxc and mmcx absett from this table ?
---
bod
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH 8/8] media: iris: Add platform data for kaanapali
2025-10-02 15:29 ` Bryan O'Donoghue
@ 2025-10-18 6:55 ` Vishnu Reddy
0 siblings, 0 replies; 54+ messages in thread
From: Vishnu Reddy @ 2025-10-18 6:55 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel
On 10/2/2025 8:59 PM, Bryan O'Donoghue wrote:
> On 25/09/2025 00:14, Vikash Garodia wrote:
>> Add support for the kaanapali platform by re-using the SM8550
>> definitions and using the vpu4 ops.
>> Move the configurations that differs in a per-SoC platform
>> header, that will contain SoC specific data.
>>
>> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
>> ---
>> .../platform/qcom/iris/iris_platform_common.h | 1 +
>> .../media/platform/qcom/iris/iris_platform_gen2.c | 86
>> ++++++++++++++++++++++
>> .../platform/qcom/iris/iris_platform_kaanapali.h | 63
>> ++++++++++++++++
>> drivers/media/platform/qcom/iris/iris_probe.c | 4 +
>> 4 files changed, 154 insertions(+)
>>
>> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h
>> b/drivers/media/platform/qcom/iris/iris_platform_common.h
>> index
>> d6d4a9fdfc189797f903dfeb56d931741b405ee2..465943db0c6671e9b564b40e31ce6ba2d645a84c 100644
>> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
>> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
>> @@ -46,6 +46,7 @@ extern struct iris_platform_data sm8250_data;
>> extern struct iris_platform_data sm8550_data;
>> extern struct iris_platform_data sm8650_data;
>> extern struct iris_platform_data sm8750_data;
>> +extern struct iris_platform_data kaanapali_data;
>>
>> enum platform_clk_type {
>> IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI
>> clocks */
>> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
>> b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
>> index
>> 00c6b9021b98aac80612b1bb9734c8dac8146bd9..142b7d84ee00a9b65420158ac1f168515b56f4a3 100644
>> --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
>> +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
>> @@ -15,6 +15,7 @@
>> #include "iris_platform_qcs8300.h"
>> #include "iris_platform_sm8650.h"
>> #include "iris_platform_sm8750.h"
>> +#include "iris_platform_kaanapali.h"
>>
>> #define VIDEO_ARCH_LX 1
>> #define BITRATE_MAX 245000000
>> @@ -1095,3 +1096,88 @@ struct iris_platform_data qcs8300_data = {
>> .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
>> .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
>> };
>> +
>> +struct iris_platform_data kaanapali_data = {
>> + .get_instance = iris_hfi_gen2_get_instance,
>> + .init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
>> + .init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
>> + .get_vpu_buffer_size = iris_vpu4x_buf_size,
>> + .vpu_ops = &iris_vpu4x_ops,
>> + .set_preset_registers = iris_set_sm8550_preset_registers,
>> + .icc_tbl = sm8550_icc_table,
>> + .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
>> + .clk_rst_tbl = kaanapali_clk_reset_table,
>> + .clk_rst_tbl_size = ARRAY_SIZE(kaanapali_clk_reset_table),
>> + .bw_tbl_dec = sm8550_bw_table_dec,
>> + .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
>> + .pmdomain_tbl = kaanapali_pmdomain_table,
>> + .pmdomain_tbl_size = ARRAY_SIZE(kaanapali_pmdomain_table),
>> + .opp_pd_tbl = sm8550_opp_pd_table,
>> + .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
>> + .clk_tbl = kaanapali_clk_table,
>> + .clk_tbl_size = ARRAY_SIZE(kaanapali_clk_table),
>> + .opp_clk_tbl = kaanapali_opp_clk_table,
>> + /* Upper bound of DMA address range */
>> + .dma_mask = 0xe0000000 - 1,
>> + .fwname = "qcom/vpu/vpu40_p2.mbn",
>> + .pas_id = IRIS_PAS_ID,
>> + .inst_caps = &platform_inst_cap_sm8550,
>> + .inst_fw_caps_dec = inst_fw_cap_sm8550_dec,
>> + .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
>> + .inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
>> + .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
>> + .tz_cp_config_data = tz_cp_config_kaanapali,
>> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_kaanapali),
>> + .core_arch = VIDEO_ARCH_LX,
>> + .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
>> + .ubwc_config = &ubwc_config_sm8550,
>> + .num_vpp_pipe = 2,
>> + .max_session_count = 16,
>> + .max_core_mbpf = NUM_MBS_8K * 2,
>> + .max_core_mbps = ((8192 * 4352) / 256) * 60,
>> + .dec_input_config_params_default =
>> + sm8550_vdec_input_config_params_default,
>> + .dec_input_config_params_default_size =
>> + ARRAY_SIZE(sm8550_vdec_input_config_params_default),
>> + .dec_input_config_params_hevc =
>> + sm8550_vdec_input_config_param_hevc,
>> + .dec_input_config_params_hevc_size =
>> + ARRAY_SIZE(sm8550_vdec_input_config_param_hevc),
>> + .dec_input_config_params_vp9 =
>> + sm8550_vdec_input_config_param_vp9,
>> + .dec_input_config_params_vp9_size =
>> + ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
>> + .dec_output_config_params =
>> + sm8550_vdec_output_config_params,
>> + .dec_output_config_params_size =
>> + ARRAY_SIZE(sm8550_vdec_output_config_params),
>> +
>> + .enc_input_config_params =
>> + sm8550_venc_input_config_params,
>> + .enc_input_config_params_size =
>> + ARRAY_SIZE(sm8550_venc_input_config_params),
>> + .enc_output_config_params =
>> + sm8550_venc_output_config_params,
>> + .enc_output_config_params_size =
>> + ARRAY_SIZE(sm8550_venc_output_config_params),
>> +
>> + .dec_input_prop = sm8550_vdec_subscribe_input_properties,
>> + .dec_input_prop_size =
>> ARRAY_SIZE(sm8550_vdec_subscribe_input_properties),
>> + .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc,
>> + .dec_output_prop_avc_size =
>> + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc),
>> + .dec_output_prop_hevc =
>> sm8550_vdec_subscribe_output_properties_hevc,
>> + .dec_output_prop_hevc_size =
>> + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc),
>> + .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
>> + .dec_output_prop_vp9_size =
>> + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
>> +
>> + .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
>> + .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),
>> + .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,
>> + .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),
>> +
>> + .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
>> + .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
>> +};
>> diff --git
>> a/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h
>> b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h
>> new file mode 100644
>> index
>> 0000000000000000000000000000000000000000..247fb9d7cb632d2e9a1e9832d087cb03ac9b7cf3
>> --- /dev/null
>> +++ b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h
>> @@ -0,0 +1,63 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/*
>> + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights
>> reserved.
>> + */
>> +
>> +#ifndef __IRIS_PLATFORM_KAANAPALI_H__
>> +#define __IRIS_PLATFORM_KAANAPALI_H__
>> +
>> +#define VIDEO_REGION_VM0_SECURE_NP_ID 1
>> +#define VIDEO_REGION_VM0_NONSECURE_NP_ID 5
>> +
>> +static const char *const kaanapali_clk_reset_table[] = {
>> + "bus0",
>> + "bus1",
>> + "core_freerun_reset",
>> + "vcodec0_core_freerun_reset",
>> +};
>> +
>> +static const char *const kaanapali_pmdomain_table[] = {
>> + "venus",
>> + "vcodec0",
>> + "vpp0",
>> + "vpp1",
>> + "apv",
>> +};
>> +
>> +static const struct platform_clk_data kaanapali_clk_table[] = {
>> + { IRIS_AXI_CLK, "iface" },
>> + { IRIS_CTRL_CLK, "core" },
>> + { IRIS_HW_CLK, "vcodec0_core" },
>> + { IRIS_AXI1_CLK, "iface1" },
>> + { IRIS_CTRL_FREERUN_CLK, "core_freerun" },
>> + { IRIS_HW_FREERUN_CLK, "vcodec0_core_freerun" },
>> + { IRIS_BSE_HW_CLK, "vcodec_bse" },
>> + { IRIS_VPP0_HW_CLK, "vcodec_vpp0" },
>> + { IRIS_VPP1_HW_CLK, "vcodec_vpp1" },
>> + { IRIS_APV_HW_CLK, "vcodec_apv" },
>> +};
>> +
>> +static const char *const kaanapali_opp_clk_table[] = {
>> + "vcodec0_core",
>> + "vcodec_apv",
>> + "vcodec_bse",
>> + "core",
>> + NULL,
>> +};
>
> Why are mxc and mmcx absett from this table ?
>
> ---
> bod
mxc and mmcx OPP power domains listed in opp_pd_table
(sm8550_opp_pd_table in iris_platform_gen2.c). This opp_pd_tbl list
attached with PD_FLAG_DEV_LINK_ON | PD_FLAG_REQUIRED_OPP when calling
devm_pm_domain_attach_list, while pmdomain_tbl list will be attached
with PD_FLAG_NO_DEV_LINK flag.
Regards,
Vishnu Reddy
^ permalink raw reply [flat|nested] 54+ messages in thread