* [PATCH v6 0/4] initial clock support for exynosauto v920 SoC [not found] <CGME20240819052422epcas2p27acdb1fd7154984cfebe54506bcaac65@epcas2p2.samsung.com> @ 2024-08-19 5:24 ` Sunyeal Hong [not found] ` <CGME20240819052422epcas2p4db394defd5f298658f7841af3649ac6f@epcas2p4.samsung.com> ` (3 more replies) 0 siblings, 4 replies; 17+ messages in thread From: Sunyeal Hong @ 2024-08-19 5:24 UTC (permalink / raw) To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Conor Dooley Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, Sunyeal Hong This patchset adds initial clock driver support for Exynos Auto v920 SoC. This driver uses HW Auto Clock gating. So all gate clocks did not register. Below CMU blocks are supported in this patchset and remains will be implemented later. - CMU_TOP - CMU_PERIC0 Changes in v6: - Add peric1, mis and hsi0/1 in the bindings document Changes in v5: - Change CMU_TOP odd numbering - Move the descriptions and names common clocks properties Changes in v4: - Change PLL_531x fdiv type and mask bit - Change PLL_531x mdiv type Changes in v3: - Change SoC name from Exynos Auto to ExynosAuto - Change the makefile order to the bottom of exynosautov9 - Add PLL_531x formula for integer PLL Changes in v2: - Fix typo from v209 to v920 - Change USI clock to appropriate - Merge headers into binding patches - Change clock-name to the recommended name Sunyeal Hong (4): dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings arm64: dts: exynos: add initial CMU clock nodes in ExynosAuto v920 clk: samsung: clk-pll: Add support for pll_531x clk: samsung: add top clock support for ExynosAuto v920 SoC .../clock/samsung,exynosautov920-clock.yaml | 197 +++ .../arm64/boot/dts/exynos/exynosautov920.dtsi | 40 +- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynosautov920.c | 1173 +++++++++++++++++ drivers/clk/samsung/clk-pll.c | 44 + drivers/clk/samsung/clk-pll.h | 1 + .../clock/samsung,exynosautov920.h | 191 +++ 7 files changed, 1634 insertions(+), 13 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml create mode 100644 drivers/clk/samsung/clk-exynosautov920.c create mode 100644 include/dt-bindings/clock/samsung,exynosautov920.h -- 2.45.2 ^ permalink raw reply [flat|nested] 17+ messages in thread
[parent not found: <CGME20240819052422epcas2p4db394defd5f298658f7841af3649ac6f@epcas2p4.samsung.com>]
* [PATCH v6 1/4] dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings [not found] ` <CGME20240819052422epcas2p4db394defd5f298658f7841af3649ac6f@epcas2p4.samsung.com> @ 2024-08-19 5:24 ` Sunyeal Hong 2024-08-19 8:19 ` Krzysztof Kozlowski 2024-08-20 3:16 ` Alim Akhtar 0 siblings, 2 replies; 17+ messages in thread From: Sunyeal Hong @ 2024-08-19 5:24 UTC (permalink / raw) To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Conor Dooley Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, Sunyeal Hong Add dt-schema for ExynosAuto v920 SoC clock controller. Add device tree clock binding definitions for below CMU blocks. - CMU_TOP - CMU_PERIC0 Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> --- .../clock/samsung,exynosautov920-clock.yaml | 197 ++++++++++++++++++ .../clock/samsung,exynosautov920.h | 191 +++++++++++++++++ 2 files changed, 388 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml create mode 100644 include/dt-bindings/clock/samsung,exynosautov920.h diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml new file mode 100644 index 000000000000..7efb474e57e8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml @@ -0,0 +1,197 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynosautov920-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung ExynosAuto v920 SoC clock controller + +maintainers: + - Sunyeal Hong <sunyeal.hong@samsung.com> + - Chanwoo Choi <cw00.choi@samsung.com> + - Krzysztof Kozlowski <krzk@kernel.org> + - Sylwester Nawrocki <s.nawrocki@samsung.com> + +description: | + ExynosAuto v920 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. Root clocks in that clock tree are + two external clocks:: OSCCLK/XTCXO (38.4 MHz) and RTCCLK/XrtcXTI (32768 Hz). + The external OSCCLK must be defined as fixed-rate clock in dts. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other clocks of function blocks (other CMUs) are usually + derived from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'include/dt-bindings/clock/samsung,exynosautov920.h' header. + +properties: + compatible: + enum: + - samsung,exynosautov920-cmu-top + - samsung,exynosautov920-cmu-peric0 + - samsung,exynosautov920-cmu-peric1 + - samsung,exynosautov920-cmu-misc + - samsung,exynosautov920-cmu-hsi0 + - samsung,exynosautov920-cmu-hsi1 + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynosautov920-cmu-top + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov920-cmu-peric0 + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_PERIC0 NOC clock (from CMU_TOP) + - description: CMU_PERIC0 IP clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: noc + - const: ip + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov920-cmu-peric1 + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_PERIC1 NOC clock (from CMU_TOP) + - description: CMU_PERIC1 IP clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: noc + - const: ip + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov920-cmu-misc + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_MISC NOC clock (from CMU_MISC) + + clock-names: + items: + - const: oscclk + - const: noc + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov920-cmu-hsi0 + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_HSI0 NOC clock (from CMU_HSI0) + + clock-names: + items: + - const: oscclk + - const: noc + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov920-cmu-hsi1 + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_HSI1 NOC clock (from CMU_HSI1) + - description: CMU_HSI1 USBDRD clock (from CMU_HSI1) + - description: CMU_HSI1 MMC_CARD clock (from CMU_HSI1) + + clock-names: + items: + - const: oscclk + - const: noc + - const: usbdrd + - const: mmc_card + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + - reg + +additionalProperties: false + +examples: + # Clock controller node for CMU_PERIC0 + - | + #include <dt-bindings/clock/samsung,exynosautov920.h> + + cmu_peric0: clock-controller@10800000 { + compatible = "samsung,exynosautov920-cmu-peric0"; + reg = <0x10800000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_PERIC0_NOC>, + <&cmu_top DOUT_CLKCMU_PERIC0_IP>; + clock-names = "oscclk", + "noc", + "ip"; + }; + +... diff --git a/include/dt-bindings/clock/samsung,exynosautov920.h b/include/dt-bindings/clock/samsung,exynosautov920.h new file mode 100644 index 000000000000..c720f344b6bf --- /dev/null +++ b/include/dt-bindings/clock/samsung,exynosautov920.h @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 Samsung Electronics Co., Ltd. + * Author: Sunyeal Hong <sunyeal.hong@samsung.com> + * + * Device Tree binding constants for ExynosAuto v920 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H +#define _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H + +/* CMU_TOP */ +#define FOUT_SHARED0_PLL 1 +#define FOUT_SHARED1_PLL 2 +#define FOUT_SHARED2_PLL 3 +#define FOUT_SHARED3_PLL 4 +#define FOUT_SHARED4_PLL 5 +#define FOUT_SHARED5_PLL 6 +#define FOUT_MMC_PLL 7 + +/* MUX in CMU_TOP */ +#define MOUT_SHARED0_PLL 8 +#define MOUT_SHARED1_PLL 9 +#define MOUT_SHARED2_PLL 10 +#define MOUT_SHARED3_PLL 11 +#define MOUT_SHARED4_PLL 12 +#define MOUT_SHARED5_PLL 13 +#define MOUT_MMC_PLL 14 +#define MOUT_CLKCMU_CMU_BOOST 15 +#define MOUT_CLKCMU_CMU_CMUREF 16 +#define MOUT_CLKCMU_ACC_NOC 17 +#define MOUT_CLKCMU_ACC_ORB 18 +#define MOUT_CLKCMU_APM_NOC 19 +#define MOUT_CLKCMU_AUD_CPU 20 +#define MOUT_CLKCMU_AUD_NOC 21 +#define MOUT_CLKCMU_CPUCL0_SWITCH 22 +#define MOUT_CLKCMU_CPUCL0_CLUSTER 23 +#define MOUT_CLKCMU_CPUCL0_DBG 24 +#define MOUT_CLKCMU_CPUCL1_SWITCH 25 +#define MOUT_CLKCMU_CPUCL1_CLUSTER 26 +#define MOUT_CLKCMU_CPUCL2_SWITCH 27 +#define MOUT_CLKCMU_CPUCL2_CLUSTER 28 +#define MOUT_CLKCMU_DNC_NOC 29 +#define MOUT_CLKCMU_DPTX_NOC 30 +#define MOUT_CLKCMU_DPTX_DPGTC 31 +#define MOUT_CLKCMU_DPTX_DPOSC 32 +#define MOUT_CLKCMU_DPUB_NOC 33 +#define MOUT_CLKCMU_DPUB_DSIM 34 +#define MOUT_CLKCMU_DPUF0_NOC 35 +#define MOUT_CLKCMU_DPUF1_NOC 36 +#define MOUT_CLKCMU_DPUF2_NOC 37 +#define MOUT_CLKCMU_DSP_NOC 38 +#define MOUT_CLKCMU_G3D_SWITCH 39 +#define MOUT_CLKCMU_G3D_NOCP 40 +#define MOUT_CLKCMU_GNPU_NOC 41 +#define MOUT_CLKCMU_HSI0_NOC 42 +#define MOUT_CLKCMU_HSI1_NOC 43 +#define MOUT_CLKCMU_HSI1_USBDRD 44 +#define MOUT_CLKCMU_HSI1_MMC_CARD 45 +#define MOUT_CLKCMU_HSI2_NOC 46 +#define MOUT_CLKCMU_HSI2_NOC_UFS 47 +#define MOUT_CLKCMU_HSI2_UFS_EMBD 48 +#define MOUT_CLKCMU_HSI2_ETHERNET 49 +#define MOUT_CLKCMU_ISP_NOC 50 +#define MOUT_CLKCMU_M2M_NOC 51 +#define MOUT_CLKCMU_M2M_JPEG 52 +#define MOUT_CLKCMU_MFC_MFC 53 +#define MOUT_CLKCMU_MFC_WFD 54 +#define MOUT_CLKCMU_MFD_NOC 55 +#define MOUT_CLKCMU_MIF_SWITCH 56 +#define MOUT_CLKCMU_MIF_NOCP 57 +#define MOUT_CLKCMU_MISC_NOC 58 +#define MOUT_CLKCMU_NOCL0_NOC 59 +#define MOUT_CLKCMU_NOCL1_NOC 60 +#define MOUT_CLKCMU_NOCL2_NOC 61 +#define MOUT_CLKCMU_PERIC0_NOC 62 +#define MOUT_CLKCMU_PERIC0_IP 63 +#define MOUT_CLKCMU_PERIC1_NOC 64 +#define MOUT_CLKCMU_PERIC1_IP 65 +#define MOUT_CLKCMU_SDMA_NOC 66 +#define MOUT_CLKCMU_SNW_NOC 67 +#define MOUT_CLKCMU_SSP_NOC 68 +#define MOUT_CLKCMU_TAA_NOC 69 + +/* DIV in CMU_TOP */ +#define DOUT_SHARED0_DIV1 70 +#define DOUT_SHARED0_DIV2 71 +#define DOUT_SHARED0_DIV3 72 +#define DOUT_SHARED0_DIV4 73 +#define DOUT_SHARED1_DIV1 74 +#define DOUT_SHARED1_DIV2 75 +#define DOUT_SHARED1_DIV3 76 +#define DOUT_SHARED1_DIV4 77 +#define DOUT_SHARED2_DIV1 78 +#define DOUT_SHARED2_DIV2 79 +#define DOUT_SHARED2_DIV3 80 +#define DOUT_SHARED2_DIV4 81 +#define DOUT_SHARED3_DIV1 82 +#define DOUT_SHARED3_DIV2 83 +#define DOUT_SHARED3_DIV3 84 +#define DOUT_SHARED3_DIV4 85 +#define DOUT_SHARED4_DIV1 86 +#define DOUT_SHARED4_DIV2 87 +#define DOUT_SHARED4_DIV3 88 +#define DOUT_SHARED4_DIV4 89 +#define DOUT_SHARED5_DIV1 90 +#define DOUT_SHARED5_DIV2 91 +#define DOUT_SHARED5_DIV3 92 +#define DOUT_SHARED5_DIV4 93 +#define DOUT_CLKCMU_CMU_BOOST 94 +#define DOUT_CLKCMU_ACC_NOC 95 +#define DOUT_CLKCMU_ACC_ORB 96 +#define DOUT_CLKCMU_APM_NOC 97 +#define DOUT_CLKCMU_AUD_CPU 98 +#define DOUT_CLKCMU_AUD_NOC 99 +#define DOUT_CLKCMU_CPUCL0_SWITCH 100 +#define DOUT_CLKCMU_CPUCL0_CLUSTER 101 +#define DOUT_CLKCMU_CPUCL0_DBG 102 +#define DOUT_CLKCMU_CPUCL1_SWITCH 103 +#define DOUT_CLKCMU_CPUCL1_CLUSTER 104 +#define DOUT_CLKCMU_CPUCL2_SWITCH 105 +#define DOUT_CLKCMU_CPUCL2_CLUSTER 106 +#define DOUT_CLKCMU_DNC_NOC 107 +#define DOUT_CLKCMU_DPTX_NOC 108 +#define DOUT_CLKCMU_DPTX_DPGTC 109 +#define DOUT_CLKCMU_DPTX_DPOSC 110 +#define DOUT_CLKCMU_DPUB_NOC 111 +#define DOUT_CLKCMU_DPUB_DSIM 112 +#define DOUT_CLKCMU_DPUF0_NOC 113 +#define DOUT_CLKCMU_DPUF1_NOC 114 +#define DOUT_CLKCMU_DPUF2_NOC 115 +#define DOUT_CLKCMU_DSP_NOC 116 +#define DOUT_CLKCMU_G3D_SWITCH 117 +#define DOUT_CLKCMU_G3D_NOCP 118 +#define DOUT_CLKCMU_GNPU_NOC 119 +#define DOUT_CLKCMU_HSI0_NOC 120 +#define DOUT_CLKCMU_HSI1_NOC 121 +#define DOUT_CLKCMU_HSI1_USBDRD 122 +#define DOUT_CLKCMU_HSI1_MMC_CARD 123 +#define DOUT_CLKCMU_HSI2_NOC 124 +#define DOUT_CLKCMU_HSI2_NOC_UFS 125 +#define DOUT_CLKCMU_HSI2_UFS_EMBD 126 +#define DOUT_CLKCMU_HSI2_ETHERNET 127 +#define DOUT_CLKCMU_ISP_NOC 128 +#define DOUT_CLKCMU_M2M_NOC 129 +#define DOUT_CLKCMU_M2M_JPEG 130 +#define DOUT_CLKCMU_MFC_MFC 131 +#define DOUT_CLKCMU_MFC_WFD 132 +#define DOUT_CLKCMU_MFD_NOC 133 +#define DOUT_CLKCMU_MIF_NOCP 134 +#define DOUT_CLKCMU_MISC_NOC 135 +#define DOUT_CLKCMU_NOCL0_NOC 136 +#define DOUT_CLKCMU_NOCL1_NOC 137 +#define DOUT_CLKCMU_NOCL2_NOC 138 +#define DOUT_CLKCMU_PERIC0_NOC 139 +#define DOUT_CLKCMU_PERIC0_IP 140 +#define DOUT_CLKCMU_PERIC1_NOC 141 +#define DOUT_CLKCMU_PERIC1_IP 142 +#define DOUT_CLKCMU_SDMA_NOC 143 +#define DOUT_CLKCMU_SNW_NOC 144 +#define DOUT_CLKCMU_SSP_NOC 145 +#define DOUT_CLKCMU_TAA_NOC 146 + +/* CMU_PERIC0 */ +#define CLK_MOUT_PERIC0_IP_USER 1 +#define CLK_MOUT_PERIC0_NOC_USER 2 +#define CLK_MOUT_PERIC0_USI00_USI 3 +#define CLK_MOUT_PERIC0_USI01_USI 4 +#define CLK_MOUT_PERIC0_USI02_USI 5 +#define CLK_MOUT_PERIC0_USI03_USI 6 +#define CLK_MOUT_PERIC0_USI04_USI 7 +#define CLK_MOUT_PERIC0_USI05_USI 8 +#define CLK_MOUT_PERIC0_USI06_USI 9 +#define CLK_MOUT_PERIC0_USI07_USI 10 +#define CLK_MOUT_PERIC0_USI08_USI 11 +#define CLK_MOUT_PERIC0_USI_I2C 12 +#define CLK_MOUT_PERIC0_I3C 13 + +#define CLK_DOUT_PERIC0_USI00_USI 14 +#define CLK_DOUT_PERIC0_USI01_USI 15 +#define CLK_DOUT_PERIC0_USI02_USI 16 +#define CLK_DOUT_PERIC0_USI03_USI 17 +#define CLK_DOUT_PERIC0_USI04_USI 18 +#define CLK_DOUT_PERIC0_USI05_USI 19 +#define CLK_DOUT_PERIC0_USI06_USI 20 +#define CLK_DOUT_PERIC0_USI07_USI 21 +#define CLK_DOUT_PERIC0_USI08_USI 22 +#define CLK_DOUT_PERIC0_USI_I2C 23 +#define CLK_DOUT_PERIC0_I3C 24 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */ -- 2.45.2 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v6 1/4] dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings 2024-08-19 5:24 ` [PATCH v6 1/4] dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings Sunyeal Hong @ 2024-08-19 8:19 ` Krzysztof Kozlowski 2024-08-20 1:46 ` sunyeal.hong 2024-08-20 3:16 ` Alim Akhtar 1 sibling, 1 reply; 17+ messages in thread From: Krzysztof Kozlowski @ 2024-08-19 8:19 UTC (permalink / raw) To: Sunyeal Hong Cc: Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Conor Dooley, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On Mon, Aug 19, 2024 at 02:24:12PM +0900, Sunyeal Hong wrote: > Add dt-schema for ExynosAuto v920 SoC clock controller. > Add device tree clock binding definitions for below CMU blocks. > > - CMU_TOP > - CMU_PERIC0 > > Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> + then: > + properties: > + clocks: > + items: > + - description: External reference clock (38.4 MHz) > + - description: CMU_PERIC0 NOC clock (from CMU_TOP) > + - description: CMU_PERIC0 IP clock (from CMU_TOP) > + > + clock-names: > + items: > + - const: oscclk > + - const: noc > + - const: ip > + > + - if: > + properties: > + compatible: > + contains: > + const: samsung,exynosautov920-cmu-peric1 > + > + then: > + properties: > + clocks: > + items: > + - description: External reference clock (38.4 MHz) > + - description: CMU_PERIC1 NOC clock (from CMU_TOP) > + - description: CMU_PERIC1 IP clock (from CMU_TOP) > + > + clock-names: > + items: > + - const: oscclk > + - const: noc > + - const: ip This is the same peric0, so combine them and clocks could be just: items: - description: External reference clock (38.4 MHz) - description: CMU_PERICn NOC clock (from CMU_TOP) - description: CMU_PERICn IP clock (from CMU_TOP) > + > + - if: > + properties: > + compatible: > + contains: > + const: samsung,exynosautov920-cmu-misc > + > + then: > + properties: > + clocks: > + items: > + - description: External reference clock (38.4 MHz) > + - description: CMU_MISC NOC clock (from CMU_MISC) Similarly: - description: CMU_MISC/CMU_HSI0 NOC clock (from CMU_MISC) ^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: [PATCH v6 1/4] dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings 2024-08-19 8:19 ` Krzysztof Kozlowski @ 2024-08-20 1:46 ` sunyeal.hong 0 siblings, 0 replies; 17+ messages in thread From: sunyeal.hong @ 2024-08-20 1:46 UTC (permalink / raw) To: 'Krzysztof Kozlowski' Cc: 'Sylwester Nawrocki', 'Chanwoo Choi', 'Alim Akhtar', 'Michael Turquette', 'Stephen Boyd', 'Rob Herring', 'Conor Dooley', linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel Hello Krzysztof, > -----Original Message----- > From: Krzysztof Kozlowski <krzk@kernel.org> > Sent: Monday, August 19, 2024 5:20 PM > To: Sunyeal Hong <sunyeal.hong@samsung.com> > Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>; Chanwoo Choi > <cw00.choi@samsung.com>; Alim Akhtar <alim.akhtar@samsung.com>; Michael > Turquette <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob > Herring <robh@kernel.org>; Conor Dooley <conor+dt@kernel.org>; linux- > samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org > Subject: Re: [PATCH v6 1/4] dt-bindings: clock: add ExynosAuto v920 SoC > CMU bindings > > On Mon, Aug 19, 2024 at 02:24:12PM +0900, Sunyeal Hong wrote: > > Add dt-schema for ExynosAuto v920 SoC clock controller. > > Add device tree clock binding definitions for below CMU blocks. > > > > - CMU_TOP > > - CMU_PERIC0 > > > > Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> > + then: > > + properties: > > + clocks: > > + items: > > + - description: External reference clock (38.4 MHz) > > + - description: CMU_PERIC0 NOC clock (from CMU_TOP) > > + - description: CMU_PERIC0 IP clock (from CMU_TOP) > > + > > + clock-names: > > + items: > > + - const: oscclk > > + - const: noc > > + - const: ip > > + > > + - if: > > + properties: > > + compatible: > > + contains: > > + const: samsung,exynosautov920-cmu-peric1 > > + > > + then: > > + properties: > > + clocks: > > + items: > > + - description: External reference clock (38.4 MHz) > > + - description: CMU_PERIC1 NOC clock (from CMU_TOP) > > + - description: CMU_PERIC1 IP clock (from CMU_TOP) > > + > > + clock-names: > > + items: > > + - const: oscclk > > + - const: noc > > + - const: ip > > This is the same peric0, so combine them and clocks could be just: > > items: > - description: External reference clock (38.4 MHz) > - description: CMU_PERICn NOC clock (from CMU_TOP) > - description: CMU_PERICn IP clock (from CMU_TOP) > As you reviewed, I will remove the duplicates. > > + > > + - if: > > + properties: > > + compatible: > > + contains: > > + const: samsung,exynosautov920-cmu-misc > > + > > + then: > > + properties: > > + clocks: > > + items: > > + - description: External reference clock (38.4 MHz) > > + - description: CMU_MISC NOC clock (from CMU_MISC) > > Similarly: > > - description: CMU_MISC/CMU_HSI0 NOC clock (from CMU_MISC) Best Regards, sunyeal ^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: [PATCH v6 1/4] dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings 2024-08-19 5:24 ` [PATCH v6 1/4] dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings Sunyeal Hong 2024-08-19 8:19 ` Krzysztof Kozlowski @ 2024-08-20 3:16 ` Alim Akhtar 2024-08-20 7:43 ` sunyeal.hong 1 sibling, 1 reply; 17+ messages in thread From: Alim Akhtar @ 2024-08-20 3:16 UTC (permalink / raw) To: 'Sunyeal Hong', 'Krzysztof Kozlowski', 'Sylwester Nawrocki', 'Chanwoo Choi', 'Michael Turquette', 'Stephen Boyd', 'Rob Herring', 'Conor Dooley' Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel Hi Sunyeal, > -----Original Message----- > From: Sunyeal Hong <sunyeal.hong@samsung.com> > Sent: Monday, August 19, 2024 10:54 AM > To: Krzysztof Kozlowski <krzk@kernel.org>; Sylwester Nawrocki > <s.nawrocki@samsung.com>; Chanwoo Choi <cw00.choi@samsung.com>; > Alim Akhtar <alim.akhtar@samsung.com>; Michael Turquette > <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob > Herring <robh@kernel.org>; Conor Dooley <conor+dt@kernel.org> > Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org; Sunyeal Hong <sunyeal.hong@samsung.com> > Subject: [PATCH v6 1/4] dt-bindings: clock: add ExynosAuto v920 SoC CMU > bindings > > Add dt-schema for ExynosAuto v920 SoC clock controller. > Add device tree clock binding definitions for below CMU blocks. > > - CMU_TOP > - CMU_PERIC0 > Do update the commit message to match with the changes in this patch Thanks > Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> > --- > .../clock/samsung,exynosautov920-clock.yaml | 197 ++++++++++++++++++ > .../clock/samsung,exynosautov920.h | 191 +++++++++++++++++ > 2 files changed, 388 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/clock/samsung,exynosautov920- > clock.yaml > create mode 100644 include/dt-bindings/clock/samsung,exynosautov920.h > [snip] > diff --git > > + - samsung,exynosautov920-cmu-top > + - samsung,exynosautov920-cmu-peric0 > + - samsung,exynosautov920-cmu-peric1 > + - samsung,exynosautov920-cmu-misc > + - samsung,exynosautov920-cmu-hsi0 > + - samsung,exynosautov920-cmu-hsi1 > + [snip] > +#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */ > -- > 2.45.2 ^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: [PATCH v6 1/4] dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings 2024-08-20 3:16 ` Alim Akhtar @ 2024-08-20 7:43 ` sunyeal.hong 0 siblings, 0 replies; 17+ messages in thread From: sunyeal.hong @ 2024-08-20 7:43 UTC (permalink / raw) To: 'Alim Akhtar', 'Krzysztof Kozlowski', 'Sylwester Nawrocki', 'Chanwoo Choi', 'Michael Turquette', 'Stephen Boyd', 'Rob Herring', 'Conor Dooley' Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel Hello Alim, > -----Original Message----- > From: Alim Akhtar <alim.akhtar@samsung.com> > Sent: Tuesday, August 20, 2024 12:17 PM > To: 'Sunyeal Hong' <sunyeal.hong@samsung.com>; 'Krzysztof Kozlowski' > <krzk@kernel.org>; 'Sylwester Nawrocki' <s.nawrocki@samsung.com>; 'Chanwoo > Choi' <cw00.choi@samsung.com>; 'Michael Turquette' > <mturquette@baylibre.com>; 'Stephen Boyd' <sboyd@kernel.org>; 'Rob > Herring' <robh@kernel.org>; 'Conor Dooley' <conor+dt@kernel.org> > Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org > Subject: RE: [PATCH v6 1/4] dt-bindings: clock: add ExynosAuto v920 SoC > CMU bindings > > Hi Sunyeal, > > > -----Original Message----- > > From: Sunyeal Hong <sunyeal.hong@samsung.com> > > Sent: Monday, August 19, 2024 10:54 AM > > To: Krzysztof Kozlowski <krzk@kernel.org>; Sylwester Nawrocki > > <s.nawrocki@samsung.com>; Chanwoo Choi <cw00.choi@samsung.com>; Alim > > Akhtar <alim.akhtar@samsung.com>; Michael Turquette > > <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob > > Herring <robh@kernel.org>; Conor Dooley <conor+dt@kernel.org> > > Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; > > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > > linux- kernel@vger.kernel.org; Sunyeal Hong <sunyeal.hong@samsung.com> > > Subject: [PATCH v6 1/4] dt-bindings: clock: add ExynosAuto v920 SoC > > CMU bindings > > > > Add dt-schema for ExynosAuto v920 SoC clock controller. > > Add device tree clock binding definitions for below CMU blocks. > > > > - CMU_TOP > > - CMU_PERIC0 > > > Do update the commit message to match with the changes in this patch > Thanks > Okay... I'll update this, too. Thanks > > Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> > > --- > > .../clock/samsung,exynosautov920-clock.yaml | 197 ++++++++++++++++++ > > .../clock/samsung,exynosautov920.h | 191 +++++++++++++++++ > > 2 files changed, 388 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/clock/samsung,exynosautov920- > > clock.yaml > > create mode 100644 include/dt-bindings/clock/samsung,exynosautov920.h > > > [snip] > > > diff --git > > > > + - samsung,exynosautov920-cmu-top > > + - samsung,exynosautov920-cmu-peric0 > > + - samsung,exynosautov920-cmu-peric1 > > + - samsung,exynosautov920-cmu-misc > > + - samsung,exynosautov920-cmu-hsi0 > > + - samsung,exynosautov920-cmu-hsi1 > > + > [snip] > > > +#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */ > > -- > > 2.45.2 > ^ permalink raw reply [flat|nested] 17+ messages in thread
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* [PATCH v6 2/4] arm64: dts: exynos: add initial CMU clock nodes in ExynosAuto v920 [not found] ` <CGME20240819052422epcas2p4f2ee384824a64e1b6f074de972ab3ffc@epcas2p4.samsung.com> @ 2024-08-19 5:24 ` Sunyeal Hong 0 siblings, 0 replies; 17+ messages in thread From: Sunyeal Hong @ 2024-08-19 5:24 UTC (permalink / raw) To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Conor Dooley Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, Sunyeal Hong Add cmu_top, cmu_peric0 clock nodes and switch USI clocks instead of dummy fixed-rate-clock. Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> --- .../arm64/boot/dts/exynos/exynosautov920.dtsi | 40 +++++++++++++------ 1 file changed, 27 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index c1c8566d74f5..91882b37fdb3 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -6,6 +6,7 @@ * */ +#include <dt-bindings/clock/samsung,exynosautov920.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/soc/samsung,exynos-usi.h> @@ -38,17 +39,6 @@ xtcxo: clock { clock-output-names = "oscclk"; }; - /* - * FIXME: Keep the stub clock for serial driver, until proper clock - * driver is implemented. - */ - clock_usi: clock-usi { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - clock-output-names = "usi"; - }; - cpus: cpus { #address-cells = <2>; #size-cells = <0>; @@ -192,6 +182,19 @@ gic: interrupt-controller@10400000 { interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; + cmu_peric0: clock-controller@10800000 { + compatible = "samsung,exynosautov920-cmu-peric0"; + reg = <0x10800000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_PERIC0_NOC>, + <&cmu_top DOUT_CLKCMU_PERIC0_IP>; + clock-names = "oscclk", + "noc", + "ip"; + }; + syscon_peric0: syscon@10820000 { compatible = "samsung,exynosautov920-peric0-sysreg", "syscon"; @@ -213,7 +216,8 @@ usi_0: usi@108800c0 { #address-cells = <1>; #size-cells = <1>; ranges; - clocks = <&clock_usi>, <&clock_usi>; + clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>; clock-names = "pclk", "ipclk"; status = "disabled"; @@ -224,7 +228,8 @@ serial_0: serial@10880000 { interrupts = <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&uart0_bus>; - clocks = <&clock_usi>, <&clock_usi>; + clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <256>; status = "disabled"; @@ -254,6 +259,15 @@ pinctrl_peric1: pinctrl@10c30000 { interrupts = <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>; }; + cmu_top: clock-controller@11000000 { + compatible = "samsung,exynosautov920-cmu-top"; + reg = <0x11000000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>; + clock-names = "oscclk"; + }; + pinctrl_alive: pinctrl@11850000 { compatible = "samsung,exynosautov920-pinctrl"; reg = <0x11850000 0x10000>; -- 2.45.2 ^ permalink raw reply related [flat|nested] 17+ messages in thread
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* [PATCH v6 3/4] clk: samsung: clk-pll: Add support for pll_531x [not found] ` <CGME20240819052422epcas2p3f7ae25b479f54f2402ffd11a0942937d@epcas2p3.samsung.com> @ 2024-08-19 5:24 ` Sunyeal Hong 0 siblings, 0 replies; 17+ messages in thread From: Sunyeal Hong @ 2024-08-19 5:24 UTC (permalink / raw) To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Conor Dooley Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, Sunyeal Hong pll531x PLL is used in Exynos Auto v920 SoC for shared pll. pll531x: Integer/fractional PLL with mid frequency FVCO (800 to 3120 MHz) PLL531x FOUT = (MDIV x FIN)/(PDIV x 2^SDIV) for integer PLL FOUT = (MDIV + F/2^32-F[31]) x FIN/(PDIV x 2^SDIV) for fractional PLL Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> --- drivers/clk/samsung/clk-pll.c | 44 +++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-pll.h | 1 + 2 files changed, 45 insertions(+) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 4be879ab917e..a6c81075417a 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -1261,6 +1261,47 @@ static const struct clk_ops samsung_pll2650xx_clk_min_ops = { .recalc_rate = samsung_pll2650xx_recalc_rate, }; +/* + * PLL531X Clock Type + */ +/* Maximum lock time can be 500 * PDIV cycles */ +#define PLL531X_LOCK_FACTOR (500) +#define PLL531X_MDIV_MASK (0x3FF) +#define PLL531X_PDIV_MASK (0x3F) +#define PLL531X_SDIV_MASK (0x7) +#define PLL531X_FDIV_MASK (0xFFFFFFFF) +#define PLL531X_MDIV_SHIFT (16) +#define PLL531X_PDIV_SHIFT (8) +#define PLL531X_SDIV_SHIFT (0) + +static unsigned long samsung_pll531x_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 pdiv, sdiv, fdiv, pll_con0, pll_con8; + u64 mdiv, fout = parent_rate; + + pll_con0 = readl_relaxed(pll->con_reg); + pll_con8 = readl_relaxed(pll->con_reg + 20); + mdiv = (pll_con0 >> PLL531X_MDIV_SHIFT) & PLL531X_MDIV_MASK; + pdiv = (pll_con0 >> PLL531X_PDIV_SHIFT) & PLL531X_PDIV_MASK; + sdiv = (pll_con0 >> PLL531X_SDIV_SHIFT) & PLL531X_SDIV_MASK; + fdiv = (pll_con8 & PLL531X_FDIV_MASK); + + if (fdiv >> 31) + mdiv--; + + fout *= (mdiv << 24) + (fdiv >> 8); + do_div(fout, (pdiv << sdiv)); + fout >>= 24; + + return (unsigned long)fout; +} + +static const struct clk_ops samsung_pll531x_clk_ops = { + .recalc_rate = samsung_pll531x_recalc_rate, +}; + static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, const struct samsung_pll_clock *pll_clk) { @@ -1394,6 +1435,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, else init.ops = &samsung_pll2650xx_clk_ops; break; + case pll_531x: + init.ops = &samsung_pll531x_clk_ops; + break; default: pr_warn("%s: Unknown pll type for pll clk %s\n", __func__, pll_clk->name); diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index ffd3d52c0dec..ce9d6f21f993 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -41,6 +41,7 @@ enum samsung_pll_type { pll_0516x, pll_0517x, pll_0518x, + pll_531x, }; #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \ -- 2.45.2 ^ permalink raw reply related [flat|nested] 17+ messages in thread
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* [PATCH v6 4/4] clk: samsung: add top clock support for ExynosAuto v920 SoC [not found] ` <CGME20240819052422epcas2p258a29e773ebdd60573078c21f7a7da12@epcas2p2.samsung.com> @ 2024-08-19 5:24 ` Sunyeal Hong 2024-08-19 9:32 ` Kwanghoon Son 0 siblings, 1 reply; 17+ messages in thread From: Sunyeal Hong @ 2024-08-19 5:24 UTC (permalink / raw) To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Conor Dooley Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, Sunyeal Hong This adds support for CMU_TOP which generates clocks for all the function blocks such as CORE, HSI0/1/2, PERIC0/1 and so on. For CMU_TOP, PLL_SHARED0,1,2,3,4 and 5 will be the sources of this block and they will generate bus clocks. Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> --- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynosautov920.c | 1173 ++++++++++++++++++++++ 2 files changed, 1174 insertions(+) create mode 100644 drivers/clk/samsung/clk-exynosautov920.c diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 3056944a5a54..f1ba48758c78 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov920.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o diff --git a/drivers/clk/samsung/clk-exynosautov920.c b/drivers/clk/samsung/clk-exynosautov920.c new file mode 100644 index 000000000000..c17d25e3c9a0 --- /dev/null +++ b/drivers/clk/samsung/clk-exynosautov920.c @@ -0,0 +1,1173 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 Samsung Electronics Co., Ltd. + * Author: Sunyeal Hong <sunyeal.hong@samsung.com> + * + * Common Clock Framework support for ExynosAuto v920 SoC. + */ + +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include <dt-bindings/clock/samsung,exynosautov920.h> + +#include "clk.h" +#include "clk-exynos-arm64.h" + +/* NOTE: Must be equal to the last clock ID increased by one */ +#define CLKS_NR_TOP (DOUT_CLKCMU_TAA_NOC + 1) +#define CLKS_NR_PERIC0 (CLK_DOUT_PERIC0_I3C + 1) + +/* ---- CMU_TOP ------------------------------------------------------------ */ + +/* Register Offset definitions for CMU_TOP (0x11000000) */ +#define PLL_LOCKTIME_PLL_MMC 0x0004 +#define PLL_LOCKTIME_PLL_SHARED0 0x0008 +#define PLL_LOCKTIME_PLL_SHARED1 0x000c +#define PLL_LOCKTIME_PLL_SHARED2 0x0010 +#define PLL_LOCKTIME_PLL_SHARED3 0x0014 +#define PLL_LOCKTIME_PLL_SHARED4 0x0018 +#define PLL_LOCKTIME_PLL_SHARED5 0x0018 +#define PLL_CON0_PLL_MMC 0x0140 +#define PLL_CON3_PLL_MMC 0x014c +#define PLL_CON0_PLL_SHARED0 0x0180 +#define PLL_CON3_PLL_SHARED0 0x018c +#define PLL_CON0_PLL_SHARED1 0x01c0 +#define PLL_CON3_PLL_SHARED1 0x01cc +#define PLL_CON0_PLL_SHARED2 0x0200 +#define PLL_CON3_PLL_SHARED2 0x020c +#define PLL_CON0_PLL_SHARED3 0x0240 +#define PLL_CON3_PLL_SHARED3 0x024c +#define PLL_CON0_PLL_SHARED4 0x0280 +#define PLL_CON3_PLL_SHARED4 0x028c +#define PLL_CON0_PLL_SHARED5 0x02c0 +#define PLL_CON3_PLL_SHARED5 0x02cc + +/* MUX */ +#define CLK_CON_MUX_MUX_CLKCMU_ACC_NOC 0x1000 +#define CLK_CON_MUX_MUX_CLKCMU_APM_NOC 0x1004 +#define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x1008 +#define CLK_CON_MUX_MUX_CLKCMU_AUD_NOC 0x100c +#define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK0 0x1010 +#define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK1 0x1014 +#define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK2 0x1018 +#define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK3 0x101c +#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1020 +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER 0x1024 +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x1028 +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x102c +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER 0x1030 +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1034 +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_CLUSTER 0x1038 +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x103c +#define CLK_CON_MUX_MUX_CLKCMU_DNC_NOC 0x1040 +#define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC 0x1044 +#define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPOSC 0x1048 +#define CLK_CON_MUX_MUX_CLKCMU_DPTX_NOC 0x104c +#define CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM 0x1050 +#define CLK_CON_MUX_MUX_CLKCMU_DPUB_NOC 0x1054 +#define CLK_CON_MUX_MUX_CLKCMU_DPUF0_NOC 0x1058 +#define CLK_CON_MUX_MUX_CLKCMU_DPUF1_NOC 0x105c +#define CLK_CON_MUX_MUX_CLKCMU_DPUF2_NOC 0x1060 +#define CLK_CON_MUX_MUX_CLKCMU_DSP_NOC 0x1064 +#define CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP 0x1068 +#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x106c +#define CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC 0x1070 +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC 0x1074 +#define CLK_CON_MUX_MUX_CLKCMU_ACC_ORB 0x1078 +#define CLK_CON_MUX_MUX_CLKCMU_GNPU_XMAA 0x107c +#define CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD 0x1080 +#define CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC 0x1084 +#define CLK_CON_MUX_MUX_CLKCMU_HSI1_USBDRD 0x1088 +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_ETHERNET 0x108c +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC 0x1090 +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_UFS 0x1094 +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x1098 +#define CLK_CON_MUX_MUX_CLKCMU_ISP_NOC 0x109c +#define CLK_CON_MUX_MUX_CLKCMU_M2M_JPEG 0x10a0 +#define CLK_CON_MUX_MUX_CLKCMU_M2M_NOC 0x10a4 +#define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10a8 +#define CLK_CON_MUX_MUX_CLKCMU_MFC_WFD 0x10ac +#define CLK_CON_MUX_MUX_CLKCMU_MFD_NOC 0x10b0 +#define CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP 0x10b4 +#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10b8 +#define CLK_CON_MUX_MUX_CLKCMU_MISC_NOC 0x10bc +#define CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC 0x10c0 +#define CLK_CON_MUX_MUX_CLKCMU_NOCL1_NOC 0x10c4 +#define CLK_CON_MUX_MUX_CLKCMU_NOCL2_NOC 0x10c8 +#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10cc +#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC 0x10d0 +#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10d4 +#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC 0x10d8 +#define CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC 0x10dc +#define CLK_CON_MUX_MUX_CLKCMU_SNW_NOC 0x10e0 +#define CLK_CON_MUX_MUX_CLKCMU_SSP_NOC 0x10e4 +#define CLK_CON_MUX_MUX_CLKCMU_TAA_NOC 0x10e8 +#define CLK_CON_MUX_MUX_CLK_CMU_NOCP 0x10ec +#define CLK_CON_MUX_MUX_CLK_CMU_PLLCLKOUT 0x10f0 +#define CLK_CON_MUX_MUX_CMU_CMUREF 0x10f4 + +/* DIV */ +#define CLK_CON_DIV_CLKCMU_ACC_NOC 0x1800 +#define CLK_CON_DIV_CLKCMU_APM_NOC 0x1804 +#define CLK_CON_DIV_CLKCMU_AUD_CPU 0x1808 +#define CLK_CON_DIV_CLKCMU_AUD_NOC 0x180c +#define CLK_CON_DIV_CLKCMU_CIS_MCLK0 0x1810 +#define CLK_CON_DIV_CLKCMU_CIS_MCLK1 0x1814 +#define CLK_CON_DIV_CLKCMU_CIS_MCLK2 0x1818 +#define CLK_CON_DIV_CLKCMU_CIS_MCLK3 0x181c +#define CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER 0x1820 +#define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1824 +#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1828 +#define CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER 0x182c +#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x1830 +#define CLK_CON_DIV_CLKCMU_CPUCL2_CLUSTER 0x1834 +#define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1838 +#define CLK_CON_DIV_CLKCMU_DNC_NOC 0x183c +#define CLK_CON_DIV_CLKCMU_DPTX_DPGTC 0x1840 +#define CLK_CON_DIV_CLKCMU_DPTX_DPOSC 0x1844 +#define CLK_CON_DIV_CLKCMU_DPTX_NOC 0x1848 +#define CLK_CON_DIV_CLKCMU_DPUB_DSIM 0x184c +#define CLK_CON_DIV_CLKCMU_DPUB_NOC 0x1850 +#define CLK_CON_DIV_CLKCMU_DPUF0_NOC 0x1854 +#define CLK_CON_DIV_CLKCMU_DPUF1_NOC 0x1858 +#define CLK_CON_DIV_CLKCMU_DPUF2_NOC 0x185c +#define CLK_CON_DIV_CLKCMU_DSP_NOC 0x1860 +#define CLK_CON_DIV_CLKCMU_G3D_NOCP 0x1864 +#define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1868 +#define CLK_CON_DIV_CLKCMU_GNPU_NOC 0x186c +#define CLK_CON_DIV_CLKCMU_HSI0_NOC 0x1870 +#define CLK_CON_DIV_CLKCMU_ACC_ORB 0x1874 +#define CLK_CON_DIV_CLKCMU_GNPU_XMAA 0x1878 +#define CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD 0x187c +#define CLK_CON_DIV_CLKCMU_HSI1_NOC 0x1880 +#define CLK_CON_DIV_CLKCMU_HSI1_USBDRD 0x1884 +#define CLK_CON_DIV_CLKCMU_HSI2_ETHERNET 0x1888 +#define CLK_CON_DIV_CLKCMU_HSI2_NOC 0x188c +#define CLK_CON_DIV_CLKCMU_HSI2_NOC_UFS 0x1890 +#define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x1894 +#define CLK_CON_DIV_CLKCMU_ISP_NOC 0x1898 +#define CLK_CON_DIV_CLKCMU_M2M_JPEG 0x189c +#define CLK_CON_DIV_CLKCMU_M2M_NOC 0x18a0 +#define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18a4 +#define CLK_CON_DIV_CLKCMU_MFC_WFD 0x18a8 +#define CLK_CON_DIV_CLKCMU_MFD_NOC 0x18ac +#define CLK_CON_DIV_CLKCMU_MIF_NOCP 0x18b0 +#define CLK_CON_DIV_CLKCMU_MISC_NOC 0x18b4 +#define CLK_CON_DIV_CLKCMU_NOCL0_NOC 0x18b8 +#define CLK_CON_DIV_CLKCMU_NOCL1_NOC 0x18bc +#define CLK_CON_DIV_CLKCMU_NOCL2_NOC 0x18c0 +#define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18c4 +#define CLK_CON_DIV_CLKCMU_PERIC0_NOC 0x18c8 +#define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18cc +#define CLK_CON_DIV_CLKCMU_PERIC1_NOC 0x18d0 +#define CLK_CON_DIV_CLKCMU_SDMA_NOC 0x18d4 +#define CLK_CON_DIV_CLKCMU_SNW_NOC 0x18d8 +#define CLK_CON_DIV_CLKCMU_SSP_NOC 0x18dc +#define CLK_CON_DIV_CLKCMU_TAA_NOC 0x18e0 +#define CLK_CON_DIV_CLK_ADD_CH_CLK 0x18e4 +#define CLK_CON_DIV_CLK_CMU_PLLCLKOUT 0x18e8 +#define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18ec +#define CLK_CON_DIV_DIV_CLK_CMU_NOCP 0x18f0 + +static const unsigned long top_clk_regs[] __initconst = { + PLL_LOCKTIME_PLL_MMC, + PLL_LOCKTIME_PLL_SHARED0, + PLL_LOCKTIME_PLL_SHARED1, + PLL_LOCKTIME_PLL_SHARED2, + PLL_LOCKTIME_PLL_SHARED3, + PLL_LOCKTIME_PLL_SHARED4, + PLL_LOCKTIME_PLL_SHARED5, + PLL_CON0_PLL_MMC, + PLL_CON3_PLL_MMC, + PLL_CON0_PLL_SHARED0, + PLL_CON3_PLL_SHARED0, + PLL_CON0_PLL_SHARED1, + PLL_CON3_PLL_SHARED1, + PLL_CON0_PLL_SHARED2, + PLL_CON3_PLL_SHARED2, + PLL_CON0_PLL_SHARED3, + PLL_CON3_PLL_SHARED3, + PLL_CON0_PLL_SHARED4, + PLL_CON3_PLL_SHARED4, + PLL_CON0_PLL_SHARED5, + PLL_CON3_PLL_SHARED5, + CLK_CON_MUX_MUX_CLKCMU_ACC_NOC, + CLK_CON_MUX_MUX_CLKCMU_APM_NOC, + CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, + CLK_CON_MUX_MUX_CLKCMU_AUD_NOC, + CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK0, + CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK1, + CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK2, + CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK3, + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER, + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, + CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER, + CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, + CLK_CON_MUX_MUX_CLKCMU_CPUCL2_CLUSTER, + CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, + CLK_CON_MUX_MUX_CLKCMU_DNC_NOC, + CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC, + CLK_CON_MUX_MUX_CLKCMU_DPTX_DPOSC, + CLK_CON_MUX_MUX_CLKCMU_DPTX_NOC, + CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM, + CLK_CON_MUX_MUX_CLKCMU_DPUB_NOC, + CLK_CON_MUX_MUX_CLKCMU_DPUF0_NOC, + CLK_CON_MUX_MUX_CLKCMU_DPUF1_NOC, + CLK_CON_MUX_MUX_CLKCMU_DPUF2_NOC, + CLK_CON_MUX_MUX_CLKCMU_DSP_NOC, + CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP, + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, + CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC, + CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC, + CLK_CON_MUX_MUX_CLKCMU_ACC_ORB, + CLK_CON_MUX_MUX_CLKCMU_GNPU_XMAA, + CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD, + CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC, + CLK_CON_MUX_MUX_CLKCMU_HSI1_USBDRD, + CLK_CON_MUX_MUX_CLKCMU_HSI2_ETHERNET, + CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC, + CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_UFS, + CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, + CLK_CON_MUX_MUX_CLKCMU_ISP_NOC, + CLK_CON_MUX_MUX_CLKCMU_M2M_JPEG, + CLK_CON_MUX_MUX_CLKCMU_M2M_NOC, + CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, + CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, + CLK_CON_MUX_MUX_CLKCMU_MFD_NOC, + CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP, + CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, + CLK_CON_MUX_MUX_CLKCMU_MISC_NOC, + CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC, + CLK_CON_MUX_MUX_CLKCMU_NOCL1_NOC, + CLK_CON_MUX_MUX_CLKCMU_NOCL2_NOC, + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, + CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC, + CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, + CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC, + CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC, + CLK_CON_MUX_MUX_CLKCMU_SNW_NOC, + CLK_CON_MUX_MUX_CLKCMU_SSP_NOC, + CLK_CON_MUX_MUX_CLKCMU_TAA_NOC, + CLK_CON_MUX_MUX_CLK_CMU_NOCP, + CLK_CON_MUX_MUX_CLK_CMU_PLLCLKOUT, + CLK_CON_MUX_MUX_CMU_CMUREF, + CLK_CON_DIV_CLKCMU_ACC_NOC, + CLK_CON_DIV_CLKCMU_APM_NOC, + CLK_CON_DIV_CLKCMU_AUD_CPU, + CLK_CON_DIV_CLKCMU_AUD_NOC, + CLK_CON_DIV_CLKCMU_CIS_MCLK0, + CLK_CON_DIV_CLKCMU_CIS_MCLK1, + CLK_CON_DIV_CLKCMU_CIS_MCLK2, + CLK_CON_DIV_CLKCMU_CIS_MCLK3, + CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER, + CLK_CON_DIV_CLKCMU_CPUCL0_DBG, + CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, + CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER, + CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, + CLK_CON_DIV_CLKCMU_CPUCL2_CLUSTER, + CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, + CLK_CON_DIV_CLKCMU_DNC_NOC, + CLK_CON_DIV_CLKCMU_DPTX_DPGTC, + CLK_CON_DIV_CLKCMU_DPTX_DPOSC, + CLK_CON_DIV_CLKCMU_DPTX_NOC, + CLK_CON_DIV_CLKCMU_DPUB_DSIM, + CLK_CON_DIV_CLKCMU_DPUB_NOC, + CLK_CON_DIV_CLKCMU_DPUF0_NOC, + CLK_CON_DIV_CLKCMU_DPUF1_NOC, + CLK_CON_DIV_CLKCMU_DPUF2_NOC, + CLK_CON_DIV_CLKCMU_DSP_NOC, + CLK_CON_DIV_CLKCMU_G3D_NOCP, + CLK_CON_DIV_CLKCMU_G3D_SWITCH, + CLK_CON_DIV_CLKCMU_GNPU_NOC, + CLK_CON_DIV_CLKCMU_HSI0_NOC, + CLK_CON_DIV_CLKCMU_ACC_ORB, + CLK_CON_DIV_CLKCMU_GNPU_XMAA, + CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD, + CLK_CON_DIV_CLKCMU_HSI1_NOC, + CLK_CON_DIV_CLKCMU_HSI1_USBDRD, + CLK_CON_DIV_CLKCMU_HSI2_ETHERNET, + CLK_CON_DIV_CLKCMU_HSI2_NOC, + CLK_CON_DIV_CLKCMU_HSI2_NOC_UFS, + CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, + CLK_CON_DIV_CLKCMU_ISP_NOC, + CLK_CON_DIV_CLKCMU_M2M_JPEG, + CLK_CON_DIV_CLKCMU_M2M_NOC, + CLK_CON_DIV_CLKCMU_MFC_MFC, + CLK_CON_DIV_CLKCMU_MFC_WFD, + CLK_CON_DIV_CLKCMU_MFD_NOC, + CLK_CON_DIV_CLKCMU_MIF_NOCP, + CLK_CON_DIV_CLKCMU_MISC_NOC, + CLK_CON_DIV_CLKCMU_NOCL0_NOC, + CLK_CON_DIV_CLKCMU_NOCL1_NOC, + CLK_CON_DIV_CLKCMU_NOCL2_NOC, + CLK_CON_DIV_CLKCMU_PERIC0_IP, + CLK_CON_DIV_CLKCMU_PERIC0_NOC, + CLK_CON_DIV_CLKCMU_PERIC1_IP, + CLK_CON_DIV_CLKCMU_PERIC1_NOC, + CLK_CON_DIV_CLKCMU_SDMA_NOC, + CLK_CON_DIV_CLKCMU_SNW_NOC, + CLK_CON_DIV_CLKCMU_SSP_NOC, + CLK_CON_DIV_CLKCMU_TAA_NOC, + CLK_CON_DIV_CLK_ADD_CH_CLK, + CLK_CON_DIV_CLK_CMU_PLLCLKOUT, + CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, + CLK_CON_DIV_DIV_CLK_CMU_NOCP, +}; + +static const struct samsung_pll_clock top_pll_clks[] __initconst = { + /* CMU_TOP_PURECLKCOMP */ + PLL(pll_531x, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", + PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL), + PLL(pll_531x, FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", + PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL), + PLL(pll_531x, FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk", + PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL), + PLL(pll_531x, FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk", + PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL), + PLL(pll_531x, FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk", + PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL), + PLL(pll_531x, FOUT_SHARED5_PLL, "fout_shared5_pll", "oscclk", + PLL_LOCKTIME_PLL_SHARED5, PLL_CON3_PLL_SHARED5, NULL), + PLL(pll_531x, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk", + PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL), +}; + +/* List of parent clocks for Muxes in CMU_TOP */ +PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" }; +PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" }; +PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" }; +PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" }; +PNAME(mout_shared4_pll_p) = { "oscclk", "fout_shared4_pll" }; +PNAME(mout_shared5_pll_p) = { "oscclk", "fout_shared5_pll" }; +PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" }; + +PNAME(mout_clkcmu_cmu_boost_p) = { "dout_shared2_div3", "dout_shared1_div4", + "dout_shared2_div4", "dout_shared4_div4" }; + +PNAME(mout_clkcmu_cmu_cmuref_p) = { "oscclk", "dout_cmu_boost" }; + +PNAME(mout_clkcmu_acc_noc_p) = { "dout_shared2_div2", "dout_shared0_div3", + "dout_shared4_div2", "dout_shared1_div3", + "dout_shared2_div3", "dout_shared5_div1", + "dout_shared3_div1", "oscclk" }; + +PNAME(mout_clkcmu_acc_orb_p) = { "dout_shared2_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div3", "fout_shared5_pll", + "fout_shared3_pll", "oscclk" }; + +PNAME(mout_clkcmu_apm_noc_p) = { "dout_shared2_div2", "dout_shared1_div4", + "dout_shared2_div4", "dout_shared4_div4" }; + +PNAME(mout_clkcmu_aud_cpu_p) = { "dout_shared0_div2", "dout_shared1_div2", + "dout_shared2_div2", "dout_shared0_div3", + "dout_shared4_div2", "dout_shared1_div3", + "dout_shared2_div3", "dout_shared4_div3" }; + +PNAME(mout_clkcmu_aud_noc_p) = { "dout_shared2_div2", "dout_shared4_div2", + "dout_shared1_div2", "dout_shared2_div3" }; + +PNAME(mout_clkcmu_cpucl0_switch_p) = { "dout_shared0_div2", "dout_shared1_div2", + "dout_shared2_div2", "dout_shared4_div2" }; + +PNAME(mout_clkcmu_cpucl0_cluster_p) = { "fout_shared2_pll", "fout_shared4_pll", + "dout_shared0_div2", "dout_shared1_div2", + "dout_shared2_div2", "dout_shared4_div2", + "dout_shared2_div3", "fout_shared3_pll" }; + +PNAME(mout_clkcmu_cpucl0_dbg_p) = { "dout_shared2_div2", "dout_shared0_div3", + "dout_shared4_div2", "dout_shared0_div4" }; + +PNAME(mout_clkcmu_cpucl1_switch_p) = { "dout_shared0_div2", "dout_shared1_div2", + "dout_shared2_div2", "dout_shared4_div2" }; + +PNAME(mout_clkcmu_cpucl1_cluster_p) = { "fout_shared2_pll", "fout_shared4_pll", + "dout_shared0_div2", "dout_shared1_div2", + "dout_shared2_div2", "dout_shared4_div2", + "dout_shared2_div3", "fout_shared3_pll" }; + +PNAME(mout_clkcmu_cpucl2_switch_p) = { "dout_shared0_div2", "dout_shared1_div2", + "dout_shared2_div2", "dout_shared4_div2" }; + +PNAME(mout_clkcmu_cpucl2_cluster_p) = { "fout_shared2_pll", "fout_shared4_pll", + "dout_shared0_div2", "dout_shared1_div2", + "dout_shared2_div2", "dout_shared4_div2", + "dout_shared2_div3", "fout_shared3_pll" }; + +PNAME(mout_clkcmu_dnc_noc_p) = { "dout_shared1_div2", "dout_shared2_div2", + "dout_shared0_div3", "dout_shared4_div2", + "dout_shared1_div3", "dout_shared2_div3", + "dout_shared1_div4", "fout_shared3_pll" }; + +PNAME(mout_clkcmu_dptx_noc_p) = { "dout_shared4_div2", "dout_shared2_div3", + "dout_shared1_div4", "dout_shared2_div4" }; + +PNAME(mout_clkcmu_dptx_dpgtc_p) = { "oscclk", "dout_shared2_div3", + "dout_shared2_div4", "dout_shared4_div4" }; + +PNAME(mout_clkcmu_dptx_dposc_p) = { "oscclk", "dout_shared2_div4" }; + +PNAME(mout_clkcmu_dpub_noc_p) = { "dout_shared4_div2", "dout_shared1_div3", + "dout_shared2_div3", "dout_shared1_div4", + "dout_shared2_div4", "dout_shared4_div4", + "fout_shared3_pll" }; + +PNAME(mout_clkcmu_dpub_dsim_p) = { "dout_shared2_div3", "dout_shared2_div4" }; + +PNAME(mout_clkcmu_dpuf_noc_p) = { "dout_shared4_div2", "dout_shared1_div3", + "dout_shared2_div3", "dout_shared1_div4", + "dout_shared2_div4", "dout_shared4_div4", + "fout_shared3_pll" }; + +PNAME(mout_clkcmu_dsp_noc_p) = { "dout_shared0_div2", "dout_shared1_div2", + "dout_shared2_div2", "dout_shared0_div3", + "dout_shared4_div2", "dout_shared1_div3", + "fout_shared5_pll", "fout_shared3_pll" }; + +PNAME(mout_clkcmu_g3d_switch_p) = { "dout_shared0_div2", "dout_shared1_div2", + "dout_shared2_div2", "dout_shared4_div2" }; + +PNAME(mout_clkcmu_g3d_nocp_p) = { "dout_shared2_div3", "dout_shared1_div4", + "dout_shared2_div4", "dout_shared4_div4" }; + +PNAME(mout_clkcmu_gnpu_noc_p) = { "dout_shared0_div2", "dout_shared1_div2", + "dout_shared2_div2", "dout_shared0_div3", + "dout_shared4_div2", "dout_shared2_div3", + "fout_shared5_pll", "fout_shared3_pll" }; + +PNAME(mout_clkcmu_hsi0_noc_p) = { "dout_shared4_div2", "dout_shared2_div3", + "dout_shared1_div4", "dout_shared2_div4" }; + +PNAME(mout_clkcmu_hsi1_noc_p) = { "dout_shared2_div3", "dout_shared1_div4", + "dout_shared2_div4", "dout_shared4_div4" }; + +PNAME(mout_clkcmu_hsi1_usbdrd_p) = { "oscclk", "dout_shared2_div3", + "dout_shared2_div4", "dout_shared4_div4" }; + +PNAME(mout_clkcmu_hsi1_mmc_card_p) = { "oscclk", "dout_shared2_div2", + "dout_shared4_div2", "fout_mmc_pll" }; + +PNAME(mout_clkcmu_hsi2_noc_p) = { "dout_shared4_div2", "dout_shared2_div3", + "dout_shared1_div4", "dout_shared2_div4" }; + +PNAME(mout_clkcmu_hsi2_noc_ufs_p) = { "dout_shared4_div2", "dout_shared2_div3", + "dout_shared1_div4", "dout_shared2_div2" }; + +PNAME(mout_clkcmu_hsi2_ufs_embd_p) = { "oscclk", "dout_shared2_div3", + "dout_shared2_div4", "dout_shared4_div4" }; + +PNAME(mout_clkcmu_hsi2_ethernet_p) = { "oscclk", "dout_shared2_div2", + "dout_shared0_div3", "dout_shared1_div3" }; + +PNAME(mout_clkcmu_isp_noc_p) = { "dout_shared2_div2", "dout_shared0_div3", + "dout_shared4_div2", "dout_shared1_div3", + "dout_shared2_div3", "fout_shared5_pll", + "fout_shared3_pll", "oscclk" }; + +PNAME(mout_clkcmu_m2m_noc_p) = { "dout_shared0_div3", "dout_shared4_div2", + "dout_shared2_div3", "dout_shared1_div4" }; + +PNAME(mout_clkcmu_m2m_jpeg_p) = { "dout_shared0_div3", "dout_shared4_div2", + "dout_shared2_div3", "dout_shared1_div4" }; + +PNAME(mout_clkcmu_mfc_mfc_p) = { "dout_shared0_div3", "dout_shared4_div2", + "dout_shared2_div3", "dout_shared1_div4" }; + +PNAME(mout_clkcmu_mfc_wfd_p) = { "dout_shared0_div3", "dout_shared4_div2", + "dout_shared2_div3", "dout_shared1_div4" }; + +PNAME(mout_clkcmu_mfd_noc_p) = { "dout_shared2_div2", "dout_shared0_div3", + "dout_shared4_div2", "dout_shared1_div3", + "dout_shared2_div3", "fout_shared5_pll", + "fout_shared3_pll", "oscclk" }; + +PNAME(mout_clkcmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll", + "fout_shared2_pll", "fout_shared4_pll", + "dout_shared0_div2", "dout_shared1_div2", + "dout_shared2_div2", "fout_shared5_pll" }; + +PNAME(mout_clkcmu_mif_nocp_p) = { "dout_shared2_div3", "dout_shared1_div4", + "dout_shared2_div4", "dout_shared4_div4" }; + +PNAME(mout_clkcmu_misc_noc_p) = { "dout_shared4_div2", "dout_shared2_div3", + "dout_shared1_div4", "dout_shared2_div4" }; + +PNAME(mout_clkcmu_nocl0_noc_p) = { "dout_shared0_div2", "dout_shared1_div2", + "dout_shared2_div2", "dout_shared0_div3", + "dout_shared4_div2", "dout_shared1_div3", + "dout_shared2_div3", "fout_shared3_pll" }; + +PNAME(mout_clkcmu_nocl1_noc_p) = { "dout_shared2_div2", "dout_shared0_div3", + "dout_shared4_div2", "dout_shared1_div3", + "dout_shared2_div3", "fout_shared5_pll", + "fout_shared3_pll", "oscclk" }; + +PNAME(mout_clkcmu_nocl2_noc_p) = { "dout_shared2_div2", "dout_shared0_div3", + "dout_shared4_div2", "dout_shared1_div3", + "dout_shared2_div3", "fout_shared5_pll", + "fout_shared3_pll", "oscclk" }; + +PNAME(mout_clkcmu_peric0_noc_p) = { "dout_shared2_div3", "dout_shared2_div4" }; + +PNAME(mout_clkcmu_peric0_ip_p) = { "dout_shared2_div3", "dout_shared2_div4" }; + +PNAME(mout_clkcmu_peric1_noc_p) = { "dout_shared2_div3", "dout_shared2_div4" }; + +PNAME(mout_clkcmu_peric1_ip_p) = { "dout_shared2_div3", "dout_shared2_div4" }; + +PNAME(mout_clkcmu_sdma_noc_p) = { "dout_shared1_div2", "dout_shared2_div2", + "dout_shared0_div3", "dout_shared4_div2", + "dout_shared1_div3", "dout_shared2_div3", + "dout_shared1_div4", "fout_shared3_pll" }; + +PNAME(mout_clkcmu_snw_noc_p) = { "dout_shared2_div2", "dout_shared0_div3", + "dout_shared4_div2", "dout_shared1_div3", + "dout_shared2_div3", "fout_shared5_pll", + "fout_shared3_pll", "oscclk" }; + +PNAME(mout_clkcmu_ssp_noc_p) = { "dout_shared2_div3", "dout_shared1_div4", + "dout_shared2_div2", "dout_shared4_div4" }; + +PNAME(mout_clkcmu_taa_noc_p) = { "dout_shared2_div2", "dout_shared0_div3", + "dout_shared4_div2", "dout_shared1_div3", + "dout_shared2_div3", "fout_shared5_pll", + "fout_shared3_pll", "oscclk" }; + +static const struct samsung_mux_clock top_mux_clks[] __initconst = { + /* CMU_TOP_PURECLKCOMP */ + MUX(MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p, + PLL_CON0_PLL_SHARED0, 4, 1), + MUX(MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p, + PLL_CON0_PLL_SHARED1, 4, 1), + MUX(MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p, + PLL_CON0_PLL_SHARED2, 4, 1), + MUX(MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p, + PLL_CON0_PLL_SHARED3, 4, 1), + MUX(MOUT_SHARED4_PLL, "mout_shared4_pll", mout_shared4_pll_p, + PLL_CON0_PLL_SHARED4, 4, 1), + MUX(MOUT_SHARED5_PLL, "mout_shared5_pll", mout_shared5_pll_p, + PLL_CON0_PLL_SHARED5, 4, 1), + MUX(MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p, + PLL_CON0_PLL_MMC, 4, 1), + + /* BOOST */ + MUX(MOUT_CLKCMU_CMU_BOOST, "mout_clkcmu_cmu_boost", + mout_clkcmu_cmu_boost_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2), + MUX(MOUT_CLKCMU_CMU_CMUREF, "mout_clkcmu_cmu_cmuref", + mout_clkcmu_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1), + + /* ACC */ + MUX(MOUT_CLKCMU_ACC_NOC, "mout_clkcmu_acc_noc", + mout_clkcmu_acc_noc_p, CLK_CON_MUX_MUX_CLKCMU_ACC_NOC, 0, 3), + MUX(MOUT_CLKCMU_ACC_ORB, "mout_clkcmu_acc_orb", + mout_clkcmu_acc_orb_p, CLK_CON_MUX_MUX_CLKCMU_ACC_ORB, 0, 3), + + /* APM */ + MUX(MOUT_CLKCMU_APM_NOC, "mout_clkcmu_apm_noc", + mout_clkcmu_apm_noc_p, CLK_CON_MUX_MUX_CLKCMU_APM_NOC, 0, 2), + + /* AUD */ + MUX(MOUT_CLKCMU_AUD_CPU, "mout_clkcmu_aud_cpu", + mout_clkcmu_aud_cpu_p, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0, 3), + MUX(MOUT_CLKCMU_AUD_NOC, "mout_clkcmu_aud_noc", + mout_clkcmu_aud_noc_p, CLK_CON_MUX_MUX_CLKCMU_AUD_NOC, 0, 2), + + /* CPUCL0 */ + MUX(MOUT_CLKCMU_CPUCL0_SWITCH, "mout_clkcmu_cpucl0_switch", + mout_clkcmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, + 0, 2), + MUX(MOUT_CLKCMU_CPUCL0_CLUSTER, "mout_clkcmu_cpucl0_cluster", + mout_clkcmu_cpucl0_cluster_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER, + 0, 3), + MUX(MOUT_CLKCMU_CPUCL0_DBG, "mout_clkcmu_cpucl0_dbg", + mout_clkcmu_cpucl0_dbg_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, + 0, 2), + + /* CPUCL1 */ + MUX(MOUT_CLKCMU_CPUCL1_SWITCH, "mout_clkcmu_cpucl1_switch", + mout_clkcmu_cpucl1_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, + 0, 2), + MUX(MOUT_CLKCMU_CPUCL1_CLUSTER, "mout_clkcmu_cpucl1_cluster", + mout_clkcmu_cpucl1_cluster_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER, + 0, 3), + + /* CPUCL2 */ + MUX(MOUT_CLKCMU_CPUCL2_SWITCH, "mout_clkcmu_cpucl2_switch", + mout_clkcmu_cpucl2_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, + 0, 2), + MUX(MOUT_CLKCMU_CPUCL2_CLUSTER, "mout_clkcmu_cpucl2_cluster", + mout_clkcmu_cpucl2_cluster_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_CLUSTER, + 0, 3), + + /* DNC */ + MUX(MOUT_CLKCMU_DNC_NOC, "mout_clkcmu_dnc_noc", + mout_clkcmu_dnc_noc_p, CLK_CON_MUX_MUX_CLKCMU_DNC_NOC, 0, 3), + + /* DPTX */ + MUX(MOUT_CLKCMU_DPTX_NOC, "mout_clkcmu_dptx_noc", + mout_clkcmu_dptx_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_NOC, 0, 2), + MUX(MOUT_CLKCMU_DPTX_DPGTC, "mout_clkcmu_dptx_dpgtc", + mout_clkcmu_dptx_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC, 0, 2), + MUX(MOUT_CLKCMU_DPTX_DPOSC, "mout_clkcmu_dptx_dposc", + mout_clkcmu_dptx_dposc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPOSC, 0, 1), + + /* DPUB */ + MUX(MOUT_CLKCMU_DPUB_NOC, "mout_clkcmu_dpub_noc", + mout_clkcmu_dpub_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUB_NOC, 0, 3), + MUX(MOUT_CLKCMU_DPUB_DSIM, "mout_clkcmu_dpub_dsim", + mout_clkcmu_dpub_dsim_p, CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM, 0, 1), + + /* DPUF */ + MUX(MOUT_CLKCMU_DPUF0_NOC, "mout_clkcmu_dpuf0_noc", + mout_clkcmu_dpuf_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUF0_NOC, 0, 3), + MUX(MOUT_CLKCMU_DPUF1_NOC, "mout_clkcmu_dpuf1_noc", + mout_clkcmu_dpuf_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUF1_NOC, 0, 3), + MUX(MOUT_CLKCMU_DPUF2_NOC, "mout_clkcmu_dpuf2_noc", + mout_clkcmu_dpuf_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUF2_NOC, 0, 3), + + /* DSP */ + MUX(MOUT_CLKCMU_DSP_NOC, "mout_clkcmu_dsp_noc", + mout_clkcmu_dsp_noc_p, CLK_CON_MUX_MUX_CLKCMU_DSP_NOC, 0, 3), + + /* G3D */ + MUX(MOUT_CLKCMU_G3D_SWITCH, "mout_clkcmu_g3d_switch", + mout_clkcmu_g3d_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2), + MUX(MOUT_CLKCMU_G3D_NOCP, "mout_clkcmu_g3d_nocp", + mout_clkcmu_g3d_nocp_p, CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP, 0, 2), + + /* GNPU */ + MUX(MOUT_CLKCMU_GNPU_NOC, "mout_clkcmu_gnpu_noc", + mout_clkcmu_gnpu_noc_p, CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC, 0, 3), + + /* HSI0 */ + MUX(MOUT_CLKCMU_HSI0_NOC, "mout_clkcmu_hsi0_noc", + mout_clkcmu_hsi0_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC, 0, 2), + + /* HSI1 */ + MUX(MOUT_CLKCMU_HSI1_NOC, "mout_clkcmu_hsi1_noc", + mout_clkcmu_hsi1_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC, + 0, 2), + MUX(MOUT_CLKCMU_HSI1_USBDRD, "mout_clkcmu_hsi1_usbdrd", + mout_clkcmu_hsi1_usbdrd_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_USBDRD, + 0, 2), + MUX(MOUT_CLKCMU_HSI1_MMC_CARD, "mout_clkcmu_hsi1_mmc_card", + mout_clkcmu_hsi1_mmc_card_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD, + 0, 2), + + /* HSI2 */ + MUX(MOUT_CLKCMU_HSI2_NOC, "mout_clkcmu_hsi2_noc", + mout_clkcmu_hsi2_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC, + 0, 2), + MUX(MOUT_CLKCMU_HSI2_NOC_UFS, "mout_clkcmu_hsi2_noc_ufs", + mout_clkcmu_hsi2_noc_ufs_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_UFS, + 0, 2), + MUX(MOUT_CLKCMU_HSI2_UFS_EMBD, "mout_clkcmu_hsi2_ufs_embd", + mout_clkcmu_hsi2_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, + 0, 2), + MUX(MOUT_CLKCMU_HSI2_ETHERNET, "mout_clkcmu_hsi2_ethernet", + mout_clkcmu_hsi2_ethernet_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_ETHERNET, + 0, 2), + + /* ISP */ + MUX(MOUT_CLKCMU_ISP_NOC, "mout_clkcmu_isp_noc", + mout_clkcmu_isp_noc_p, CLK_CON_MUX_MUX_CLKCMU_ISP_NOC, 0, 3), + + /* M2M */ + MUX(MOUT_CLKCMU_M2M_NOC, "mout_clkcmu_m2m_noc", + mout_clkcmu_m2m_noc_p, CLK_CON_MUX_MUX_CLKCMU_M2M_NOC, 0, 2), + MUX(MOUT_CLKCMU_M2M_JPEG, "mout_clkcmu_m2m_jpeg", + mout_clkcmu_m2m_jpeg_p, CLK_CON_MUX_MUX_CLKCMU_M2M_JPEG, 0, 2), + + /* MFC */ + MUX(MOUT_CLKCMU_MFC_MFC, "mout_clkcmu_mfc_mfc", + mout_clkcmu_mfc_mfc_p, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2), + MUX(MOUT_CLKCMU_MFC_WFD, "mout_clkcmu_mfc_wfd", + mout_clkcmu_mfc_wfd_p, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, 0, 2), + + /* MFD */ + MUX(MOUT_CLKCMU_MFD_NOC, "mout_clkcmu_mfd_noc", + mout_clkcmu_mfd_noc_p, CLK_CON_MUX_MUX_CLKCMU_MFD_NOC, 0, 3), + + /* MIF */ + MUX(MOUT_CLKCMU_MIF_SWITCH, "mout_clkcmu_mif_switch", + mout_clkcmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3), + MUX(MOUT_CLKCMU_MIF_NOCP, "mout_clkcmu_mif_nocp", + mout_clkcmu_mif_nocp_p, CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP, 0, 2), + + /* MISC */ + MUX(MOUT_CLKCMU_MISC_NOC, "mout_clkcmu_misc_noc", + mout_clkcmu_misc_noc_p, CLK_CON_MUX_MUX_CLKCMU_MISC_NOC, 0, 2), + + /* NOCL0 */ + MUX(MOUT_CLKCMU_NOCL0_NOC, "mout_clkcmu_nocl0_noc", + mout_clkcmu_nocl0_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC, 0, 3), + + /* NOCL1 */ + MUX(MOUT_CLKCMU_NOCL1_NOC, "mout_clkcmu_nocl1_noc", + mout_clkcmu_nocl1_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL1_NOC, 0, 3), + + /* NOCL2 */ + MUX(MOUT_CLKCMU_NOCL2_NOC, "mout_clkcmu_nocl2_noc", + mout_clkcmu_nocl2_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL2_NOC, 0, 3), + + /* PERIC0 */ + MUX(MOUT_CLKCMU_PERIC0_NOC, "mout_clkcmu_peric0_noc", + mout_clkcmu_peric0_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC, 0, 1), + MUX(MOUT_CLKCMU_PERIC0_IP, "mout_clkcmu_peric0_ip", + mout_clkcmu_peric0_ip_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 1), + + /* PERIC1 */ + MUX(MOUT_CLKCMU_PERIC1_NOC, "mout_clkcmu_peric1_noc", + mout_clkcmu_peric1_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC, 0, 1), + MUX(MOUT_CLKCMU_PERIC1_IP, "mout_clkcmu_peric1_ip", + mout_clkcmu_peric1_ip_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 1), + + /* SDMA */ + MUX(MOUT_CLKCMU_SDMA_NOC, "mout_clkcmu_sdma_noc", + mout_clkcmu_sdma_noc_p, CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC, 0, 3), + + /* SNW */ + MUX(MOUT_CLKCMU_SNW_NOC, "mout_clkcmu_snw_noc", + mout_clkcmu_snw_noc_p, CLK_CON_MUX_MUX_CLKCMU_SNW_NOC, 0, 3), + + /* SSP */ + MUX(MOUT_CLKCMU_SSP_NOC, "mout_clkcmu_ssp_noc", + mout_clkcmu_ssp_noc_p, CLK_CON_MUX_MUX_CLKCMU_SSP_NOC, 0, 2), + + /* TAA */ + MUX(MOUT_CLKCMU_TAA_NOC, "mout_clkcmu_taa_noc", + mout_clkcmu_taa_noc_p, CLK_CON_MUX_MUX_CLKCMU_TAA_NOC, 0, 3), +}; + +static const struct samsung_div_clock top_div_clks[] __initconst = { + /* CMU_TOP_PURECLKCOMP */ + + /* BOOST */ + DIV(DOUT_CLKCMU_CMU_BOOST, "dout_clkcmu_cmu_boost", + "mout_clkcmu_cmu_boost", CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2), + + /* ACC */ + DIV(DOUT_CLKCMU_ACC_NOC, "dout_clkcmu_acc_noc", + "mout_clkcmu_acc_noc", CLK_CON_DIV_CLKCMU_ACC_NOC, 0, 4), + DIV(DOUT_CLKCMU_ACC_ORB, "dout_clkcmu_acc_orb", + "mout_clkcmu_acc_orb", CLK_CON_DIV_CLKCMU_ACC_ORB, 0, 4), + + /* APM */ + DIV(DOUT_CLKCMU_APM_NOC, "dout_clkcmu_apm_noc", + "mout_clkcmu_apm_noc", CLK_CON_DIV_CLKCMU_APM_NOC, 0, 3), + + /* AUD */ + DIV(DOUT_CLKCMU_AUD_CPU, "dout_clkcmu_aud_cpu", + "mout_clkcmu_aud_cpu", CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3), + DIV(DOUT_CLKCMU_AUD_NOC, "dout_clkcmu_aud_noc", + "mout_clkcmu_aud_noc", CLK_CON_DIV_CLKCMU_AUD_NOC, 0, 4), + + /* CPUCL0 */ + DIV(DOUT_CLKCMU_CPUCL0_SWITCH, "dout_clkcmu_cpucl0_switch", + "mout_clkcmu_cpucl0_switch", + CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3), + DIV(DOUT_CLKCMU_CPUCL0_CLUSTER, "dout_clkcmu_cpucl0_cluster", + "mout_clkcmu_cpucl0_cluster", + CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER, 0, 3), + DIV(DOUT_CLKCMU_CPUCL0_DBG, "dout_clkcmu_cpucl0_dbg", + "mout_clkcmu_cpucl0_dbg", + CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4), + + /* CPUCL1 */ + DIV(DOUT_CLKCMU_CPUCL1_SWITCH, "dout_clkcmu_cpucl1_switch", + "mout_clkcmu_cpucl1_switch", + CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3), + DIV(DOUT_CLKCMU_CPUCL1_CLUSTER, "dout_clkcmu_cpucl1_cluster", + "mout_clkcmu_cpucl1_cluster", + CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER, 0, 3), + + /* CPUCL2 */ + DIV(DOUT_CLKCMU_CPUCL2_SWITCH, "dout_clkcmu_cpucl2_switch", + "mout_clkcmu_cpucl2_switch", + CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3), + DIV(DOUT_CLKCMU_CPUCL2_CLUSTER, "dout_clkcmu_cpucl2_cluster", + "mout_clkcmu_cpucl2_cluster", + CLK_CON_DIV_CLKCMU_CPUCL2_CLUSTER, 0, 3), + + /* DNC */ + DIV(DOUT_CLKCMU_DNC_NOC, "dout_clkcmu_dnc_noc", + "mout_clkcmu_dnc_noc", CLK_CON_DIV_CLKCMU_DNC_NOC, 0, 4), + + /* DPTX */ + DIV(DOUT_CLKCMU_DPTX_NOC, "dout_clkcmu_dptx_noc", + "mout_clkcmu_dptx_noc", CLK_CON_DIV_CLKCMU_DPTX_NOC, 0, 4), + DIV(DOUT_CLKCMU_DPTX_DPGTC, "dout_clkcmu_dptx_dpgtc", + "mout_clkcmu_dptx_dpgtc", CLK_CON_DIV_CLKCMU_DPTX_DPGTC, 0, 3), + DIV(DOUT_CLKCMU_DPTX_DPOSC, "dout_clkcmu_dptx_dposc", + "mout_clkcmu_dptx_dposc", CLK_CON_DIV_CLKCMU_DPTX_DPOSC, 0, 5), + + /* DPUB */ + DIV(DOUT_CLKCMU_DPUB_NOC, "dout_clkcmu_dpub_noc", + "mout_clkcmu_dpub_noc", CLK_CON_DIV_CLKCMU_DPUB_NOC, 0, 4), + DIV(DOUT_CLKCMU_DPUB_DSIM, "dout_clkcmu_dpub_dsim", + "mout_clkcmu_dpub_dsim", CLK_CON_DIV_CLKCMU_DPUB_DSIM, 0, 4), + + /* DPUF */ + DIV(DOUT_CLKCMU_DPUF0_NOC, "dout_clkcmu_dpuf0_noc", + "mout_clkcmu_dpuf0_noc", CLK_CON_DIV_CLKCMU_DPUF0_NOC, 0, 4), + DIV(DOUT_CLKCMU_DPUF1_NOC, "dout_clkcmu_dpuf1_noc", + "mout_clkcmu_dpuf1_noc", CLK_CON_DIV_CLKCMU_DPUF1_NOC, 0, 4), + DIV(DOUT_CLKCMU_DPUF2_NOC, "dout_clkcmu_dpuf2_noc", + "mout_clkcmu_dpuf2_noc", CLK_CON_DIV_CLKCMU_DPUF2_NOC, 0, 4), + + /* DSP */ + DIV(DOUT_CLKCMU_DSP_NOC, "dout_clkcmu_dsp_noc", + "mout_clkcmu_dsp_noc", CLK_CON_DIV_CLKCMU_DSP_NOC, 0, 4), + + /* G3D */ + DIV(DOUT_CLKCMU_G3D_SWITCH, "dout_clkcmu_g3d_switch", + "mout_clkcmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3), + DIV(DOUT_CLKCMU_G3D_NOCP, "dout_clkcmu_g3d_nocp", + "mout_clkcmu_g3d_nocp", CLK_CON_DIV_CLKCMU_G3D_NOCP, 0, 3), + + /* GNPU */ + DIV(DOUT_CLKCMU_GNPU_NOC, "dout_clkcmu_gnpu_noc", + "mout_clkcmu_gnpu_noc", CLK_CON_DIV_CLKCMU_GNPU_NOC, 0, 4), + + /* HSI0 */ + DIV(DOUT_CLKCMU_HSI0_NOC, "dout_clkcmu_hsi0_noc", + "mout_clkcmu_hsi0_noc", CLK_CON_DIV_CLKCMU_HSI0_NOC, 0, 4), + + /* HSI1 */ + DIV(DOUT_CLKCMU_HSI1_NOC, "dout_clkcmu_hsi1_noc", + "mout_clkcmu_hsi1_noc", CLK_CON_DIV_CLKCMU_HSI1_NOC, 0, 4), + DIV(DOUT_CLKCMU_HSI1_USBDRD, "dout_clkcmu_hsi1_usbdrd", + "mout_clkcmu_hsi1_usbdrd", CLK_CON_DIV_CLKCMU_HSI1_USBDRD, 0, 4), + DIV(DOUT_CLKCMU_HSI1_MMC_CARD, "dout_clkcmu_hsi1_mmc_card", + "mout_clkcmu_hsi1_mmc_card", CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD, 0, 9), + + /* HSI2 */ + DIV(DOUT_CLKCMU_HSI2_NOC, "dout_clkcmu_hsi2_noc", + "mout_clkcmu_hsi2_noc", CLK_CON_DIV_CLKCMU_HSI2_NOC, 0, 4), + DIV(DOUT_CLKCMU_HSI2_NOC_UFS, "dout_clkcmu_hsi2_noc_ufs", + "mout_clkcmu_hsi2_noc_ufs", CLK_CON_DIV_CLKCMU_HSI2_NOC_UFS, 0, 4), + DIV(DOUT_CLKCMU_HSI2_UFS_EMBD, "dout_clkcmu_hsi2_ufs_embd", + "mout_clkcmu_hsi2_ufs_embd", CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 3), + DIV(DOUT_CLKCMU_HSI2_ETHERNET, "dout_clkcmu_hsi2_ethernet", + "mout_clkcmu_hsi2_ethernet", CLK_CON_DIV_CLKCMU_HSI2_ETHERNET, 0, 3), + + /* ISP */ + DIV(DOUT_CLKCMU_ISP_NOC, "dout_clkcmu_isp_noc", + "mout_clkcmu_isp_noc", CLK_CON_DIV_CLKCMU_ISP_NOC, 0, 4), + + /* M2M */ + DIV(DOUT_CLKCMU_M2M_NOC, "dout_clkcmu_m2m_noc", + "mout_clkcmu_m2m_noc", CLK_CON_DIV_CLKCMU_M2M_NOC, 0, 4), + DIV(DOUT_CLKCMU_M2M_JPEG, "dout_clkcmu_m2m_jpeg", + "mout_clkcmu_m2m_jpeg", CLK_CON_DIV_CLKCMU_M2M_JPEG, 0, 4), + + /* MFC */ + DIV(DOUT_CLKCMU_MFC_MFC, "dout_clkcmu_mfc_mfc", + "mout_clkcmu_mfc_mfc", CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4), + DIV(DOUT_CLKCMU_MFC_WFD, "dout_clkcmu_mfc_wfd", + "mout_clkcmu_mfc_wfd", CLK_CON_DIV_CLKCMU_MFC_WFD, 0, 4), + + /* MFD */ + DIV(DOUT_CLKCMU_MFD_NOC, "dout_clkcmu_mfd_noc", + "mout_clkcmu_mfd_noc", CLK_CON_DIV_CLKCMU_MFD_NOC, 0, 4), + + /* MIF */ + DIV(DOUT_CLKCMU_MIF_NOCP, "dout_clkcmu_mif_nocp", + "mout_clkcmu_mif_nocp", CLK_CON_DIV_CLKCMU_MIF_NOCP, 0, 4), + + /* MISC */ + DIV(DOUT_CLKCMU_MISC_NOC, "dout_clkcmu_misc_noc", + "mout_clkcmu_misc_noc", CLK_CON_DIV_CLKCMU_MISC_NOC, 0, 4), + + /* NOCL0 */ + DIV(DOUT_CLKCMU_NOCL0_NOC, "dout_clkcmu_nocl0_noc", + "mout_clkcmu_nocl0_noc", CLK_CON_DIV_CLKCMU_NOCL0_NOC, 0, 4), + + /* NOCL1 */ + DIV(DOUT_CLKCMU_NOCL1_NOC, "dout_clkcmu_nocl1_noc", + "mout_clkcmu_nocl1_noc", CLK_CON_DIV_CLKCMU_NOCL1_NOC, 0, 4), + + /* NOCL2 */ + DIV(DOUT_CLKCMU_NOCL2_NOC, "dout_clkcmu_nocl2_noc", + "mout_clkcmu_nocl2_noc", CLK_CON_DIV_CLKCMU_NOCL2_NOC, 0, 4), + + /* PERIC0 */ + DIV(DOUT_CLKCMU_PERIC0_NOC, "dout_clkcmu_peric0_noc", + "mout_clkcmu_peric0_noc", CLK_CON_DIV_CLKCMU_PERIC0_NOC, 0, 4), + DIV(DOUT_CLKCMU_PERIC0_IP, "dout_clkcmu_peric0_ip", + "mout_clkcmu_peric0_ip", CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4), + + /* PERIC1 */ + DIV(DOUT_CLKCMU_PERIC1_NOC, "dout_clkcmu_peric1_noc", + "mout_clkcmu_peric1_noc", CLK_CON_DIV_CLKCMU_PERIC1_NOC, 0, 4), + DIV(DOUT_CLKCMU_PERIC1_IP, "dout_clkcmu_peric1_ip", + "mout_clkcmu_peric1_ip", CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4), + + /* SDMA */ + DIV(DOUT_CLKCMU_SDMA_NOC, "dout_clkcmu_sdma_noc", + "mout_clkcmu_sdma_noc", CLK_CON_DIV_CLKCMU_SDMA_NOC, 0, 4), + + /* SNW */ + DIV(DOUT_CLKCMU_SNW_NOC, "dout_clkcmu_snw_noc", + "mout_clkcmu_snw_noc", CLK_CON_DIV_CLKCMU_SNW_NOC, 0, 4), + + /* SSP */ + DIV(DOUT_CLKCMU_SSP_NOC, "dout_clkcmu_ssp_noc", + "mout_clkcmu_ssp_noc", CLK_CON_DIV_CLKCMU_SSP_NOC, 0, 4), + + /* TAA */ + DIV(DOUT_CLKCMU_TAA_NOC, "dout_clkcmu_taa_noc", + "mout_clkcmu_taa_noc", CLK_CON_DIV_CLKCMU_TAA_NOC, 0, 4), +}; + +static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = { + FFACTOR(DOUT_SHARED0_DIV1, "dout_shared0_div1", + "mout_shared0_pll", 1, 1, 0), + FFACTOR(DOUT_SHARED0_DIV2, "dout_shared0_div2", + "mout_shared0_pll", 1, 2, 0), + FFACTOR(DOUT_SHARED0_DIV3, "dout_shared0_div3", + "mout_shared0_pll", 1, 3, 0), + FFACTOR(DOUT_SHARED0_DIV4, "dout_shared0_div4", + "mout_shared0_pll", 1, 4, 0), + FFACTOR(DOUT_SHARED1_DIV1, "dout_shared1_div1", + "mout_shared1_pll", 1, 1, 0), + FFACTOR(DOUT_SHARED1_DIV2, "dout_shared1_div2", + "mout_shared1_pll", 1, 2, 0), + FFACTOR(DOUT_SHARED1_DIV3, "dout_shared1_div3", + "mout_shared1_pll", 1, 3, 0), + FFACTOR(DOUT_SHARED1_DIV4, "dout_shared1_div4", + "mout_shared1_pll", 1, 4, 0), + FFACTOR(DOUT_SHARED2_DIV1, "dout_shared2_div1", + "mout_shared2_pll", 1, 1, 0), + FFACTOR(DOUT_SHARED2_DIV2, "dout_shared2_div2", + "mout_shared2_pll", 1, 2, 0), + FFACTOR(DOUT_SHARED2_DIV3, "dout_shared2_div3", + "mout_shared2_pll", 1, 3, 0), + FFACTOR(DOUT_SHARED2_DIV4, "dout_shared2_div4", + "mout_shared2_pll", 1, 4, 0), + FFACTOR(DOUT_SHARED3_DIV1, "dout_shared3_div1", + "mout_shared3_pll", 1, 1, 0), + FFACTOR(DOUT_SHARED3_DIV2, "dout_shared3_div2", + "mout_shared3_pll", 1, 2, 0), + FFACTOR(DOUT_SHARED3_DIV3, "dout_shared3_div3", + "mout_shared3_pll", 1, 3, 0), + FFACTOR(DOUT_SHARED3_DIV4, "dout_shared3_div4", + "mout_shared3_pll", 1, 4, 0), + FFACTOR(DOUT_SHARED4_DIV1, "dout_shared4_div1", + "mout_shared4_pll", 1, 1, 0), + FFACTOR(DOUT_SHARED4_DIV2, "dout_shared4_div2", + "mout_shared4_pll", 1, 2, 0), + FFACTOR(DOUT_SHARED4_DIV3, "dout_shared4_div3", + "mout_shared4_pll", 1, 3, 0), + FFACTOR(DOUT_SHARED4_DIV4, "dout_shared4_div4", + "mout_shared4_pll", 1, 4, 0), + FFACTOR(DOUT_SHARED5_DIV1, "dout_shared5_div1", + "mout_shared5_pll", 1, 1, 0), + FFACTOR(DOUT_SHARED5_DIV2, "dout_shared5_div2", + "mout_shared5_pll", 1, 2, 0), + FFACTOR(DOUT_SHARED5_DIV3, "dout_shared5_div3", + "mout_shared5_pll", 1, 3, 0), + FFACTOR(DOUT_SHARED5_DIV4, "dout_shared5_div4", + "mout_shared5_pll", 1, 4, 0), +}; + +static const struct samsung_cmu_info top_cmu_info __initconst = { + .pll_clks = top_pll_clks, + .nr_pll_clks = ARRAY_SIZE(top_pll_clks), + .mux_clks = top_mux_clks, + .nr_mux_clks = ARRAY_SIZE(top_mux_clks), + .div_clks = top_div_clks, + .nr_div_clks = ARRAY_SIZE(top_div_clks), + .fixed_factor_clks = top_fixed_factor_clks, + .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks), + .nr_clk_ids = CLKS_NR_TOP, + .clk_regs = top_clk_regs, + .nr_clk_regs = ARRAY_SIZE(top_clk_regs), +}; + +static void __init exynosautov920_cmu_top_init(struct device_node *np) +{ + exynos_arm64_register_cmu(NULL, np, &top_cmu_info); +} + +/* Register CMU_TOP early, as it's a dependency for other early domains */ +CLK_OF_DECLARE(exynosautov920_cmu_top, "samsung,exynosautov920-cmu-top", + exynosautov920_cmu_top_init); + +/* ---- CMU_PERIC0 --------------------------------------------------------- */ + +/* Register Offset definitions for CMU_PERIC0 (0x10800000) */ +#define PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER 0x0600 +#define PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER 0x0610 +#define CLK_CON_MUX_MUX_CLK_PERIC0_I3C 0x1000 +#define CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI 0x1004 +#define CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI 0x1008 +#define CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI 0x100c +#define CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI 0x1010 +#define CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI 0x1014 +#define CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI 0x1018 +#define CLK_CON_MUX_MUX_CLK_PERIC0_USI06_USI 0x101c +#define CLK_CON_MUX_MUX_CLK_PERIC0_USI07_USI 0x1020 +#define CLK_CON_MUX_MUX_CLK_PERIC0_USI08_USI 0x1024 +#define CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C 0x1028 +#define CLK_CON_DIV_DIV_CLK_PERIC0_I3C 0x1800 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI 0x1804 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI 0x1808 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI 0x180c +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI 0x1810 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI 0x1814 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI 0x1818 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI06_USI 0x181c +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI07_USI 0x1820 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI08_USI 0x1824 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C 0x1828 + +static const unsigned long peric0_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER, + CLK_CON_MUX_MUX_CLK_PERIC0_I3C, + CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI, + CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI, + CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI, + CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI, + CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI, + CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI, + CLK_CON_MUX_MUX_CLK_PERIC0_USI06_USI, + CLK_CON_MUX_MUX_CLK_PERIC0_USI07_USI, + CLK_CON_MUX_MUX_CLK_PERIC0_USI08_USI, + CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C, + CLK_CON_DIV_DIV_CLK_PERIC0_I3C, + CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI06_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI07_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI08_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, +}; + +/* List of parent clocks for Muxes in CMU_PERIC0 */ +PNAME(mout_peric0_ip_user_p) = { "oscclk", "dout_clkcmu_peric0_ip" }; +PNAME(mout_peric0_noc_user_p) = { "oscclk", "dout_clkcmu_peric0_noc" }; +PNAME(mout_peric0_usi_p) = { "oscclk", "mout_peric0_ip_user" }; + +static const struct samsung_mux_clock peric0_mux_clks[] __initconst = { + MUX(CLK_MOUT_PERIC0_IP_USER, "mout_peric0_ip_user", + mout_peric0_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_NOC_USER, "mout_peric0_noc_user", + mout_peric0_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER, 4, 1), + /* USI00 ~ USI08 */ + MUX(CLK_MOUT_PERIC0_USI00_USI, "mout_peric0_usi00_usi", + mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI, 0, 1), + MUX(CLK_MOUT_PERIC0_USI01_USI, "mout_peric0_usi01_usi", + mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI, 0, 1), + MUX(CLK_MOUT_PERIC0_USI02_USI, "mout_peric0_usi02_usi", + mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI, 0, 1), + MUX(CLK_MOUT_PERIC0_USI03_USI, "mout_peric0_usi03_usi", + mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI, 0, 1), + MUX(CLK_MOUT_PERIC0_USI04_USI, "mout_peric0_usi04_usi", + mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI, 0, 1), + MUX(CLK_MOUT_PERIC0_USI05_USI, "mout_peric0_usi05_usi", + mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI, 0, 1), + MUX(CLK_MOUT_PERIC0_USI06_USI, "mout_peric0_usi06_usi", + mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI06_USI, 0, 1), + MUX(CLK_MOUT_PERIC0_USI07_USI, "mout_peric0_usi07_usi", + mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI07_USI, 0, 1), + MUX(CLK_MOUT_PERIC0_USI08_USI, "mout_peric0_usi08_usi", + mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI08_USI, 0, 1), + /* USI_I2C */ + MUX(CLK_MOUT_PERIC0_USI_I2C, "mout_peric0_usi_i2c", + mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C, 0, 1), + /* USI_I3C */ + MUX(CLK_MOUT_PERIC0_I3C, "mout_peric0_i3c", + mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_I3C, 0, 1), +}; + +static const struct samsung_div_clock peric0_div_clks[] __initconst = { + /* USI00 ~ USI08 */ + DIV(CLK_DOUT_PERIC0_USI00_USI, "dout_peric0_usi00_usi", + "mout_peric0_usi00_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI, + 0, 4), + DIV(CLK_DOUT_PERIC0_USI01_USI, "dout_peric0_usi01_usi", + "mout_peric0_usi01_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI, + 0, 4), + DIV(CLK_DOUT_PERIC0_USI02_USI, "dout_peric0_usi02_usi", + "mout_peric0_usi02_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI, + 0, 4), + DIV(CLK_DOUT_PERIC0_USI03_USI, "dout_peric0_usi03_usi", + "mout_peric0_usi03_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI, + 0, 4), + DIV(CLK_DOUT_PERIC0_USI04_USI, "dout_peric0_usi04_usi", + "mout_peric0_usi04_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI, + 0, 4), + DIV(CLK_DOUT_PERIC0_USI05_USI, "dout_peric0_usi05_usi", + "mout_peric0_usi05_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI, + 0, 4), + DIV(CLK_DOUT_PERIC0_USI06_USI, "dout_peric0_usi06_usi", + "mout_peric0_usi06_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI06_USI, + 0, 4), + DIV(CLK_DOUT_PERIC0_USI07_USI, "dout_peric0_usi07_usi", + "mout_peric0_usi07_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI07_USI, + 0, 4), + DIV(CLK_DOUT_PERIC0_USI08_USI, "dout_peric0_usi08_usi", + "mout_peric0_usi08_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI08_USI, + 0, 4), + /* USI_I2C */ + DIV(CLK_DOUT_PERIC0_USI_I2C, "dout_peric0_usi_i2c", + "mout_peric0_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 0, 4), + /* USI_I3C */ + DIV(CLK_DOUT_PERIC0_I3C, "dout_peric0_i3c", + "mout_peric0_i3c", CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 0, 4), +}; + +static const struct samsung_cmu_info peric0_cmu_info __initconst = { + .mux_clks = peric0_mux_clks, + .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), + .div_clks = peric0_div_clks, + .nr_div_clks = ARRAY_SIZE(peric0_div_clks), + .nr_clk_ids = CLKS_NR_PERIC0, + .clk_regs = peric0_clk_regs, + .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), + .clk_name = "dout_clkcmu_peric0_noc", +}; + +static int __init exynosautov920_cmu_probe(struct platform_device *pdev) +{ + const struct samsung_cmu_info *info; + struct device *dev = &pdev->dev; + + info = of_device_get_match_data(dev); + exynos_arm64_register_cmu(dev, dev->of_node, info); + + return 0; +} + +static const struct of_device_id exynosautov920_cmu_of_match[] = { + { + .compatible = "samsung,exynosautov920-cmu-peric0", + .data = &peric0_cmu_info, + }, +}; + +static struct platform_driver exynosautov920_cmu_driver __refdata = { + .driver = { + .name = "exynosautov920-cmu", + .of_match_table = exynosautov920_cmu_of_match, + .suppress_bind_attrs = true, + }, + .probe = exynosautov920_cmu_probe, +}; + +static int __init exynosautov920_cmu_init(void) +{ + return platform_driver_register(&exynosautov920_cmu_driver); +} +core_initcall(exynosautov920_cmu_init); -- 2.45.2 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v6 4/4] clk: samsung: add top clock support for ExynosAuto v920 SoC 2024-08-19 5:24 ` [PATCH v6 4/4] clk: samsung: add top clock support for ExynosAuto v920 SoC Sunyeal Hong @ 2024-08-19 9:32 ` Kwanghoon Son 2024-08-20 1:50 ` sunyeal.hong 0 siblings, 1 reply; 17+ messages in thread From: Kwanghoon Son @ 2024-08-19 9:32 UTC (permalink / raw) To: Sunyeal Hong, Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Conor Dooley Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On Mon, 2024-08-19 at 14:24 +0900, Sunyeal Hong wrote: > This adds support for CMU_TOP which generates clocks for all the > function blocks such as CORE, HSI0/1/2, PERIC0/1 and so on. For > CMU_TOP, PLL_SHARED0,1,2,3,4 and 5 will be the sources of this block > and they will generate bus clocks. > > Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> > --- > drivers/clk/samsung/Makefile | 1 + > drivers/clk/samsung/clk-exynosautov920.c | 1173 ++++++++++++++++++++++ > 2 files changed, 1174 insertions(+) > create mode 100644 drivers/clk/samsung/clk-exynosautov920.c > > diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile > index 3056944a5a54..f1ba48758c78 100644 > --- a/drivers/clk/samsung/Makefile > +++ b/drivers/clk/samsung/Makefile > @@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o > +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov920.o > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o > obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o > obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o > diff --git a/drivers/clk/samsung/clk-exynosautov920.c b/drivers/clk/samsung/clk-exynosautov920.c > new file mode 100644 > index 000000000000..c17d25e3c9a0 > --- /dev/null > +++ b/drivers/clk/samsung/clk-exynosautov920.c [snip] > +}; > + > +static const struct samsung_cmu_info peric0_cmu_info __initconst = { > + .mux_clks = peric0_mux_clks, > + .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), > + .div_clks = peric0_div_clks, > + .nr_div_clks = ARRAY_SIZE(peric0_div_clks), > + .nr_clk_ids = CLKS_NR_PERIC0, > + .clk_regs = peric0_clk_regs, > + .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), > + .clk_name = "dout_clkcmu_peric0_noc", same question. Isn't it "noc"? https://lore.kernel.org/linux-samsung-soc/58dfae564a4a624e464c7803a309f1f07b5ae83d.camel@samsung.com/ In my case(autov9), if put wrong clk_name dmesg will show that, exynos_arm64_register_cmu: could not enable bus clock ...; err = -2 Kwang. ^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: [PATCH v6 4/4] clk: samsung: add top clock support for ExynosAuto v920 SoC 2024-08-19 9:32 ` Kwanghoon Son @ 2024-08-20 1:50 ` sunyeal.hong 2024-08-20 9:54 ` Kwanghoon Son 0 siblings, 1 reply; 17+ messages in thread From: sunyeal.hong @ 2024-08-20 1:50 UTC (permalink / raw) To: 'Kwanghoon Son', 'Krzysztof Kozlowski', 'Sylwester Nawrocki', 'Chanwoo Choi', 'Alim Akhtar', 'Michael Turquette', 'Stephen Boyd', 'Rob Herring', 'Conor Dooley' Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel Hello Kwanghoon, > -----Original Message----- > From: Kwanghoon Son <k.son@samsung.com> > Sent: Monday, August 19, 2024 6:32 PM > To: Sunyeal Hong <sunyeal.hong@samsung.com>; Krzysztof Kozlowski > <krzk@kernel.org>; Sylwester Nawrocki <s.nawrocki@samsung.com>; Chanwoo > Choi <cw00.choi@samsung.com>; Alim Akhtar <alim.akhtar@samsung.com>; > Michael Turquette <mturquette@baylibre.com>; Stephen Boyd > <sboyd@kernel.org>; Rob Herring <robh@kernel.org>; Conor Dooley > <conor+dt@kernel.org> > Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org > Subject: Re: [PATCH v6 4/4] clk: samsung: add top clock support for > ExynosAuto v920 SoC > > On Mon, 2024-08-19 at 14:24 +0900, Sunyeal Hong wrote: > > This adds support for CMU_TOP which generates clocks for all the > > function blocks such as CORE, HSI0/1/2, PERIC0/1 and so on. For > > CMU_TOP, PLL_SHARED0,1,2,3,4 and 5 will be the sources of this block > > and they will generate bus clocks. > > > > Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> > > --- > > drivers/clk/samsung/Makefile | 1 + > > drivers/clk/samsung/clk-exynosautov920.c | 1173 > > ++++++++++++++++++++++ > > 2 files changed, 1174 insertions(+) > > create mode 100644 drivers/clk/samsung/clk-exynosautov920.c > > > > diff --git a/drivers/clk/samsung/Makefile > > b/drivers/clk/samsung/Makefile index 3056944a5a54..f1ba48758c78 100644 > > --- a/drivers/clk/samsung/Makefile > > +++ b/drivers/clk/samsung/Makefile > > @@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk- > exynos7.o > > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o > > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o > > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o > > +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov920.o > > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o > > obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o > > obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210- > audss.o > > diff --git a/drivers/clk/samsung/clk-exynosautov920.c > > b/drivers/clk/samsung/clk-exynosautov920.c > > new file mode 100644 > > index 000000000000..c17d25e3c9a0 > > --- /dev/null > > +++ b/drivers/clk/samsung/clk-exynosautov920.c > > [snip] > > > +}; > > + > > +static const struct samsung_cmu_info peric0_cmu_info __initconst = { > > + .mux_clks = peric0_mux_clks, > > + .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), > > + .div_clks = peric0_div_clks, > > + .nr_div_clks = ARRAY_SIZE(peric0_div_clks), > > + .nr_clk_ids = CLKS_NR_PERIC0, > > + .clk_regs = peric0_clk_regs, > > + .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), > > + .clk_name = "dout_clkcmu_peric0_noc", > > same question. > Isn't it "noc"? > https://lore.kernel.org/linux-samsung- > soc/58dfae564a4a624e464c7803a309f1f07b5ae83d.camel@samsung.com/ > > In my case(autov9), if put wrong clk_name dmesg will show that, > exynos_arm64_register_cmu: could not enable bus clock ...; err = -2 > > Kwang. > > clk_name follows the guide document provided by hw. v9 is bus, but v920 uses noc. Best Regards, sunyeal ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v6 4/4] clk: samsung: add top clock support for ExynosAuto v920 SoC 2024-08-20 1:50 ` sunyeal.hong @ 2024-08-20 9:54 ` Kwanghoon Son 2024-08-21 2:23 ` sunyeal.hong 0 siblings, 1 reply; 17+ messages in thread From: Kwanghoon Son @ 2024-08-20 9:54 UTC (permalink / raw) To: sunyeal.hong, 'Krzysztof Kozlowski', 'Sylwester Nawrocki', 'Chanwoo Choi', 'Alim Akhtar', 'Michael Turquette', 'Stephen Boyd', 'Rob Herring', 'Conor Dooley' Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On Tue, 2024-08-20 at 10:50 +0900, sunyeal.hong wrote: > Hello Kwanghoon, > > > -----Original Message----- > > From: Kwanghoon Son <k.son@samsung.com> > > Sent: Monday, August 19, 2024 6:32 PM > > To: Sunyeal Hong <sunyeal.hong@samsung.com>; Krzysztof Kozlowski > > <krzk@kernel.org>; Sylwester Nawrocki <s.nawrocki@samsung.com>; Chanwoo > > Choi <cw00.choi@samsung.com>; Alim Akhtar <alim.akhtar@samsung.com>; > > Michael Turquette <mturquette@baylibre.com>; Stephen Boyd > > <sboyd@kernel.org>; Rob Herring <robh@kernel.org>; Conor Dooley > > <conor+dt@kernel.org> > > Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; > > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > > kernel@vger.kernel.org > > Subject: Re: [PATCH v6 4/4] clk: samsung: add top clock support for > > ExynosAuto v920 SoC > > > > On Mon, 2024-08-19 at 14:24 +0900, Sunyeal Hong wrote: > > > This adds support for CMU_TOP which generates clocks for all the > > > function blocks such as CORE, HSI0/1/2, PERIC0/1 and so on. For > > > CMU_TOP, PLL_SHARED0,1,2,3,4 and 5 will be the sources of this block > > > and they will generate bus clocks. > > > > > > Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> > > > --- > > > drivers/clk/samsung/Makefile | 1 + > > > drivers/clk/samsung/clk-exynosautov920.c | 1173 > > > ++++++++++++++++++++++ > > > 2 files changed, 1174 insertions(+) > > > create mode 100644 drivers/clk/samsung/clk-exynosautov920.c > > > > > > diff --git a/drivers/clk/samsung/Makefile > > > b/drivers/clk/samsung/Makefile index 3056944a5a54..f1ba48758c78 100644 > > > --- a/drivers/clk/samsung/Makefile > > > +++ b/drivers/clk/samsung/Makefile > > > @@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk- > > exynos7.o > > > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o > > > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o > > > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o > > > +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov920.o > > > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o > > > obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o > > > obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210- > > audss.o > > > diff --git a/drivers/clk/samsung/clk-exynosautov920.c > > > b/drivers/clk/samsung/clk-exynosautov920.c > > > new file mode 100644 > > > index 000000000000..c17d25e3c9a0 > > > --- /dev/null > > > +++ b/drivers/clk/samsung/clk-exynosautov920.c > > > > [snip] > > > > > +}; > > > + > > > +static const struct samsung_cmu_info peric0_cmu_info __initconst = { > > > + .mux_clks = peric0_mux_clks, > > > + .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), > > > + .div_clks = peric0_div_clks, > > > + .nr_div_clks = ARRAY_SIZE(peric0_div_clks), > > > + .nr_clk_ids = CLKS_NR_PERIC0, > > > + .clk_regs = peric0_clk_regs, > > > + .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), > > > + .clk_name = "dout_clkcmu_peric0_noc", > > > > same question. > > Isn't it "noc"? > > https://lore.kernel.org/linux-samsung- > > soc/58dfae564a4a624e464c7803a309f1f07b5ae83d.camel@samsung.com/ > > > > In my case(autov9), if put wrong clk_name dmesg will show that, > > exynos_arm64_register_cmu: could not enable bus clock ...; err = -2 > > > > Kwang. > > > > > > clk_name follows the guide document provided by hw. v9 is bus, but v920 uses noc. What I mean, .clk_name = "dout_clkcmu_peric0_noc", // wrong .clk_name = "noc", // correct Because there is no clock-names "dout_clkcmu_peric0_noc" in exynos/exynosautov920.dtsi. But if you tested your patch and working fine, ignore my comment. Kwang. > > Best Regards, > sunyeal > ^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: [PATCH v6 4/4] clk: samsung: add top clock support for ExynosAuto v920 SoC 2024-08-20 9:54 ` Kwanghoon Son @ 2024-08-21 2:23 ` sunyeal.hong 2024-08-21 6:22 ` Krzysztof Kozlowski 0 siblings, 1 reply; 17+ messages in thread From: sunyeal.hong @ 2024-08-21 2:23 UTC (permalink / raw) To: 'Kwanghoon Son', 'Krzysztof Kozlowski', 'Sylwester Nawrocki', 'Chanwoo Choi', 'Alim Akhtar', 'Michael Turquette', 'Stephen Boyd', 'Rob Herring', 'Conor Dooley' Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel Hello Kwanghoon, > -----Original Message----- > From: Kwanghoon Son <k.son@samsung.com> > Sent: Tuesday, August 20, 2024 6:54 PM > To: sunyeal.hong <sunyeal.hong@samsung.com>; 'Krzysztof Kozlowski' > <krzk@kernel.org>; 'Sylwester Nawrocki' <s.nawrocki@samsung.com>; 'Chanwoo > Choi' <cw00.choi@samsung.com>; 'Alim Akhtar' <alim.akhtar@samsung.com>; > 'Michael Turquette' <mturquette@baylibre.com>; 'Stephen Boyd' > <sboyd@kernel.org>; 'Rob Herring' <robh@kernel.org>; 'Conor Dooley' > <conor+dt@kernel.org> > Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org > Subject: Re: [PATCH v6 4/4] clk: samsung: add top clock support for > ExynosAuto v920 SoC > > On Tue, 2024-08-20 at 10:50 +0900, sunyeal.hong wrote: > > Hello Kwanghoon, > > > > > -----Original Message----- > > > From: Kwanghoon Son <k.son@samsung.com> > > > Sent: Monday, August 19, 2024 6:32 PM > > > To: Sunyeal Hong <sunyeal.hong@samsung.com>; Krzysztof Kozlowski > > > <krzk@kernel.org>; Sylwester Nawrocki <s.nawrocki@samsung.com>; > > > Chanwoo Choi <cw00.choi@samsung.com>; Alim Akhtar > > > <alim.akhtar@samsung.com>; Michael Turquette > > > <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob > > > Herring <robh@kernel.org>; Conor Dooley <conor+dt@kernel.org> > > > Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; > > > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > > > linux- kernel@vger.kernel.org > > > Subject: Re: [PATCH v6 4/4] clk: samsung: add top clock support for > > > ExynosAuto v920 SoC > > > > > > On Mon, 2024-08-19 at 14:24 +0900, Sunyeal Hong wrote: > > > > This adds support for CMU_TOP which generates clocks for all the > > > > function blocks such as CORE, HSI0/1/2, PERIC0/1 and so on. For > > > > CMU_TOP, PLL_SHARED0,1,2,3,4 and 5 will be the sources of this > > > > block and they will generate bus clocks. > > > > > > > > Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> > > > > --- > > > > drivers/clk/samsung/Makefile | 1 + > > > > drivers/clk/samsung/clk-exynosautov920.c | 1173 > > > > ++++++++++++++++++++++ > > > > 2 files changed, 1174 insertions(+) create mode 100644 > > > > drivers/clk/samsung/clk-exynosautov920.c > > > > > > > > diff --git a/drivers/clk/samsung/Makefile > > > > b/drivers/clk/samsung/Makefile index 3056944a5a54..f1ba48758c78 > > > > 100644 > > > > --- a/drivers/clk/samsung/Makefile > > > > +++ b/drivers/clk/samsung/Makefile > > > > @@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk- > > > exynos7.o > > > > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o > > > > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o > > > > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o > > > > +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov920.o > > > > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o > > > > obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o > > > > obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210- > > > audss.o > > > > diff --git a/drivers/clk/samsung/clk-exynosautov920.c > > > > b/drivers/clk/samsung/clk-exynosautov920.c > > > > new file mode 100644 > > > > index 000000000000..c17d25e3c9a0 > > > > --- /dev/null > > > > +++ b/drivers/clk/samsung/clk-exynosautov920.c > > > > > > [snip] > > > > > > > +}; > > > > + > > > > +static const struct samsung_cmu_info peric0_cmu_info __initconst = > { > > > > + .mux_clks = peric0_mux_clks, > > > > + .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), > > > > + .div_clks = peric0_div_clks, > > > > + .nr_div_clks = ARRAY_SIZE(peric0_div_clks), > > > > + .nr_clk_ids = CLKS_NR_PERIC0, > > > > + .clk_regs = peric0_clk_regs, > > > > + .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), > > > > + .clk_name = "dout_clkcmu_peric0_noc", > > > > > > same question. > > > Isn't it "noc"? > > > https://lore.kernel.org/linux-samsung- > > > soc/58dfae564a4a624e464c7803a309f1f07b5ae83d.camel@samsung.com/ > > > > > > In my case(autov9), if put wrong clk_name dmesg will show that, > > > exynos_arm64_register_cmu: could not enable bus clock ...; err = -2 > > > > > > Kwang. > > > > > > > > > > clk_name follows the guide document provided by hw. v9 is bus, but v920 > uses noc. > > What I mean, > > .clk_name = "dout_clkcmu_peric0_noc", // wrong > .clk_name = "noc", // correct > > Because there is no clock-names "dout_clkcmu_peric0_noc" in > exynos/exynosautov920.dtsi. > The clk_name written here has nothing to do with the device tree. Please look at the code carefully. Best Regards, Sunyeal > But if you tested your patch and working fine, ignore my comment. > > Kwang. > > > > > Best Regards, > > sunyeal > > ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v6 4/4] clk: samsung: add top clock support for ExynosAuto v920 SoC 2024-08-21 2:23 ` sunyeal.hong @ 2024-08-21 6:22 ` Krzysztof Kozlowski 2024-08-21 7:06 ` sunyeal.hong 0 siblings, 1 reply; 17+ messages in thread From: Krzysztof Kozlowski @ 2024-08-21 6:22 UTC (permalink / raw) To: sunyeal.hong, 'Kwanghoon Son', 'Sylwester Nawrocki', 'Chanwoo Choi', 'Alim Akhtar', 'Michael Turquette', 'Stephen Boyd', 'Rob Herring', 'Conor Dooley' Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On 21/08/2024 04:23, sunyeal.hong wrote: > Hello Kwanghoon, > >> -----Original Message----- >> From: Kwanghoon Son <k.son@samsung.com> >> Sent: Tuesday, August 20, 2024 6:54 PM >> To: sunyeal.hong <sunyeal.hong@samsung.com>; 'Krzysztof Kozlowski' >> <krzk@kernel.org>; 'Sylwester Nawrocki' <s.nawrocki@samsung.com>; 'Chanwoo >> Choi' <cw00.choi@samsung.com>; 'Alim Akhtar' <alim.akhtar@samsung.com>; >> 'Michael Turquette' <mturquette@baylibre.com>; 'Stephen Boyd' >> <sboyd@kernel.org>; 'Rob Herring' <robh@kernel.org>; 'Conor Dooley' >> <conor+dt@kernel.org> >> Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; >> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- >> kernel@vger.kernel.org >> Subject: Re: [PATCH v6 4/4] clk: samsung: add top clock support for >> ExynosAuto v920 SoC >> >> On Tue, 2024-08-20 at 10:50 +0900, sunyeal.hong wrote: >>> Hello Kwanghoon, >>> >>>> -----Original Message----- >>>> From: Kwanghoon Son <k.son@samsung.com> >>>> Sent: Monday, August 19, 2024 6:32 PM >>>> To: Sunyeal Hong <sunyeal.hong@samsung.com>; Krzysztof Kozlowski >>>> <krzk@kernel.org>; Sylwester Nawrocki <s.nawrocki@samsung.com>; >>>> Chanwoo Choi <cw00.choi@samsung.com>; Alim Akhtar >>>> <alim.akhtar@samsung.com>; Michael Turquette >>>> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob >>>> Herring <robh@kernel.org>; Conor Dooley <conor+dt@kernel.org> >>>> Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; >>>> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; >>>> linux- kernel@vger.kernel.org >>>> Subject: Re: [PATCH v6 4/4] clk: samsung: add top clock support for >>>> ExynosAuto v920 SoC >>>> >>>> On Mon, 2024-08-19 at 14:24 +0900, Sunyeal Hong wrote: >>>>> This adds support for CMU_TOP which generates clocks for all the >>>>> function blocks such as CORE, HSI0/1/2, PERIC0/1 and so on. For >>>>> CMU_TOP, PLL_SHARED0,1,2,3,4 and 5 will be the sources of this >>>>> block and they will generate bus clocks. >>>>> >>>>> Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> >>>>> --- >>>>> drivers/clk/samsung/Makefile | 1 + >>>>> drivers/clk/samsung/clk-exynosautov920.c | 1173 >>>>> ++++++++++++++++++++++ >>>>> 2 files changed, 1174 insertions(+) create mode 100644 >>>>> drivers/clk/samsung/clk-exynosautov920.c >>>>> >>>>> diff --git a/drivers/clk/samsung/Makefile >>>>> b/drivers/clk/samsung/Makefile index 3056944a5a54..f1ba48758c78 >>>>> 100644 >>>>> --- a/drivers/clk/samsung/Makefile >>>>> +++ b/drivers/clk/samsung/Makefile >>>>> @@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk- >>>> exynos7.o >>>>> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o >>>>> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o >>>>> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o >>>>> +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov920.o >>>>> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o >>>>> obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o >>>>> obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210- >>>> audss.o >>>>> diff --git a/drivers/clk/samsung/clk-exynosautov920.c >>>>> b/drivers/clk/samsung/clk-exynosautov920.c >>>>> new file mode 100644 >>>>> index 000000000000..c17d25e3c9a0 >>>>> --- /dev/null >>>>> +++ b/drivers/clk/samsung/clk-exynosautov920.c >>>> >>>> [snip] >>>> >>>>> +}; >>>>> + >>>>> +static const struct samsung_cmu_info peric0_cmu_info __initconst = >> { >>>>> + .mux_clks = peric0_mux_clks, >>>>> + .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), >>>>> + .div_clks = peric0_div_clks, >>>>> + .nr_div_clks = ARRAY_SIZE(peric0_div_clks), >>>>> + .nr_clk_ids = CLKS_NR_PERIC0, >>>>> + .clk_regs = peric0_clk_regs, >>>>> + .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), >>>>> + .clk_name = "dout_clkcmu_peric0_noc", >>>> >>>> same question. >>>> Isn't it "noc"? >>>> https://lore.kernel.org/linux-samsung- >>>> soc/58dfae564a4a624e464c7803a309f1f07b5ae83d.camel@samsung.com/ >>>> >>>> In my case(autov9), if put wrong clk_name dmesg will show that, >>>> exynos_arm64_register_cmu: could not enable bus clock ...; err = -2 >>>> >>>> Kwang. >>>> >>>> >>> >>> clk_name follows the guide document provided by hw. v9 is bus, but v920 >> uses noc. >> >> What I mean, >> >> .clk_name = "dout_clkcmu_peric0_noc", // wrong >> .clk_name = "noc", // correct >> >> Because there is no clock-names "dout_clkcmu_peric0_noc" in >> exynos/exynosautov920.dtsi. >> > > The clk_name written here has nothing to do with the device tree. Please look at the code carefully. Hm? I see in the code clearly: clk_get(dev, cmu->clk_name); Where cmu is the discussed struct. If you claim it does not have anything to do with DT, then what is it for? Best regards, Krzysztof ^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: [PATCH v6 4/4] clk: samsung: add top clock support for ExynosAuto v920 SoC 2024-08-21 6:22 ` Krzysztof Kozlowski @ 2024-08-21 7:06 ` sunyeal.hong 2024-08-21 8:02 ` Krzysztof Kozlowski 0 siblings, 1 reply; 17+ messages in thread From: sunyeal.hong @ 2024-08-21 7:06 UTC (permalink / raw) To: 'Krzysztof Kozlowski', 'Kwanghoon Son', 'Sylwester Nawrocki', 'Chanwoo Choi', 'Alim Akhtar', 'Michael Turquette', 'Stephen Boyd', 'Rob Herring', 'Conor Dooley' Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel Hello Krzysztof, > -----Original Message----- > From: Krzysztof Kozlowski <krzk@kernel.org> > Sent: Wednesday, August 21, 2024 3:23 PM > To: sunyeal.hong <sunyeal.hong@samsung.com>; 'Kwanghoon Son' > <k.son@samsung.com>; 'Sylwester Nawrocki' <s.nawrocki@samsung.com>; > 'Chanwoo Choi' <cw00.choi@samsung.com>; 'Alim Akhtar' > <alim.akhtar@samsung.com>; 'Michael Turquette' <mturquette@baylibre.com>; > 'Stephen Boyd' <sboyd@kernel.org>; 'Rob Herring' <robh@kernel.org>; 'Conor > Dooley' <conor+dt@kernel.org> > Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org > Subject: Re: [PATCH v6 4/4] clk: samsung: add top clock support for > ExynosAuto v920 SoC > > On 21/08/2024 04:23, sunyeal.hong wrote: > > Hello Kwanghoon, > > > >> -----Original Message----- > >> From: Kwanghoon Son <k.son@samsung.com> > >> Sent: Tuesday, August 20, 2024 6:54 PM > >> To: sunyeal.hong <sunyeal.hong@samsung.com>; 'Krzysztof Kozlowski' > >> <krzk@kernel.org>; 'Sylwester Nawrocki' <s.nawrocki@samsung.com>; > >> 'Chanwoo Choi' <cw00.choi@samsung.com>; 'Alim Akhtar' > >> <alim.akhtar@samsung.com>; 'Michael Turquette' > <mturquette@baylibre.com>; 'Stephen Boyd' > >> <sboyd@kernel.org>; 'Rob Herring' <robh@kernel.org>; 'Conor Dooley' > >> <conor+dt@kernel.org> > >> Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; > >> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > >> linux- kernel@vger.kernel.org > >> Subject: Re: [PATCH v6 4/4] clk: samsung: add top clock support for > >> ExynosAuto v920 SoC > >> > >> On Tue, 2024-08-20 at 10:50 +0900, sunyeal.hong wrote: > >>> Hello Kwanghoon, > >>> > >>>> -----Original Message----- > >>>> From: Kwanghoon Son <k.son@samsung.com> > >>>> Sent: Monday, August 19, 2024 6:32 PM > >>>> To: Sunyeal Hong <sunyeal.hong@samsung.com>; Krzysztof Kozlowski > >>>> <krzk@kernel.org>; Sylwester Nawrocki <s.nawrocki@samsung.com>; > >>>> Chanwoo Choi <cw00.choi@samsung.com>; Alim Akhtar > >>>> <alim.akhtar@samsung.com>; Michael Turquette > >>>> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob > >>>> Herring <robh@kernel.org>; Conor Dooley <conor+dt@kernel.org> > >>>> Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; > >>>> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > >>>> linux- kernel@vger.kernel.org > >>>> Subject: Re: [PATCH v6 4/4] clk: samsung: add top clock support for > >>>> ExynosAuto v920 SoC > >>>> > >>>> On Mon, 2024-08-19 at 14:24 +0900, Sunyeal Hong wrote: > >>>>> This adds support for CMU_TOP which generates clocks for all the > >>>>> function blocks such as CORE, HSI0/1/2, PERIC0/1 and so on. For > >>>>> CMU_TOP, PLL_SHARED0,1,2,3,4 and 5 will be the sources of this > >>>>> block and they will generate bus clocks. > >>>>> > >>>>> Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> > >>>>> --- > >>>>> drivers/clk/samsung/Makefile | 1 + > >>>>> drivers/clk/samsung/clk-exynosautov920.c | 1173 > >>>>> ++++++++++++++++++++++ > >>>>> 2 files changed, 1174 insertions(+) create mode 100644 > >>>>> drivers/clk/samsung/clk-exynosautov920.c > >>>>> > >>>>> diff --git a/drivers/clk/samsung/Makefile > >>>>> b/drivers/clk/samsung/Makefile index 3056944a5a54..f1ba48758c78 > >>>>> 100644 > >>>>> --- a/drivers/clk/samsung/Makefile > >>>>> +++ b/drivers/clk/samsung/Makefile > >>>>> @@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk- > >>>> exynos7.o > >>>>> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o > >>>>> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o > >>>>> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o > >>>>> +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov920.o > >>>>> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o > >>>>> obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o > >>>>> obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210- > >>>> audss.o > >>>>> diff --git a/drivers/clk/samsung/clk-exynosautov920.c > >>>>> b/drivers/clk/samsung/clk-exynosautov920.c > >>>>> new file mode 100644 > >>>>> index 000000000000..c17d25e3c9a0 > >>>>> --- /dev/null > >>>>> +++ b/drivers/clk/samsung/clk-exynosautov920.c > >>>> > >>>> [snip] > >>>> > >>>>> +}; > >>>>> + > >>>>> +static const struct samsung_cmu_info peric0_cmu_info __initconst > >>>>> += > >> { > >>>>> + .mux_clks = peric0_mux_clks, > >>>>> + .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), > >>>>> + .div_clks = peric0_div_clks, > >>>>> + .nr_div_clks = ARRAY_SIZE(peric0_div_clks), > >>>>> + .nr_clk_ids = CLKS_NR_PERIC0, > >>>>> + .clk_regs = peric0_clk_regs, > >>>>> + .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), > >>>>> + .clk_name = "dout_clkcmu_peric0_noc", > >>>> > >>>> same question. > >>>> Isn't it "noc"? > >>>> https://lore.kernel.org/linux-samsung- > >>>> soc/58dfae564a4a624e464c7803a309f1f07b5ae83d.camel@samsung.com/ > >>>> > >>>> In my case(autov9), if put wrong clk_name dmesg will show that, > >>>> exynos_arm64_register_cmu: could not enable bus clock ...; err = -2 > >>>> > >>>> Kwang. > >>>> > >>>> > >>> > >>> clk_name follows the guide document provided by hw. v9 is bus, but > >>> v920 > >> uses noc. > >> > >> What I mean, > >> > >> .clk_name = "dout_clkcmu_peric0_noc", // wrong > >> .clk_name = "noc", // correct > >> > >> Because there is no clock-names "dout_clkcmu_peric0_noc" in > >> exynos/exynosautov920.dtsi. > >> > > > > The clk_name written here has nothing to do with the device tree. Please > look at the code carefully. > > Hm? I see in the code clearly: > > clk_get(dev, cmu->clk_name); > > Where cmu is the discussed struct. > > If you claim it does not have anything to do with DT, then what is it for? > > Best regards, > Krzysztof In general, clk_get is used via the clk_name declared in the DT. However, the question asked here is the parent clock name of peric0_noc, so it is unrelated to the device tree. PNAME(mout_peric0_noc_user_p) = { "oscclk", "dout_clkcmu_peric0_noc" }; So we are using clk_name as "dout_clkcmu_peric0_noc". Best Regards, sunyeal ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v6 4/4] clk: samsung: add top clock support for ExynosAuto v920 SoC 2024-08-21 7:06 ` sunyeal.hong @ 2024-08-21 8:02 ` Krzysztof Kozlowski 2024-08-21 9:30 ` sunyeal.hong 0 siblings, 1 reply; 17+ messages in thread From: Krzysztof Kozlowski @ 2024-08-21 8:02 UTC (permalink / raw) To: sunyeal.hong, 'Kwanghoon Son', 'Sylwester Nawrocki', 'Chanwoo Choi', 'Alim Akhtar', 'Michael Turquette', 'Stephen Boyd', 'Rob Herring', 'Conor Dooley' Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On 21/08/2024 09:06, sunyeal.hong wrote: >>>>>>> + .clk_name = "dout_clkcmu_peric0_noc", >>>>>> >>>>>> same question. >>>>>> Isn't it "noc"? >>>>>> https://lore.kernel.org/linux-samsung- >>>>>> soc/58dfae564a4a624e464c7803a309f1f07b5ae83d.camel@samsung.com/ >>>>>> >>>>>> In my case(autov9), if put wrong clk_name dmesg will show that, >>>>>> exynos_arm64_register_cmu: could not enable bus clock ...; err = -2 >>>>>> >>>>>> Kwang. >>>>>> >>>>>> >>>>> >>>>> clk_name follows the guide document provided by hw. v9 is bus, but >>>>> v920 >>>> uses noc. >>>> >>>> What I mean, >>>> >>>> .clk_name = "dout_clkcmu_peric0_noc", // wrong >>>> .clk_name = "noc", // correct >>>> >>>> Because there is no clock-names "dout_clkcmu_peric0_noc" in >>>> exynos/exynosautov920.dtsi. >>>> >>> >>> The clk_name written here has nothing to do with the device tree. Please >> look at the code carefully. >> >> Hm? I see in the code clearly: >> >> clk_get(dev, cmu->clk_name); >> >> Where cmu is the discussed struct. >> >> If you claim it does not have anything to do with DT, then what is it for? >> >> Best regards, >> Krzysztof > > In general, clk_get is used via the clk_name declared in the DT. > > However, the question asked here is the parent clock name of peric0_noc, so it is unrelated to the device tree. No. The question was about clk_name entry in cmu info used directly for clk_get. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: [PATCH v6 4/4] clk: samsung: add top clock support for ExynosAuto v920 SoC 2024-08-21 8:02 ` Krzysztof Kozlowski @ 2024-08-21 9:30 ` sunyeal.hong 0 siblings, 0 replies; 17+ messages in thread From: sunyeal.hong @ 2024-08-21 9:30 UTC (permalink / raw) To: 'Krzysztof Kozlowski', 'Kwanghoon Son', 'Sylwester Nawrocki', 'Chanwoo Choi', 'Alim Akhtar', 'Michael Turquette', 'Stephen Boyd', 'Rob Herring', 'Conor Dooley' Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel Hello Krzysztof, > -----Original Message----- > From: Krzysztof Kozlowski <krzk@kernel.org> > Sent: Wednesday, August 21, 2024 5:02 PM > To: sunyeal.hong <sunyeal.hong@samsung.com>; 'Kwanghoon Son' > <k.son@samsung.com>; 'Sylwester Nawrocki' <s.nawrocki@samsung.com>; > 'Chanwoo Choi' <cw00.choi@samsung.com>; 'Alim Akhtar' > <alim.akhtar@samsung.com>; 'Michael Turquette' <mturquette@baylibre.com>; > 'Stephen Boyd' <sboyd@kernel.org>; 'Rob Herring' <robh@kernel.org>; 'Conor > Dooley' <conor+dt@kernel.org> > Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org > Subject: Re: [PATCH v6 4/4] clk: samsung: add top clock support for > ExynosAuto v920 SoC > > On 21/08/2024 09:06, sunyeal.hong wrote: > >>>>>>> + .clk_name = "dout_clkcmu_peric0_noc", > >>>>>> > >>>>>> same question. > >>>>>> Isn't it "noc"? > >>>>>> https://lore.kernel.org/linux-samsung- > >>>>>> soc/58dfae564a4a624e464c7803a309f1f07b5ae83d.camel@samsung.com/ > >>>>>> > >>>>>> In my case(autov9), if put wrong clk_name dmesg will show that, > >>>>>> exynos_arm64_register_cmu: could not enable bus clock ...; err = > >>>>>> -2 > >>>>>> > >>>>>> Kwang. > >>>>>> > >>>>>> > >>>>> > >>>>> clk_name follows the guide document provided by hw. v9 is bus, but > >>>>> v920 > >>>> uses noc. > >>>> > >>>> What I mean, > >>>> > >>>> .clk_name = "dout_clkcmu_peric0_noc", // wrong > >>>> .clk_name = "noc", // correct > >>>> > >>>> Because there is no clock-names "dout_clkcmu_peric0_noc" in > >>>> exynos/exynosautov920.dtsi. > >>>> > >>> > >>> The clk_name written here has nothing to do with the device tree. > >>> Please > >> look at the code carefully. > >> > >> Hm? I see in the code clearly: > >> > >> clk_get(dev, cmu->clk_name); > >> > >> Where cmu is the discussed struct. > >> > >> If you claim it does not have anything to do with DT, then what is it > for? > >> > >> Best regards, > >> Krzysztof > > > > In general, clk_get is used via the clk_name declared in the DT. > > > > However, the question asked here is the parent clock name of peric0_noc, > so it is unrelated to the device tree. > > No. The question was about clk_name entry in cmu info used directly for > clk_get. > I have verified that peric0 has a dev parameter and that it should use a clk_name that matches the clock-names declared in the device tree. I will update the patch with a fix. Best Regards, sunyeal > > Best regards, > Krzysztof > ^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2024-08-21 9:30 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz follow: Atom feed
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[not found] <CGME20240819052422epcas2p27acdb1fd7154984cfebe54506bcaac65@epcas2p2.samsung.com>
2024-08-19 5:24 ` [PATCH v6 0/4] initial clock support for exynosauto v920 SoC Sunyeal Hong
[not found] ` <CGME20240819052422epcas2p4db394defd5f298658f7841af3649ac6f@epcas2p4.samsung.com>
2024-08-19 5:24 ` [PATCH v6 1/4] dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings Sunyeal Hong
2024-08-19 8:19 ` Krzysztof Kozlowski
2024-08-20 1:46 ` sunyeal.hong
2024-08-20 3:16 ` Alim Akhtar
2024-08-20 7:43 ` sunyeal.hong
[not found] ` <CGME20240819052422epcas2p4f2ee384824a64e1b6f074de972ab3ffc@epcas2p4.samsung.com>
2024-08-19 5:24 ` [PATCH v6 2/4] arm64: dts: exynos: add initial CMU clock nodes in ExynosAuto v920 Sunyeal Hong
[not found] ` <CGME20240819052422epcas2p3f7ae25b479f54f2402ffd11a0942937d@epcas2p3.samsung.com>
2024-08-19 5:24 ` [PATCH v6 3/4] clk: samsung: clk-pll: Add support for pll_531x Sunyeal Hong
[not found] ` <CGME20240819052422epcas2p258a29e773ebdd60573078c21f7a7da12@epcas2p2.samsung.com>
2024-08-19 5:24 ` [PATCH v6 4/4] clk: samsung: add top clock support for ExynosAuto v920 SoC Sunyeal Hong
2024-08-19 9:32 ` Kwanghoon Son
2024-08-20 1:50 ` sunyeal.hong
2024-08-20 9:54 ` Kwanghoon Son
2024-08-21 2:23 ` sunyeal.hong
2024-08-21 6:22 ` Krzysztof Kozlowski
2024-08-21 7:06 ` sunyeal.hong
2024-08-21 8:02 ` Krzysztof Kozlowski
2024-08-21 9:30 ` sunyeal.hong
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