From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 661C0C433FE for ; Thu, 24 Nov 2022 15:41:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229455AbiKXPlB (ORCPT ); Thu, 24 Nov 2022 10:41:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229681AbiKXPlA (ORCPT ); Thu, 24 Nov 2022 10:41:00 -0500 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88AC21181C5 for ; Thu, 24 Nov 2022 07:40:56 -0800 (PST) Received: by mail-lf1-x136.google.com with SMTP id g12so3084109lfh.3 for ; Thu, 24 Nov 2022 07:40:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=VCFr/V7FAnUFT7OVq5HHngjGTeEZtVW0kYV/zxFYTPc=; b=aYxs7vhu8jPqjCN15B5pqN7dNBgORyB31x0aypGBK2YwE7g5ceffh8fof5vayOy2ym JJ+o3oU+LsVvV2NTv4QxCdTv99YNZkNoMXl/GACPYrkuUhKsyecybMpRrdIfacUIosFa lcjwddYZehnydafRKjU2Pk75H0O91Gn3NguQRr0xAl3ogyYztTQdJ1AH9TGwIaiQof2w mU+WWX69KP7fT68FbnnhyLYx5WkxWVzBPDuVqIlw9tfFbfBC8nQzLTFyJTKVw1Fyb5vj GN+nrCoPHjzsu2YHpuyoz8fNX2DTikokIsAzHwxrQpR/xqqi+45+E/fJb2v0ChVMzqbS BZ3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=VCFr/V7FAnUFT7OVq5HHngjGTeEZtVW0kYV/zxFYTPc=; b=SZm4/SQVbUHupzVVzE5GuSEdMflPSnwjSdWCKaq8s1C9L3AILAy7G5I6/W7FC9Oo5J /e+GYVsI7MDj5W7/HL3nKtv4K3pQ30SOUF/9NsBbFbRa8ULgR272f342Ho21/xaCNF1T Iz9wh4VGakWcm5ANEqAzKXJlPpaPDG8poMsMyBgFSKedze+33vjvpKlz6T10k/o7dwj5 SEvTz4KtxVzI2OAFuEAzIA/6FFm0TDdCQiV2OV4PlYN4r7Kkm2GWUkVo2wEUzuI12Ks8 PGdOjqcsG7qkl1lGloCzWCST85iglGmldgpkvh5aY+MCeclSSDTBnqJ5NMxB1SJ8C+K2 iueQ== X-Gm-Message-State: ANoB5pmLeRIAy2Nug0vE2t4XztJ1WwHtdgZ750bN/E5S2WKvCOI36v7p H4MxFd7TvpxMZgjV4ye9zdcMPQ== X-Google-Smtp-Source: AA0mqf536HBjiuDg+9ktwHptPvepcOWScFiBLpyxA9u0eHO58gQM32+AjiQz+blwQ/A6LK087PUDCg== X-Received: by 2002:ac2:4c50:0:b0:4b1:8a90:6524 with SMTP id o16-20020ac24c50000000b004b18a906524mr10455255lfk.628.1669304454885; Thu, 24 Nov 2022 07:40:54 -0800 (PST) Received: from [192.168.1.101] (95.49.32.48.neoplus.adsl.tpnet.pl. [95.49.32.48]) by smtp.gmail.com with ESMTPSA id j17-20020a056512029100b004b4e77ae383sm156008lfp.88.2022.11.24.07.40.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 24 Nov 2022 07:40:54 -0800 (PST) Message-ID: <0a119446-4ec1-46ce-68e5-f177f9cb49e3@linaro.org> Date: Thu, 24 Nov 2022 16:40:52 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [PATCH v2 02/10] arm64: dts: qcom: Add base SM8550 dtsi Content-Language: en-US To: Sai Prakash Ranjan , Abel Vesa , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Neil Armstrong Cc: Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org References: <20221124135646.1952727-1-abel.vesa@linaro.org> <20221124135646.1952727-3-abel.vesa@linaro.org> <351fa466-90cb-b73f-a2a4-749bc3529e22@quicinc.com> From: Konrad Dybcio In-Reply-To: <351fa466-90cb-b73f-a2a4-749bc3529e22@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 24.11.2022 16:39, Sai Prakash Ranjan wrote: > Hi, > > On 11/24/2022 7:26 PM, Abel Vesa wrote: >> Add base dtsi for SM8550 SoC and includes base description of >> CPUs, GCC, RPMHCC, UART, interrupt controller, TLMM, reserved >> memory, RPMh PD, TCSRCC, ITS, IPCC, AOSS QMP, LLCC, cpufreq, >> interconnect, thermal sensor, cpu cooling maps and SMMU nodes >> which helps boot to shell with console on boards with this SoC. >> >> Co-developed-by: Neil Armstrong >> Signed-off-by: Neil Armstrong >> Signed-off-by: Abel Vesa >> --- > > ... > >> +    timer { >> +        compatible = "arm,armv8-timer"; >> +        interrupts = , >> +                 , >> +                 , >> +                 ; > > This last interrupt must be Hypervisor physical irq(10) and 12 is Hyp virtual irq, so please change it to 10. I guess you got this from downstream but it's not right and they don't boot kernel in EL2. Does non-CrOS 8550 FW allow Linux to boot in EL2? Konrad > > Thanks, > Sai