From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5932CC47094 for ; Thu, 10 Jun 2021 13:36:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 375B260FF0 for ; Thu, 10 Jun 2021 13:36:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230458AbhFJNh5 (ORCPT ); Thu, 10 Jun 2021 09:37:57 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:23014 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S230413AbhFJNh5 (ORCPT ); Thu, 10 Jun 2021 09:37:57 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 15ADRTRM027439; Thu, 10 Jun 2021 15:35:42 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=subject : to : references : from : message-id : date : mime-version : in-reply-to : content-type : content-transfer-encoding; s=selector1; bh=PVwoi7QXAKZzjqIJrJlU43OTjFre496R9tdNWd8Ac2w=; b=ZN81NbvDFhrXwk4O1UyjffqcLGTinleTVxJhmVMlxYd5rFaqSI/dX2wNs1w2DGinAbNh Lt8/ZcUg5m0Ncdsjg0M6PEn/h5cniXxt1kuO1hOPYkb0BNIN3jxBzL0OOOF8AwSzSRHZ /jLKxZ8ARy7finN7O9nUCe5fnM4T64Z5Dxd/SsFfUgyCp+2BPFIYWqAR5V1LndMt5SNJ rjo/l64Jg4AQCtfpzScvPu6zaAvb6UhWrK0u9NCsKTYD4RFb7so9WENiByooWQ3/Ok6u mnfPKfUlIRVQ98HRjwzP+cIPkoOHqiRoHGvs0W3obLUGD7VSc4FJRhDTnPa6JcUIMt4p Bg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 392xq7y0g4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 10 Jun 2021 15:35:42 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 38EB2100034; Thu, 10 Jun 2021 15:35:41 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node3.st.com [10.75.127.6]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 195B7228817; Thu, 10 Jun 2021 15:35:41 +0200 (CEST) Received: from lmecxl0912.lme.st.com (10.75.127.50) by SFHDAG2NODE3.st.com (10.75.127.6) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 10 Jun 2021 15:35:40 +0200 Subject: Re: [PATCH v2] ARM: dts: stm32: add a new DCMI pins group To: Grzegorz Szymaszek , Maxime Coquelin , Ahmad Fatoum , Marcin Sloniewski , Rob Herring , , , , References: From: Alexandre TORGUE Message-ID: <0b37872e-4ae9-acd6-5698-b188ad38bb8a@foss.st.com> Date: Thu, 10 Jun 2021 15:35:40 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.50] X-ClientProxiedBy: SFHDAG2NODE1.st.com (10.75.127.4) To SFHDAG2NODE3.st.com (10.75.127.6) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.761 definitions=2021-06-10_07:2021-06-10,2021-06-10 signatures=0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi On 6/3/21 5:34 PM, Grzegorz Szymaszek wrote: > The Seeed Odyssey-STM32MP157C board has a 20-pin DVP camera output. > stm32mp15-pinctrl.dtsi contained one pin state definition for the DCMI > interface, dcmi-0, AKA phandle dcmi_pins_a. This definition was > incompatible with the pins used on the Odyssey board, where: > - there are 8 data pins instead of 12, > - DCMI_HSYNC is available at PA4 instead of PH8, > - DCMI_D0 is at PC6 instead of PH9, > - DCMI_D3 is at PE1 instead of PH12, > - DCMI_D4 is at PE11 instead of PH14, > - DCMI_D5 is at PD3 instead of PI4, > - DCMI_D6 is at PE13 instead of PB8, > - DCMI_D7 is at PB9 instead of PE6. > > Add the DCMI pins used on the Odyssey board as a new DCMI pin state > definition, dcmi-1, AKA phandle dcmi_pins_b. > > Signed-off-by: Grzegorz Szymaszek > --- > V1 -> V2: Removed the pinctrl override from the Odyssey device tree, > added a new pinctrl in stm32mp15-pinctrl.dtsi instead > > arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 33 ++++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > Applied on stm32-next. I just updated the commit title by "ARM: dts: stm32: add a new DCMI pins group on stm32mp15" Thanks. Alex > diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi > index 060baa8b7e9d..5b60ecbd718f 100644 > --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi > +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi > @@ -118,6 +118,39 @@ pins { > }; > }; > > + dcmi_pins_b: dcmi-1 { > + pins { > + pinmux = ,/* DCMI_HSYNC */ > + ,/* DCMI_VSYNC */ > + ,/* DCMI_PIXCLK */ > + ,/* DCMI_D0 */ > + ,/* DCMI_D1 */ > + ,/* DCMI_D2 */ > + ,/* DCMI_D3 */ > + ,/* DCMI_D4 */ > + ,/* DCMI_D5 */ > + ,/* DCMI_D6 */ > + ;/* DCMI_D7 */ > + bias-disable; > + }; > + }; > + > + dcmi_sleep_pins_b: dcmi-sleep-1 { > + pins { > + pinmux = ,/* DCMI_HSYNC */ > + ,/* DCMI_VSYNC */ > + ,/* DCMI_PIXCLK */ > + ,/* DCMI_D0 */ > + ,/* DCMI_D1 */ > + ,/* DCMI_D2 */ > + ,/* DCMI_D3 */ > + ,/* DCMI_D4 */ > + ,/* DCMI_D5 */ > + ,/* DCMI_D6 */ > + ;/* DCMI_D7 */ > + }; > + }; > + > ethernet0_rgmii_pins_a: rgmii-0 { > pins1 { > pinmux = , /* ETH_RGMII_CLK125 */ >