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Wed, 17 Jul 2024 06:24:43 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46H6Of3O006632 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 17 Jul 2024 06:24:41 GMT Received: from [10.218.19.46] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 16 Jul 2024 23:24:36 -0700 Message-ID: <0b84b689-8ab8-bcdf-f058-da2ead73786c@quicinc.com> Date: Wed, 17 Jul 2024 11:54:33 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.9.0 Subject: Re: [PATCH v2 5/6] clk: qcom: Add camera clock controller driver for SM8150 Content-Language: en-US To: Bryan O'Donoghue , Dmitry Baryshkov CC: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Abhishek Sahu , "Rob Herring" , Krzysztof Kozlowski , Conor Dooley , Stephen Boyd , , , , , Ajit Pandey , "Imran Shaik" , Taniya Das , Jagadeesh Kona References: <20240702-camcc-support-sm8150-v2-0-4baf54ec7333@quicinc.com> <20240702-camcc-support-sm8150-v2-5-4baf54ec7333@quicinc.com> <503c8ba7-585d-4222-8e81-7f4c52f5f513@linaro.org> From: "Satya Priya Kakitapalli (Temp)" In-Reply-To: <503c8ba7-585d-4222-8e81-7f4c52f5f513@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: TBawKkM9EiYE2AYGiOK4qwzdIS0sBxMt X-Proofpoint-GUID: TBawKkM9EiYE2AYGiOK4qwzdIS0sBxMt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-17_03,2024-07-16_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 phishscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 impostorscore=0 suspectscore=0 mlxlogscore=999 priorityscore=1501 bulkscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407170046 On 7/15/2024 8:31 PM, Bryan O'Donoghue wrote: > On 15/07/2024 11:38, Dmitry Baryshkov wrote: >>>> Does it apply to SM8150? For example, on SM8250 RCG2s are not parked. >>> >>> Yes, it applies to SM8150. >> Should the same logic be applied to other chipsets supported upstream? >> If this is the case, which chipsets? > > If you are representing the "top" GDSC inside of the CCF instead of > doing this > > +    /* Keep the critical clock always-on */ > +    qcom_branch_set_clk_en(regmap, 0xc1e4); /* cam_cc_gdsc_clk */ > > then the clock should be parked else you'll find the GDSC doesn't come > out of reset. > > and... as I look at it now we have a logical conflict in > drivers/clk/qcom/camcc-sc8280xp.c > > static struct clk_branch camcc_gdsc_clk = { >         .halt_reg = 0xc1e4, >         .halt_check = BRANCH_HALT, >         .clkr = { >                 .enable_reg = 0xc1e4, >                 .enable_mask = BIT(0), >                 .hw.init = &(struct clk_init_data){ >                         .name = "camcc_gdsc_clk", >                         .parent_hws = (const struct clk_hw*[]){ >                                 &camcc_xo_clk_src.clkr.hw, >                         }, >                         .num_parents = 1, >                         .flags = CLK_SET_RATE_PARENT, >                         .ops = &clk_branch2_ops, >                 }, >         }, > }; > > Patch sent. > > https://lore.kernel.org/linux-arm-msm/20240715-linux-next-24-07-13-sc8280xp-camcc-fixes-v1-1-fadb5d9445c1@linaro.org/T/#u > > If the clock is modelled, it can get disabled during the late init call, when the CCF disables the unused clocks. But, it is a PoR ON  clock and expectation from design team is to keep it always-on for GDSC functionality. So, we should not model this, instead just keep it always on from probe. > In the round I think we should avoid these horrific hard-coded > always-on writes where possible. > We have been suggested to make such clocks always ON from probe on previous upstream discussions. This is also recently acknowledged by maintainers, please see [1] and [2]. [1] https://lore.kernel.org/linux-clk/6286a410-6faa-4996-8a9e-dc334dd9421f@linaro.org/ [2] https://lore.kernel.org/linux-clk/664cca91-8615-d3f6-7525-15b9b6725cce@quicinc.com/ > Personally I think parking is better than always-on specifically > because you define the clock and "see" it in the clock tree. > > --- > bod