From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0AFAC433EF for ; Wed, 20 Apr 2022 03:15:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358002AbiDTDSX (ORCPT ); Tue, 19 Apr 2022 23:18:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48066 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349010AbiDTDSW (ORCPT ); Tue, 19 Apr 2022 23:18:22 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A95E46304; Tue, 19 Apr 2022 20:15:37 -0700 (PDT) X-UUID: 1fb72d17eccb4215ad8f9712affdea33-20220420 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:af9358d1-00b9-4c26-8d5a-21d9f751190f,OB:0,LO B:0,IP:0,URL:8,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACT ION:release,TS:53 X-CID-INFO: VERSION:1.1.4,REQID:af9358d1-00b9-4c26-8d5a-21d9f751190f,OB:0,LOB: 0,IP:0,URL:8,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACTIO N:release,TS:53 X-CID-META: VersionHash:faefae9,CLOUDID:274074ef-06b0-4305-bfbf-554bfc9d151a,C OID:b1f79c9c742c,Recheck:0,SF:13|15|28|17|19|48,TC:nil,Content:0,EDM:-3,Fi le:nil,QS:0,BEC:nil X-UUID: 1fb72d17eccb4215ad8f9712affdea33-20220420 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1562580671; Wed, 20 Apr 2022 11:15:31 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Apr 2022 11:15:31 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Apr 2022 11:15:30 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Apr 2022 11:15:30 +0800 Message-ID: <0b85798f63deb0c943ed1803aaa06cde6437e7bd.camel@mediatek.com> Subject: Re: [PATCH 3/5] dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195 From: Rex-BC Chen To: Chun-Kuang Hu , Matthias Brugger CC: Rob Herring , "krzysztof.kozlowski+dt@linaro.org" , Philipp Zabel , David Airlie , AngeloGioacchino Del Regno , Jason-JH Lin =?UTF-8?Q?=28=E6=9E=97=E7=9D=BF=E7=A5=A5=29?= , Nancy Lin =?UTF-8?Q?=28=E6=9E=97=E6=AC=A3=E8=9E=A2=29?= , DTML , linux-kernel , DRI Development , "moderated list:ARM/Mediatek SoC support" , Linux ARM , Project_Global_Chrome_Upstream_Group Date: Wed, 20 Apr 2022 11:15:30 +0800 In-Reply-To: References: <20220419033237.23405-1-rex-bc.chen@mediatek.com> <20220419033237.23405-4-rex-bc.chen@mediatek.com> <74b3f0e3-1d9f-de9e-ccf0-1f2174ba7c25@gmail.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, 2022-04-19 at 23:51 +0800, Chun-Kuang Hu wrote: > Matthias Brugger 於 2022年4月19日 週二 下午10:57寫道： > > > > > > > > On 19/04/2022 05:32, Rex-BC Chen wrote: > > > From: "Nancy.Lin" > > > > > > Add vdosys1 RDMA definition. > > > > > > Signed-off-by: Nancy.Lin > > > Reviewed-by: AngeloGioacchino Del Regno < > > > angelogioacchino.delregno@collabora.com> > > > --- > > > .../display/mediatek/mediatek,mdp-rdma.yaml | 86 > > > +++++++++++++++++++ > > > 1 file changed, 86 insertions(+) > > > create mode 100644 > > > Documentation/devicetree/bindings/display/mediatek/mediatek,mdp- > > > rdma.yaml > > > > > > diff --git > > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp > > > -rdma.yaml > > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp > > > -rdma.yaml > > > new file mode 100644 > > > index 000000000000..6ab773569462 > > > --- /dev/null > > > +++ > > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp > > > -rdma.yaml > > > @@ -0,0 +1,86 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: > > > https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,mdp-rdma.yaml*__;Iw!!CTRNKA9wMg0ARbw!2Ig4llRcam253qgvT99ty3TWC4Yo6D6Dy1DgFiNuA_fMhtu1lJHERS1f4pzOBELsqIl__FAiHl5bJCAJqNc7FAWGTw$ > > > > > > +$schema: > > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!2Ig4llRcam253qgvT99ty3TWC4Yo6D6Dy1DgFiNuA_fMhtu1lJHERS1f4pzOBELsqIl__FAiHl5bJCAJqNdU9sgsvg$ > > > > > > + > > > +title: MediaTek MDP RDMA > > > + > > > +maintainers: > > > + - Matthias Brugger > > > > I don't think I would be the correct person to maintain this. This > > should be the > > person that is maintaining the driver. > > Agree. This should be > > Chun-Kuang Hu > Philipp Zabel > > Regards, > Chun-Kuang. > > > > > Regards, > > Matthias > > Hello Chun-Kuang and Matthias, OK, I will update the list in next version. BRs, Rex > > > + > > > +description: | > > > + The mediatek MDP RDMA stands for Read Direct Memory Access. > > > + It provides real time data to the back-end panel driver, such > > > as DSI, > > > + DPI and DP_INTF. > > > + It contains one line buffer to store the sufficient pixel > > > data. > > > + RDMA device node must be siblings to the central MMSYS_CONFIG > > > node. > > > + For a description of the MMSYS_CONFIG binding, see > > > + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys. > > > yaml for details. > > > + > > > +properties: > > > + compatible: > > > + oneOf: > > > + - items: > > > + - const: mediatek,mt8195-vdo1-rdma > > > + > > > + reg: > > > + maxItems: 1 > > > + > > > + interrupts: > > > + maxItems: 1 > > > + > > > + power-domains: > > > + description: A phandle and PM domain specifier as defined by > > > bindings of > > > + the power controller specified by phandle. See > > > + Documentation/devicetree/bindings/power/power-domain.yaml > > > for details. > > > + > > > + clocks: > > > + items: > > > + - description: RDMA Clock > > > + > > > + iommus: > > > + description: > > > + This property should point to the respective IOMMU block > > > with master port as argument, > > > + see > > > Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for > > > details. > > > + > > > + mediatek,gce-client-reg: > > > + description: > > > + The register of display function block to be set by gce. > > > There are 4 arguments, > > > + such as gce node, subsys id, offset and register size. The > > > subsys id that is > > > + mapping to the register of display function blocks is > > > defined in the gce header > > > + include/include/dt-bindings/gce/-gce.h of each > > > chips. > > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > > + maxItems: 1 > > > + > > > +required: > > > + - compatible > > > + - reg > > > + - power-domains > > > + - clocks > > > + - iommus > > > + > > > +additionalProperties: false > > > + > > > +examples: > > > + - | > > > + #include > > > + #include > > > + #include > > > + #include > > > + #include > > > + > > > + soc { > > > + #address-cells = <2>; > > > + #size-cells = <2>; > > > + > > > + vdo1_rdma0: mdp-rdma@1c104000 { > > > + compatible = "mediatek,mt8195-vdo1-rdma"; > > > + reg = <0 0x1c104000 0 0x1000>; > > > + interrupts = ; > > > + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; > > > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; > > > + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; > > > + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX > > > 0x4000 0x1000>; > > > + }; > > > + };