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[79.139.233.37]) by smtp.googlemail.com with ESMTPSA id a12sm1194349ljk.48.2020.01.29.08.02.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 29 Jan 2020 08:02:41 -0800 (PST) Subject: Re: [RFC 2/2] dt-bindings: firmware: tegra186-bpmp: Document interconnects property To: Thierry Reding Cc: Georgi Djakov , Rob Herring , Jon Hunter , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org References: <20200114181519.3402385-2-thierry.reding@gmail.com> <7aefac6c-092c-b5a6-2fa6-e283d2147fc3@linaro.org> <20200120150605.GA712203@ulmo> <57c37b3c-1473-d444-db59-8c6650241188@gmail.com> <20200121141027.GE899558@ulmo> <83d94918-bc01-131b-924c-9750767d3b29@linaro.org> <20200121155432.GA912205@ulmo> <20200127122115.GA2117209@ulmo> <20200129093602.GC2479935@ulmo> From: Dmitry Osipenko Message-ID: <0b8692ab-4e06-b277-bbe2-93922e47c2f6@gmail.com> Date: Wed, 29 Jan 2020 19:02:40 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.3.0 MIME-Version: 1.0 In-Reply-To: <20200129093602.GC2479935@ulmo> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org 29.01.2020 12:36, Thierry Reding пишет: > On Tue, Jan 28, 2020 at 10:27:00PM +0300, Dmitry Osipenko wrote: >> 27.01.2020 15:21, Thierry Reding пишет: >>> On Tue, Jan 21, 2020 at 11:12:11PM +0300, Dmitry Osipenko wrote: >>>> 21.01.2020 18:54, Thierry Reding пишет: >>>>> On Tue, Jan 21, 2020 at 05:18:43PM +0200, Georgi Djakov wrote: >>>>>> On 1/21/20 16:10, Thierry Reding wrote: >>> [...] >>>>>>> I'm not sure if that TEGRA_ICC_EMEM makes a lot of sense. It's always >>>>>>> going to be the same and it's arbitrarily defined, so it's effectively >>>>>>> useless. But other than that it looks good. >>>>>> >>>>>> Well, in most cases the target would be the EMEM, so that's fine. I have seen >>>>>> that other vendors that may have an additional internal memory, especially >>>>>> dedicated to some DSPs and in such cases the bandwidth needs are different for >>>>>> the two paths (to internal memory and DDR). >>>>> >>>>> Most chips have a small internal memory that can be used, though it >>>>> seldomly is. However, in that case I would expect the target to be a >>>>> completely different device, so it'd look more like this: >>>>> >>>>> interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &iram>, >>>>> ...; >>>>> >>>>> I don't think EMEM has any "downstream" other than external memory. >>>> >>>> The node ID should be mandatory in terms of interconnect, even if it's a >>>> single node. EMC (provider) != EMEM (endpoint). >>> >>> I don't understand why. An ID only makes sense if you've got multiple >>> endpoints. For example, a regulator is a provider with a single endpoint >>> so we don't specify an ID. >> >> Because this is how ICC binding is defined, unless I'm missing something. > > I don't think so. It's defined as "pairs of phandles and interconnect > provider specifiers", which is equivalent to what pretty much all of the > resource bindings define. The #interconnect-cells property defines the > number of cells used for the specifier. In the normal case this would be > 1, and the value of the one cell would be the ID of the endpoint. But if > there's only a single endpoint, it's customary to set the number of > cells to 0, in which case only the phandle is required. Right, setting interconnect-cells=0 should work. I'll give it a try, thank you!