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Wed, 12 Nov 2025 07:00:39 -0800 (PST) Message-ID: <0bc6fadc6ec9578873fc5413da4405c968bb402b.camel@linaro.org> Subject: Re: [PATCH v4 02/20] regulator: dt-bindings: add s2mpg10-pmic regulators From: =?ISO-8859-1?Q?Andr=E9?= Draszik To: Krzysztof Kozlowski Cc: Tudor Ambarus , Rob Herring , Conor Dooley , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski , Krzysztof Kozlowski , Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org Date: Wed, 12 Nov 2025 15:00:39 +0000 In-Reply-To: <20251112-gainful-flashy-seal-f2c5dc@kuoka> References: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> <20251110-s2mpg1x-regulators-v4-2-94c9e726d4ba@linaro.org> <20251112-gainful-flashy-seal-f2c5dc@kuoka> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-2+build3 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hi Krzysztof, On Wed, 2025-11-12 at 10:51 +0100, Krzysztof Kozlowski wrote: > On Mon, Nov 10, 2025 at 07:28:45PM +0000, Andr=C3=A9 Draszik wrote: > > The S2MPG10 PMIC is a Power Management IC for mobile applications with > > buck converters, various LDOs, power meters, RTC, clock outputs, and > > additional GPIO interfaces. > >=20 > > It has 10 buck and 31 LDO rails. Several of these can either be > > controlled via software (register writes) or via external signals, in > > particular by: > > =C2=A0=C2=A0=C2=A0 * one out of several input pins connected to a main = processor's: > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 *=C2=A0 GPIO pins > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * other pins that are e.g. f= irmware- or power-domain-controlled > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 without explicit= driver intervention > > =C2=A0=C2=A0=C2=A0 * a combination of input pins and register writes. > >=20 > > Control via input pins allows PMIC rails to be controlled by firmware, > > e.g. during standby/suspend, or as part of power domain handling where > > otherwise that would not be possible. Additionally toggling a pin is > > faster than register writes, and it also allows the PMIC to ensure that > > any necessary timing requirements between rails are respected > > automatically if multiple rails are to be enabled or disabled quasi > > simultaneously. > >=20 > > While external control via input pins appears to exist on other > > versions of this PMIC, there is more flexibility in this version, in > > particular there is a selection of input pins to choose from for each > > rail (which must therefore be configured accordingly if in use), > > whereas other versions don't have this flexibility. > >=20 > > Add documentation related to the regulator (buck & ldo) parts like > > devicetree definitions, regulator naming patterns, and additional > > properties. > >=20 > > S2MPG10 is typically used as the main-PMIC together with an S2MPG11 > > PMIC in a main/sub configuration, hence the datasheet and the binding > > both suffix the rails with an 'm'. > >=20 > > Signed-off-by: Andr=C3=A9 Draszik > >=20 > > --- >=20 > What is the base of this? base-commit from cover letter: > fatal: bad object ab40c92c74c6b0c611c89516794502b3a3173966 v4 was sent on top of next-20251110 which is ab40c92c74c6 Cheers, Andre'