From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from vps0.lunn.ch (vps0.lunn.ch [156.67.10.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E197145B11; Sat, 1 Aug 2026 20:59:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=156.67.10.101 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785617949; cv=none; b=nG4Y22srN2ARjf4CeEWY5egoeozGRukAHi6i9q8AOCG/ofuhk85CTCL3tYlrfmw+yZyfEVrXz95XarkRQl+RV3iAUNiOH4oMTokQYogOA5OO74o7TAMabb+MH1M4lM1HqOi8NoGILXR43tUmok8v/bM8RXcnrvf3M+VkjaiNzHY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785617949; c=relaxed/simple; bh=XguoDNauWy0D7G85//Wbhk3WM9XZjBuSVI+T4ztMu3Q=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=ReDpdlE9YTVX3tz9ftPfxKEA7+Y4dEKQdnSAXr6YZt1d0TtYFIJeNnAIzD2vp+oX4IUumuJYIJquGct3IGKzYaA2VW/2EWMRgey+6BXwpGg9cj4HRKW6IKvccZjk+xRv5ZKNufIV5j6K1nbQqNbGi7eGzBmSg3b5rw/n0bM0WlA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch; spf=pass smtp.mailfrom=lunn.ch; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b=cQmZ48EP; arc=none smtp.client-ip=156.67.10.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=lunn.ch Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="cQmZ48EP" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=cZuc4JfzKuG/55z+yA9PYJfiUrL8fDWjW2wegwlHAM0=; b=cQmZ48EPkSZ0QTdYvDVqBI/uQ5 F/8TgqYqXXyVhtpYlxJ4MbOZ6twF0anleKi67Vbe/PSpU3AVcVnacvaEDEEDEemFXfwUV05531Qb8 /C4Y0ac+s/YLGd7KpPuVoXTDwAuV0JtpmZxgJ6F90/nBCVLq2FehLsw6tkuDrxg7M2w8=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1wqGn1-00FQCq-K1; Sat, 01 Aug 2026 22:58:39 +0200 Date: Sat, 1 Aug 2026 22:58:39 +0200 From: Andrew Lunn To: Coia Prant Cc: Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , Lad Prabhakar , Romain Gantois , Heiner Kallweit , Neil Armstrong , Russell King , Shawn Lin , David Heidelberg , netdev@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-renesas-soc@vger.kernel.org Subject: Re: [PATCH v2 03/10] phy: rockchip: naneng-combphy: add SGMII MAC selection for RK3568 Message-ID: <0cf1f734-69d4-471f-aa22-e1a2e7d0341b@lunn.ch> References: <20260801142244.679437-2-coiaprant@gmail.com> <20260801142244.679437-5-coiaprant@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260801142244.679437-5-coiaprant@gmail.com> On Sat, Aug 01, 2026 at 10:22:27PM +0800, Coia Prant wrote: > On RK3568, the SGMII interface can be routed to either GMAC0 or > GMAC1 via the GRF register pipe_sgmii_mac_sel. > > Add support for this selection by introducing > the "rockchip,sgmii-mac-sel" DT property. > > The hardware reset value is GMAC1 (1). If the property is set to 0, > the driver routes SGMII to GMAC0; if set to 1 (or omitted), it > remains at GMAC1. > > This is necessary for boards such as the Ariaboard Photonicat, which > uses the SGMII interface connected to GMAC0. If SGMII is not selected, what MII is used? RGMII? Can this setting be implied from phy-mode? Andrew