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From: Krzysztof Kozlowski <krzk@kernel.org>
To: rohan1sj@cadence.com, Ulf Hansson <ulfh@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Masahiro Yamada <yamada.masahiro@socionext.com>,
	Adrian Hunter <adrian.hunter@intel.com>
Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, mparab@cadence.com,
	pawell@cadence.com, sjakhade@cadence.com, mpillai@cadence.com
Subject: Re: [PATCH v2 1/2] dt-bindings: mmc: cdns,sdhci: Add CQE support
Date: Wed, 6 May 2026 15:24:46 +0200	[thread overview]
Message-ID: <0d9b9a53-2743-4202-96dc-0b922c48f375@kernel.org> (raw)
In-Reply-To: <20260506-cdns_sdhci_cqe-support-v2-1-754fe4de8b65@cadence.com>

On 06/05/2026 11:04, Rohan Joshi via B4 Relay wrote:
> From: Rohan Joshi <rohan1sj@cadence.com>
> 
> Cadence host controller can support CQE. Add optional CQE
> register space and reg-names property to cdns sdhci binding
> 
> Signed-off-by: Rohan Joshi <rohan1sj@cadence.com>
> ---
>  .../devicetree/bindings/mmc/cdns,sdhci.yaml        | 41 +++++++---------------
>  1 file changed, 12 insertions(+), 29 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> index 8902e7925eab..79064282fabc 100644
> --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> @@ -26,7 +26,9 @@ properties:
>  
>    reg-names:

There are no reg-names in this file.

>      minItems: 1
> -    maxItems: 2
> +    items:
> +      - const: hc
> +      - const: cqhci
>  
>    interrupts:
>      maxItems: 1
> @@ -138,22 +140,16 @@ allOf:
>            items:
>              - description: Host controller registers
>              - description: Elba byte-lane enable register for writes
> +        reg-names: false

Why?

> +      required:
> +        - resets

Why?

>      else:
>        properties:
>          reg:
> -          oneOf:
> -            - items:
> -                - description: Host controller registers
> -            - items:
> -                - description: Host controller registers
> -                - description: CQE (Command Queue Engine) registers
> -        reg-names:
> -          oneOf:
> -            - items:
> -                - const: sdhci
> -            - items:
> -                - const: sdhci
> -                - const: cqhci
> +          minItems: 1
> +          items:
> +            - description: Host Controller registers
> +            - description: CQE (Command Queuing Engine) registers

Why each device has CQE? If each, then why not Pensando?



>  
>  unevaluatedProperties: false
>  
> @@ -161,7 +157,8 @@ examples:
>    - |
>      emmc: mmc@5a000000 {
>          compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
> -        reg = <0x5a000000 0x400>;
> +        reg = <0x5a000000 0x400>, <0x5a000400 0x060>;
> +        reg-names = "hc", "cqhci";
>          interrupts = <0 78 4>;
>          clocks = <&clk 4>;
>          bus-width = <8>;
> @@ -170,17 +167,3 @@ examples:
>          mmc-hs400-1_8v;
>          cdns,phy-dll-delay-sdclk = <0>;
>      };
> -
> -  - |

What are you doing here?


Best regards,
Krzysztof

  reply	other threads:[~2026-05-06 13:24 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-06  9:04 [PATCH v2 0/2] CQE support for cadence eMMC host controller Rohan Joshi via B4 Relay
2026-05-06  9:04 ` [PATCH v2 1/2] dt-bindings: mmc: cdns,sdhci: Add CQE support Rohan Joshi via B4 Relay
2026-05-06 13:24   ` Krzysztof Kozlowski [this message]
2026-05-06  9:04 ` [PATCH v2 2/2] mmc: sdhci-cadence: add " Rohan Joshi via B4 Relay
2026-05-06 13:25   ` Krzysztof Kozlowski

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