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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: X55LbwWFDGbLbuBuMyp9bOSLqMyZKvfyeNTjat0MqygfykC5kUXDlIC6saDoE97jesRFQ5aB4MxpyT9CIv5owRK5hGDV8nUysfYvVBHIQNeS2BF3b8KaZ8k0iS0C07Ej7Hs4G4R+7muGCQsW7PbT5sS1+OPvMrc3mcOtXn5Qvz7ZvyCuo89bgECqcb1O7vRLbBE5jFFG1eU3IPQfYtsIcPmpnbTvuUVJOFkR8F1bxqisvlhNd5MJADnf34GrYCsGvT/Y457ycXY+G0V7IcwVeXOBj9dZY4knarQwtsXU7p1CnyJ0uW5laaDSUsNOu9OreUPI+CBynIbE3DALEJMCCR0y8A+VNayKSBcl9RvQfiwciGfgBwzJewXOawVEix52VzAbY7u/PkXLK6tLe0MGwVgbwRvQ16Eh2UuAwNTFdAKOrhaO8TVKFnsFbUjKkR3W X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2026 15:31:23.3956 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0730cc81-9e32-4275-5122-08df2ad15ea6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF00022BC8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7137 On 10/15/2026 9:29 AM, Ben Levinsky wrote: > >> >> >> *From: *Krzysztof Kozlowski >> *Date: *Thursday, October 15, 2026 at 2:46 AM >> *To: *Levinsky, Ben >> *Cc: *jassisinghbrar@gmail.com ; andersson@kernel.org >> ; mathieu.poirier@linaro.org ; >> robh@kernel.org ; krzk+dt@kernel.org ; >> conor+dt@kernel.org ; Simek, Michal ; >> linux-remoteproc@vger.kernel.org ; >> devicetree@vger.kernel.org ; linux-arm- >> kernel@lists.infradead.org ; linux- >> kernel@vger.kernel.org ; Shah, Tanmay >> >> *Subject: *Re: [PATCH 3/6] dt-bindings: mailbox: Add AMD PL Mailbox IP >> >> On Wed, Oct 14, 2026 at 02:34:23PM -0700, Ben Levinsky wrote: >> > Document the AMD programmable-logic Mailbox IP used for bidirectional >> > FIFO communication between two processor-facing interfaces. >> > >> > The same IP is used on ZynqMP, Versal, Versal NET and Versal Gen 2. >> > Name each SoC in its compatible, and use amd,zynqmp-pl-mbox-2.1 as the >> > fallback that drivers match. >> > >> > Define the transmit and receive channel indices together with the register >> > aperture, interrupt, and interface clock. Describe the FIFO depth chosen >> > when the IP is configured, so that the driver can size received messages >> > to it. >> > >> > Assisted-by: LLM sparse >> >> How sparse assists here? It's something new. Since when does it parse >> yaml code? > > Hi Krzysztof, > > Thank you for the review. > > You are right, sparse was not used for this patch. It was only run on > the C patches of the series, and I applied the same trailer to the > whole series by mistake. In v2 the binding patches will name only the > model, and the tool list will match what was actually used on each > patch. > >> >> > Signed-off-by: Ben Levinsky >> > --- >> > .../mailbox/amd,zynqmp-pl-mbox-2.1.yaml | 74 +++++++++++++++++++ >> > 1 file changed, 74 insertions(+) >> > create mode 100644 Documentation/devicetree/bindings/mailbox/amd,zynqmp-pl- >> mbox-2.1.yaml >> > >> > diff --git a/Documentation/devicetree/bindings/mailbox/amd,zynqmp-pl- >> mbox-2.1.yaml b/Documentation/devicetree/bindings/mailbox/amd,zynqmp-pl- >> mbox-2.1.yaml >> > new file mode 100644 >> > index 000000000000..2cc0d106b888 >> > --- /dev/null >> > +++ b/Documentation/devicetree/bindings/mailbox/amd,zynqmp-pl-mbox-2.1.yaml >> > @@ -0,0 +1,74 @@ >> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> > +%YAML 1.2 >> > +--- >> > +$id: http://devicetree.org/schemas/mailbox/amd,zynqmp-pl-mbox-2.1.yaml# >> >> > +$schema: http://devicetree.org/meta-schemas/core.yaml# > devicetree.org/meta-schemas/core.yaml#> >> > + >> > +title: AMD Programmable Logic Mailbox IP >> > + >> > +maintainers: >> > + - Ben Levinsky >> > + >> > +description: | >> > + The AMD Programmable Logic Mailbox IP provides bidirectional message passing >> > + between two processor-facing interfaces. Each interface writes messages to >> > + a send FIFO and reads messages from a receive FIFO. The register aperture, >> > + interrupt, and clock described by a node belong to one processor-facing >> > + interface. Channel 0 represents transmit and channel 1 represents receive >> > + for that interface. >> > + >> > +properties: >> > + compatible: >> > + oneOf: >> > + - const: amd,zynqmp-pl-mbox-2.1 >> >> What is 2.1? Your SoC has different versions? > > 2.1 is the version of the Mailbox IP core in the Xilinx IP catalog > (Mailbox v2.1). It is not a SoC version. The IP is synthesized into the > programmable logic, so the same core is used on every SoC, and the SoC > names in the compatibles do not add information. > > In v2 I will use a single IP-versioned compatible, "xlnx,mailbox-2.1", > and drop the SoC-specific ones. This is also the compatible the Xilinx > device tree generator already emits for this IP. > Hi here is the reasoning behind the name: We use 'amd' vendor prefix for all new drivers & bindings. Also, there is dedicated IPI hardware which can be used as mailbox too, and we should distinguish it with this PL mailbox. So I that is included in the compatible string. (pl-mbox). If we are also to include SOC name as well (per compatible property guideline), then we should include one of the SOC name as well: So, I think 'amd,zynqmp-pl-mbox-2.1' is good. Krzysztof, are you okay with above name? The 2.1 is FPGA IP design version number and not the SOC version number. So in future let's say that FPGA IP design is improved then the name (pl-mbox) will remain same, but only version number will be updated i.e. (from 2.1 to 3.0). Is it okay if we explicitly mention this in the binding description? Thank You. >> >> > + - items: >> > + - enum: >> > + - amd,versal-pl-mbox-2.1 >> > + - amd,versal-net-pl-mbox-2.1 >> > + - amd,versal2-pl-mbox-2.1 >> > + - const: amd,zynqmp-pl-mbox-2.1 >> > + >> > + reg: >> > + maxItems: 1 >> > + >> > + interrupts: >> > + maxItems: 1 >> > + >> > + clocks: >> > + maxItems: 1 >> > + >> > + amd,mbox-pl-fifo-len: >> > + $ref: /schemas/types.yaml#/definitions/uint32 >> > + minimum: 16 >> > + maximum: 8192 >> > + default: 16 >> > + description: >> > + Depth of the send and receive FIFOs in 32-bit words, as configured by >> > + the C_MAILBOX_DEPTH parameter of the IP. Must match the configured >> > + depth. >> >> So you have multiple mailboxes per one soc different in this? > > Yes. The FIFO depth is chosen per IP instance when the design is > synthesized, so one design can contain several mailboxes with different > depths. The depth cannot be read from the registers, so the driver > needs it from the device tree to size its receive buffer and to limit > transmit messages. In v2 I will rename the property to > "xlnx,mailbox-depth", after the IP parameter, and state this in its Please use 'amd' as vendor prefix, also keep pl in the property name: i.e. 'amd,pl-mailbox-depth'. > description. > > Thanks, > Ben > >> >> Best regards, >> Krzysztof >> >