* [PATCH v2 1/7] dt-bindings: loongarch: Add CPU bindings for LoongArch
2023-08-15 8:50 [PATCH v2 0/7] LoongArch: Add built-in dtb support Binbin Zhou
@ 2023-08-15 8:50 ` Binbin Zhou
2023-08-15 14:07 ` Conor Dooley
2023-08-15 8:50 ` [PATCH v2 2/7] dt-bindings: loongarch: Add Loongson SoC boards compatibles Binbin Zhou
` (5 subsequent siblings)
6 siblings, 1 reply; 23+ messages in thread
From: Binbin Zhou @ 2023-08-15 8:50 UTC (permalink / raw)
To: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree
Cc: Huacai Chen, loongson-kernel, Xuerui Wang, loongarch, Jiaxun Yang,
Hongliang Wang, Binbin Zhou
Add the available CPUs in LoongArch binding with DT schema format using
json-schema.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
.../devicetree/bindings/loongarch/cpus.yaml | 60 +++++++++++++++++++
1 file changed, 60 insertions(+)
create mode 100644 Documentation/devicetree/bindings/loongarch/cpus.yaml
diff --git a/Documentation/devicetree/bindings/loongarch/cpus.yaml b/Documentation/devicetree/bindings/loongarch/cpus.yaml
new file mode 100644
index 000000000000..ee3fe09e53dc
--- /dev/null
+++ b/Documentation/devicetree/bindings/loongarch/cpus.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/loongarch/cpus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LoongArch CPUs
+
+maintainers:
+ - Binbin Zhou <zhoubinbin@loongson.cn>
+
+description:
+ This document describes the list of LoongArch CPU cores that support FDT,
+ it describe the layout of CPUs in a system through the "cpus" node.
+
+properties:
+ compatible:
+ enum:
+ - loongson,la264
+ - loongson,la364
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ device_type: true
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/loongson,ls2k-clk.h>
+
+ cpus {
+ #size-cells = <0>;
+ #address-cells = <1>;
+
+ cpu@0 {
+ compatible = "loongson,la264";
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&clk LOONGSON2_NODE_CLK>;
+ };
+
+ cpu@1 {
+ compatible = "loongson,la264";
+ device_type = "cpu";
+ reg = <1>;
+ clocks = <&clk LOONGSON2_NODE_CLK>;
+ };
+ };
+
+...
--
2.39.3
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 1/7] dt-bindings: loongarch: Add CPU bindings for LoongArch
2023-08-15 8:50 ` [PATCH v2 1/7] dt-bindings: loongarch: Add CPU bindings for LoongArch Binbin Zhou
@ 2023-08-15 14:07 ` Conor Dooley
2023-08-16 6:37 ` Binbin Zhou
0 siblings, 1 reply; 23+ messages in thread
From: Conor Dooley @ 2023-08-15 14:07 UTC (permalink / raw)
To: Binbin Zhou
Cc: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree, Huacai Chen, loongson-kernel,
Xuerui Wang, loongarch, Jiaxun Yang, Hongliang Wang
[-- Attachment #1: Type: text/plain, Size: 2198 bytes --]
On Tue, Aug 15, 2023 at 04:50:46PM +0800, Binbin Zhou wrote:
> Add the available CPUs in LoongArch binding with DT schema format using
> json-schema.
>
> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> ---
> .../devicetree/bindings/loongarch/cpus.yaml | 60 +++++++++++++++++++
> 1 file changed, 60 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/loongarch/cpus.yaml
>
> diff --git a/Documentation/devicetree/bindings/loongarch/cpus.yaml b/Documentation/devicetree/bindings/loongarch/cpus.yaml
> new file mode 100644
> index 000000000000..ee3fe09e53dc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/loongarch/cpus.yaml
> @@ -0,0 +1,60 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/loongarch/cpus.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: LoongArch CPUs
> +
> +maintainers:
> + - Binbin Zhou <zhoubinbin@loongson.cn>
> +
> +description:
> + This document describes the list of LoongArch CPU cores that support FDT,
> + it describe the layout of CPUs in a system through the "cpus" node.
> +
> +properties:
> + compatible:
> + enum:
> + - loongson,la264
> + - loongson,la364
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + device_type: true
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> +
> +additionalProperties: false
How come you didn't add the reference to the common cpu schema?
Thanks,
Conor.
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/loongson,ls2k-clk.h>
> +
> + cpus {
> + #size-cells = <0>;
> + #address-cells = <1>;
> +
> + cpu@0 {
> + compatible = "loongson,la264";
> + device_type = "cpu";
> + reg = <0>;
> + clocks = <&clk LOONGSON2_NODE_CLK>;
> + };
> +
> + cpu@1 {
> + compatible = "loongson,la264";
> + device_type = "cpu";
> + reg = <1>;
> + clocks = <&clk LOONGSON2_NODE_CLK>;
> + };
> + };
> +
> +...
> --
> 2.39.3
>
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^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v2 1/7] dt-bindings: loongarch: Add CPU bindings for LoongArch
2023-08-15 14:07 ` Conor Dooley
@ 2023-08-16 6:37 ` Binbin Zhou
2023-08-16 6:50 ` Conor Dooley
0 siblings, 1 reply; 23+ messages in thread
From: Binbin Zhou @ 2023-08-16 6:37 UTC (permalink / raw)
To: Conor Dooley
Cc: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree, Huacai Chen, loongson-kernel,
Xuerui Wang, loongarch, Jiaxun Yang, Hongliang Wang
Hi Conor:
Thanks for the reply.
On Tue, Aug 15, 2023 at 10:07 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Tue, Aug 15, 2023 at 04:50:46PM +0800, Binbin Zhou wrote:
> > Add the available CPUs in LoongArch binding with DT schema format using
> > json-schema.
> >
> > Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> > ---
> > .../devicetree/bindings/loongarch/cpus.yaml | 60 +++++++++++++++++++
> > 1 file changed, 60 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/loongarch/cpus.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/loongarch/cpus.yaml b/Documentation/devicetree/bindings/loongarch/cpus.yaml
> > new file mode 100644
> > index 000000000000..ee3fe09e53dc
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/loongarch/cpus.yaml
> > @@ -0,0 +1,60 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/loongarch/cpus.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: LoongArch CPUs
> > +
> > +maintainers:
> > + - Binbin Zhou <zhoubinbin@loongson.cn>
> > +
> > +description:
> > + This document describes the list of LoongArch CPU cores that support FDT,
> > + it describe the layout of CPUs in a system through the "cpus" node.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - loongson,la264
> > + - loongson,la364
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + device_type: true
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > +
> > +additionalProperties: false
>
> How come you didn't add the reference to the common cpu schema?
Do you mean:
allOf:
- $ref: /schemas/cpu.yaml#
Sorry, the file started out as a copy of mips/arm and then the related
content, really didn't notice that part.
I will check again.
Also, shouldn't "additionalProperties: false" be changed to
"unevaluatedProperties: false" synchronously?
Thanks.
Binbin
>
> Thanks,
> Conor.
>
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/loongson,ls2k-clk.h>
> > +
> > + cpus {
> > + #size-cells = <0>;
> > + #address-cells = <1>;
> > +
> > + cpu@0 {
> > + compatible = "loongson,la264";
> > + device_type = "cpu";
> > + reg = <0>;
> > + clocks = <&clk LOONGSON2_NODE_CLK>;
> > + };
> > +
> > + cpu@1 {
> > + compatible = "loongson,la264";
> > + device_type = "cpu";
> > + reg = <1>;
> > + clocks = <&clk LOONGSON2_NODE_CLK>;
> > + };
> > + };
> > +
> > +...
> > --
> > 2.39.3
> >
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v2 1/7] dt-bindings: loongarch: Add CPU bindings for LoongArch
2023-08-16 6:37 ` Binbin Zhou
@ 2023-08-16 6:50 ` Conor Dooley
0 siblings, 0 replies; 23+ messages in thread
From: Conor Dooley @ 2023-08-16 6:50 UTC (permalink / raw)
To: Binbin Zhou
Cc: Conor Dooley, Binbin Zhou, Huacai Chen, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree, Huacai Chen,
loongson-kernel, Xuerui Wang, loongarch, Jiaxun Yang,
Hongliang Wang
[-- Attachment #1: Type: text/plain, Size: 2343 bytes --]
On Wed, Aug 16, 2023 at 02:37:43PM +0800, Binbin Zhou wrote:
> Hi Conor:
>
> Thanks for the reply.
>
> On Tue, Aug 15, 2023 at 10:07 PM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Tue, Aug 15, 2023 at 04:50:46PM +0800, Binbin Zhou wrote:
> > > Add the available CPUs in LoongArch binding with DT schema format using
> > > json-schema.
> > >
> > > Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> > > ---
> > > .../devicetree/bindings/loongarch/cpus.yaml | 60 +++++++++++++++++++
> > > 1 file changed, 60 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/loongarch/cpus.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/loongarch/cpus.yaml b/Documentation/devicetree/bindings/loongarch/cpus.yaml
> > > new file mode 100644
> > > index 000000000000..ee3fe09e53dc
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/loongarch/cpus.yaml
> > > @@ -0,0 +1,60 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/loongarch/cpus.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: LoongArch CPUs
> > > +
> > > +maintainers:
> > > + - Binbin Zhou <zhoubinbin@loongson.cn>
> > > +
> > > +description:
> > > + This document describes the list of LoongArch CPU cores that support FDT,
> > > + it describe the layout of CPUs in a system through the "cpus" node.
> > > +
> > > +properties:
> > > + compatible:
> > > + enum:
> > > + - loongson,la264
> > > + - loongson,la364
> > > +
> > > + reg:
> > > + maxItems: 1
> > > +
> > > + clocks:
> > > + maxItems: 1
> > > +
> > > + device_type: true
> > > +
> > > +required:
> > > + - compatible
> > > + - reg
> > > + - clocks
> > > +
> > > +additionalProperties: false
> >
> > How come you didn't add the reference to the common cpu schema?
>
> Do you mean:
> allOf:
> - $ref: /schemas/cpu.yaml#
Yes.
> Sorry, the file started out as a copy of mips/arm and then the related
> content, really didn't notice that part.
> I will check again.
>
> Also, shouldn't "additionalProperties: false" be changed to
> "unevaluatedProperties: false" synchronously?
To actually make use of the properties from there, yeah.
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^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 2/7] dt-bindings: loongarch: Add Loongson SoC boards compatibles
2023-08-15 8:50 [PATCH v2 0/7] LoongArch: Add built-in dtb support Binbin Zhou
2023-08-15 8:50 ` [PATCH v2 1/7] dt-bindings: loongarch: Add CPU bindings for LoongArch Binbin Zhou
@ 2023-08-15 8:50 ` Binbin Zhou
2023-08-15 14:13 ` Conor Dooley
2023-08-15 14:49 ` Krzysztof Kozlowski
2023-08-15 8:50 ` [PATCH v2 3/7] LoongArch: Allow device trees to be built into the kernel Binbin Zhou
` (4 subsequent siblings)
6 siblings, 2 replies; 23+ messages in thread
From: Binbin Zhou @ 2023-08-15 8:50 UTC (permalink / raw)
To: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree
Cc: Huacai Chen, loongson-kernel, Xuerui Wang, loongarch, Jiaxun Yang,
Hongliang Wang, Binbin Zhou
Add Loongson SoC boards binding with DT schema format using json-schema.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
.../devicetree/bindings/loongarch/boards.yaml | 34 +++++++++++++++++++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/loongarch/boards.yaml
diff --git a/Documentation/devicetree/bindings/loongarch/boards.yaml b/Documentation/devicetree/bindings/loongarch/boards.yaml
new file mode 100644
index 000000000000..5092314b7a52
--- /dev/null
+++ b/Documentation/devicetree/bindings/loongarch/boards.yaml
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/loongarch/boards.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson SoC-based boards
+
+maintainers:
+ - Binbin Zhou <zhoubinbin@loongson.cn>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: Loongson-2K0500 processor based boards
+ items:
+ - const: loongson,ls2k0500-ref
+ - const: loongson,ls2k0500
+
+ - description: Loongson-2K1000 processor based boards
+ items:
+ - const: loongson,ls2k1000-ref
+ - const: loongson,ls2k1000
+
+ - description: Loongson-2K2000 processor based boards
+ items:
+ - const: loongson,ls2k2000-ref
+ - const: loongson,ls2k2000
+
+additionalProperties: true
+
+...
--
2.39.3
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 2/7] dt-bindings: loongarch: Add Loongson SoC boards compatibles
2023-08-15 8:50 ` [PATCH v2 2/7] dt-bindings: loongarch: Add Loongson SoC boards compatibles Binbin Zhou
@ 2023-08-15 14:13 ` Conor Dooley
2023-08-17 6:16 ` Binbin Zhou
2023-08-15 14:49 ` Krzysztof Kozlowski
1 sibling, 1 reply; 23+ messages in thread
From: Conor Dooley @ 2023-08-15 14:13 UTC (permalink / raw)
To: Binbin Zhou
Cc: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree, Huacai Chen, loongson-kernel,
Xuerui Wang, loongarch, Jiaxun Yang, Hongliang Wang
[-- Attachment #1: Type: text/plain, Size: 1748 bytes --]
On Tue, Aug 15, 2023 at 04:50:47PM +0800, Binbin Zhou wrote:
> Add Loongson SoC boards binding with DT schema format using json-schema.
>
> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> ---
> .../devicetree/bindings/loongarch/boards.yaml | 34 +++++++++++++++++++
> 1 file changed, 34 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/loongarch/boards.yaml
>
> diff --git a/Documentation/devicetree/bindings/loongarch/boards.yaml b/Documentation/devicetree/bindings/loongarch/boards.yaml
> new file mode 100644
> index 000000000000..5092314b7a52
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/loongarch/boards.yaml
> @@ -0,0 +1,34 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/loongarch/boards.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Loongson SoC-based boards
> +
> +maintainers:
> + - Binbin Zhou <zhoubinbin@loongson.cn>
> +
> +properties:
> + $nodename:
> + const: '/'
> + compatible:
> + oneOf:
> + - description: Loongson-2K0500 processor based boards
> + items:
> + - const: loongson,ls2k0500-ref
> + - const: loongson,ls2k0500
> +
> + - description: Loongson-2K1000 processor based boards
> + items:
> + - const: loongson,ls2k1000-ref
> + - const: loongson,ls2k1000
> +
> + - description: Loongson-2K2000 processor based boards
> + items:
> + - const: loongson,ls2k2000-ref
> + - const: loongson,ls2k2000
Do all of these SoCs just have a single reference/dev board?
> +
> +additionalProperties: true
> +
> +...
> --
> 2.39.3
>
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/7] dt-bindings: loongarch: Add Loongson SoC boards compatibles
2023-08-15 14:13 ` Conor Dooley
@ 2023-08-17 6:16 ` Binbin Zhou
2023-08-17 8:44 ` Conor Dooley
0 siblings, 1 reply; 23+ messages in thread
From: Binbin Zhou @ 2023-08-17 6:16 UTC (permalink / raw)
To: Conor Dooley
Cc: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree, Huacai Chen, loongson-kernel,
Xuerui Wang, loongarch, Jiaxun Yang, Hongliang Wang
Hi Conor:
Thanks for your reply.
On Tue, Aug 15, 2023 at 10:13 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Tue, Aug 15, 2023 at 04:50:47PM +0800, Binbin Zhou wrote:
> > Add Loongson SoC boards binding with DT schema format using json-schema.
> >
> > Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> > ---
> > .../devicetree/bindings/loongarch/boards.yaml | 34 +++++++++++++++++++
> > 1 file changed, 34 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/loongarch/boards.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/loongarch/boards.yaml b/Documentation/devicetree/bindings/loongarch/boards.yaml
> > new file mode 100644
> > index 000000000000..5092314b7a52
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/loongarch/boards.yaml
> > @@ -0,0 +1,34 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/loongarch/boards.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Loongson SoC-based boards
> > +
> > +maintainers:
> > + - Binbin Zhou <zhoubinbin@loongson.cn>
> > +
> > +properties:
> > + $nodename:
> > + const: '/'
> > + compatible:
> > + oneOf:
> > + - description: Loongson-2K0500 processor based boards
> > + items:
> > + - const: loongson,ls2k0500-ref
> > + - const: loongson,ls2k0500
> > +
> > + - description: Loongson-2K1000 processor based boards
> > + items:
> > + - const: loongson,ls2k1000-ref
> > + - const: loongson,ls2k1000
> > +
> > + - description: Loongson-2K2000 processor based boards
> > + items:
> > + - const: loongson,ls2k2000-ref
> > + - const: loongson,ls2k2000
>
> Do all of these SoCs just have a single reference/dev board?
Yes, I have development boards for each Soc on hand now, and it has a
relatively complete interface. My original idea was to use the
development boards as examples to show you the Loongson-2K Soc.
I'm sure more boards will be added in the future.
Thanks.
Binbin
>
> > +
> > +additionalProperties: true
> > +
> > +...
> > --
> > 2.39.3
> >
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/7] dt-bindings: loongarch: Add Loongson SoC boards compatibles
2023-08-17 6:16 ` Binbin Zhou
@ 2023-08-17 8:44 ` Conor Dooley
2023-08-17 8:46 ` Conor Dooley
0 siblings, 1 reply; 23+ messages in thread
From: Conor Dooley @ 2023-08-17 8:44 UTC (permalink / raw)
To: Binbin Zhou
Cc: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree, Huacai Chen, loongson-kernel,
Xuerui Wang, loongarch, Jiaxun Yang, Hongliang Wang
[-- Attachment #1: Type: text/plain, Size: 2458 bytes --]
On Thu, Aug 17, 2023 at 02:16:13PM +0800, Binbin Zhou wrote:
> Hi Conor:
>
> Thanks for your reply.
>
> On Tue, Aug 15, 2023 at 10:13 PM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Tue, Aug 15, 2023 at 04:50:47PM +0800, Binbin Zhou wrote:
> > > Add Loongson SoC boards binding with DT schema format using json-schema.
> > >
> > > Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> > > ---
> > > .../devicetree/bindings/loongarch/boards.yaml | 34 +++++++++++++++++++
> > > 1 file changed, 34 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/loongarch/boards.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/loongarch/boards.yaml b/Documentation/devicetree/bindings/loongarch/boards.yaml
> > > new file mode 100644
> > > index 000000000000..5092314b7a52
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/loongarch/boards.yaml
> > > @@ -0,0 +1,34 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/loongarch/boards.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Loongson SoC-based boards
> > > +
> > > +maintainers:
> > > + - Binbin Zhou <zhoubinbin@loongson.cn>
> > > +
> > > +properties:
> > > + $nodename:
> > > + const: '/'
> > > + compatible:
> > > + oneOf:
> > > + - description: Loongson-2K0500 processor based boards
> > > + items:
> > > + - const: loongson,ls2k0500-ref
> > > + - const: loongson,ls2k0500
> > > +
> > > + - description: Loongson-2K1000 processor based boards
> > > + items:
> > > + - const: loongson,ls2k1000-ref
> > > + - const: loongson,ls2k1000
> > > +
> > > + - description: Loongson-2K2000 processor based boards
> > > + items:
> > > + - const: loongson,ls2k2000-ref
> > > + - const: loongson,ls2k2000
> >
> > Do all of these SoCs just have a single reference/dev board?
>
> Yes, I have development boards for each Soc on hand now, and it has a
> relatively complete interface. My original idea was to use the
> development boards as examples to show you the Loongson-2K Soc.
> I'm sure more boards will be added in the future.
My reason for asking was that "-ref" is quite generic, but if there is
only one reference board produced by Loongson that's not a problem.
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/7] dt-bindings: loongarch: Add Loongson SoC boards compatibles
2023-08-17 8:44 ` Conor Dooley
@ 2023-08-17 8:46 ` Conor Dooley
0 siblings, 0 replies; 23+ messages in thread
From: Conor Dooley @ 2023-08-17 8:46 UTC (permalink / raw)
To: Binbin Zhou
Cc: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree, Huacai Chen, loongson-kernel,
Xuerui Wang, loongarch, Jiaxun Yang, Hongliang Wang
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On Thu, Aug 17, 2023 at 09:44:16AM +0100, Conor Dooley wrote:
> On Thu, Aug 17, 2023 at 02:16:13PM +0800, Binbin Zhou wrote:
> > Hi Conor:
> >
> > Thanks for your reply.
> >
> > On Tue, Aug 15, 2023 at 10:13 PM Conor Dooley <conor@kernel.org> wrote:
> > >
> > > On Tue, Aug 15, 2023 at 04:50:47PM +0800, Binbin Zhou wrote:
> > > > Add Loongson SoC boards binding with DT schema format using json-schema.
> > > >
> > > > Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> > > > ---
> > > > .../devicetree/bindings/loongarch/boards.yaml | 34 +++++++++++++++++++
> > > > 1 file changed, 34 insertions(+)
> > > > create mode 100644 Documentation/devicetree/bindings/loongarch/boards.yaml
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/loongarch/boards.yaml b/Documentation/devicetree/bindings/loongarch/boards.yaml
> > > > new file mode 100644
> > > > index 000000000000..5092314b7a52
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/loongarch/boards.yaml
> > > > @@ -0,0 +1,34 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > +%YAML 1.2
> > > > +---
> > > > +$id: http://devicetree.org/schemas/loongarch/boards.yaml#
> > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > +
> > > > +title: Loongson SoC-based boards
> > > > +
> > > > +maintainers:
> > > > + - Binbin Zhou <zhoubinbin@loongson.cn>
> > > > +
> > > > +properties:
> > > > + $nodename:
> > > > + const: '/'
> > > > + compatible:
> > > > + oneOf:
> > > > + - description: Loongson-2K0500 processor based boards
> > > > + items:
> > > > + - const: loongson,ls2k0500-ref
> > > > + - const: loongson,ls2k0500
> > > > +
> > > > + - description: Loongson-2K1000 processor based boards
> > > > + items:
> > > > + - const: loongson,ls2k1000-ref
> > > > + - const: loongson,ls2k1000
> > > > +
> > > > + - description: Loongson-2K2000 processor based boards
> > > > + items:
> > > > + - const: loongson,ls2k2000-ref
> > > > + - const: loongson,ls2k2000
> > >
> > > Do all of these SoCs just have a single reference/dev board?
> >
> > Yes, I have development boards for each Soc on hand now, and it has a
> > relatively complete interface. My original idea was to use the
> > development boards as examples to show you the Loongson-2K Soc.
> > I'm sure more boards will be added in the future.
>
> My reason for asking was that "-ref" is quite generic, but if there is
> only one reference board produced by Loongson that's not a problem.
Whoops, I forgot to add this:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/7] dt-bindings: loongarch: Add Loongson SoC boards compatibles
2023-08-15 8:50 ` [PATCH v2 2/7] dt-bindings: loongarch: Add Loongson SoC boards compatibles Binbin Zhou
2023-08-15 14:13 ` Conor Dooley
@ 2023-08-15 14:49 ` Krzysztof Kozlowski
2023-08-17 6:24 ` Binbin Zhou
1 sibling, 1 reply; 23+ messages in thread
From: Krzysztof Kozlowski @ 2023-08-15 14:49 UTC (permalink / raw)
To: Binbin Zhou, Binbin Zhou, Huacai Chen, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree
Cc: Huacai Chen, loongson-kernel, Xuerui Wang, loongarch, Jiaxun Yang,
Hongliang Wang
On 15/08/2023 10:50, Binbin Zhou wrote:
> Add Loongson SoC boards binding with DT schema format using json-schema.
>
> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> ---
> .../devicetree/bindings/loongarch/boards.yaml | 34 +++++++++++++++++++
> 1 file changed, 34 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/loongarch/boards.yaml
>
> diff --git a/Documentation/devicetree/bindings/loongarch/boards.yaml b/Documentation/devicetree/bindings/loongarch/boards.yaml
> new file mode 100644
> index 000000000000..5092314b7a52
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/loongarch/boards.yaml
> @@ -0,0 +1,34 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/loongarch/boards.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Loongson SoC-based boards
> +
> +maintainers:
> + - Binbin Zhou <zhoubinbin@loongson.cn>
> +
> +properties:
> + $nodename:
> + const: '/'
> + compatible:
> + oneOf:
> + - description: Loongson-2K0500 processor based boards
> + items:
> + - const: loongson,ls2k0500-ref
> + - const: loongson,ls2k0500
> +
> + - description: Loongson-2K1000 processor based boards
> + items:
> + - const: loongson,ls2k1000-ref
> + - const: loongson,ls2k1000
> +
> + - description: Loongson-2K2000 processor based boards
> + items:
> + - const: loongson,ls2k2000-ref
> + - const: loongson,ls2k2000
This probably is a sign all your bindings are using a bogus compatible.
You were using compatibles like loongson,ls2k-clk so your SoC cannot be
ls2k2000... or your compatible is bogus. The same for:
loongson,ls2k-pm, loongson,ls2k-dwmac, loongson,ls2k-i2c,
loongson,ls2k-chipid, loongson,ls2k-gpio
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/7] dt-bindings: loongarch: Add Loongson SoC boards compatibles
2023-08-15 14:49 ` Krzysztof Kozlowski
@ 2023-08-17 6:24 ` Binbin Zhou
0 siblings, 0 replies; 23+ messages in thread
From: Binbin Zhou @ 2023-08-17 6:24 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree, Huacai Chen, loongson-kernel,
Xuerui Wang, loongarch, Jiaxun Yang, Hongliang Wang
Hi Krzysztof:
Thanks for your reply.
On Tue, Aug 15, 2023 at 10:49 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 15/08/2023 10:50, Binbin Zhou wrote:
> > Add Loongson SoC boards binding with DT schema format using json-schema.
> >
> > Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> > ---
> > .../devicetree/bindings/loongarch/boards.yaml | 34 +++++++++++++++++++
> > 1 file changed, 34 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/loongarch/boards.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/loongarch/boards.yaml b/Documentation/devicetree/bindings/loongarch/boards.yaml
> > new file mode 100644
> > index 000000000000..5092314b7a52
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/loongarch/boards.yaml
> > @@ -0,0 +1,34 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/loongarch/boards.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Loongson SoC-based boards
> > +
> > +maintainers:
> > + - Binbin Zhou <zhoubinbin@loongson.cn>
> > +
> > +properties:
> > + $nodename:
> > + const: '/'
> > + compatible:
> > + oneOf:
> > + - description: Loongson-2K0500 processor based boards
> > + items:
> > + - const: loongson,ls2k0500-ref
> > + - const: loongson,ls2k0500
> > +
> > + - description: Loongson-2K1000 processor based boards
> > + items:
> > + - const: loongson,ls2k1000-ref
> > + - const: loongson,ls2k1000
> > +
> > + - description: Loongson-2K2000 processor based boards
> > + items:
> > + - const: loongson,ls2k2000-ref
> > + - const: loongson,ls2k2000
>
> This probably is a sign all your bindings are using a bogus compatible.
> You were using compatibles like loongson,ls2k-clk so your SoC cannot be
> ls2k2000... or your compatible is bogus. The same for:
> loongson,ls2k-pm, loongson,ls2k-dwmac, loongson,ls2k-i2c,
> loongson,ls2k-chipid, loongson,ls2k-gpio
>
I'm not sure I understand correctly, are you saying I should rename
all these ls2k-xx compatibles to Soc-based compatible?
For example, loongson,ls2k-i2c should be renamed to something like this:
loongson,ls2k0500-i2c, loongson,ls2k-i2c
loongson,ls2k1000-i2c, loongson,ls2k-i2c
loongson,ls2k2000-i2c, loongson,ls2k-i2c
Even if their driver code is no different.
Thanks.
Binbin
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 3/7] LoongArch: Allow device trees to be built into the kernel
2023-08-15 8:50 [PATCH v2 0/7] LoongArch: Add built-in dtb support Binbin Zhou
2023-08-15 8:50 ` [PATCH v2 1/7] dt-bindings: loongarch: Add CPU bindings for LoongArch Binbin Zhou
2023-08-15 8:50 ` [PATCH v2 2/7] dt-bindings: loongarch: Add Loongson SoC boards compatibles Binbin Zhou
@ 2023-08-15 8:50 ` Binbin Zhou
2023-08-15 8:51 ` [PATCH v2 4/7] LoongArch: dts: DeviceTree for Loongson-2K0500 Binbin Zhou
` (3 subsequent siblings)
6 siblings, 0 replies; 23+ messages in thread
From: Binbin Zhou @ 2023-08-15 8:50 UTC (permalink / raw)
To: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree
Cc: Huacai Chen, loongson-kernel, Xuerui Wang, loongarch, Jiaxun Yang,
Hongliang Wang, Binbin Zhou
Some systems do not provide a useful device tree to the kernel at boot
time. Let's keep a device tree table in the kernel, keyed by the dts
filename, containing the relevant DTBs.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
arch/loongarch/Kconfig | 16 ++++++++++++++++
arch/loongarch/Makefile | 10 ++++++++--
arch/loongarch/boot/dts/Makefile | 3 +--
arch/loongarch/kernel/setup.c | 9 +++++++--
4 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig
index 46b4c217da14..61febadd4fce 100644
--- a/arch/loongarch/Kconfig
+++ b/arch/loongarch/Kconfig
@@ -326,6 +326,22 @@ config 64KB_3LEVEL
endchoice
+config BUILTIN_DTB
+ bool "Enable builtin dtb in kernel"
+ depends on OF
+ help
+ Some systems do not provide a useful device tree to the kernel at boot
+ time. Let's keep a device tree table in the kernel, keyed by the dts
+ filename, containing the relevant DTBs.
+
+config BUILTIN_DTB_NAME
+ string "Source file for LoongArch builtin dtb"
+ depends on BUILTIN_DTB
+ help
+ Base name (without suffix, relative to arch/loongarch/boot/dts/)
+ for the DTS file that will be used to produce the DTB linked into the
+ kernel.
+
config CMDLINE
string "Built-in kernel command line"
help
diff --git a/arch/loongarch/Makefile b/arch/loongarch/Makefile
index fb0fada43197..abaa3df9fd6f 100644
--- a/arch/loongarch/Makefile
+++ b/arch/loongarch/Makefile
@@ -5,7 +5,8 @@
boot := arch/loongarch/boot
-KBUILD_DEFCONFIG := loongson3_defconfig
+KBUILD_DEFCONFIG := loongson3_defconfig
+KBUILD_DTBS := dtbs
image-name-y := vmlinux
image-name-$(CONFIG_EFI_ZBOOT) := vmlinuz
@@ -140,11 +141,14 @@ PHONY += vdso_install
vdso_install:
$(Q)$(MAKE) $(build)=arch/loongarch/vdso $@
-all: $(notdir $(KBUILD_IMAGE))
+all: $(notdir $(KBUILD_IMAGE)) $(KBUILD_DTBS)
vmlinux.elf vmlinux.efi vmlinuz.efi: vmlinux
$(Q)$(MAKE) $(build)=$(boot) $(bootvars-y) $(boot)/$@
+# device-trees
+core-y += arch/loongarch/boot/dts/
+
install:
$(Q)install -D -m 755 $(KBUILD_IMAGE) $(INSTALL_PATH)/$(image-name-y)-$(KERNELRELEASE)
$(Q)install -D -m 644 .config $(INSTALL_PATH)/config-$(KERNELRELEASE)
@@ -152,5 +156,7 @@ install:
define archhelp
echo ' install - install kernel into $(INSTALL_PATH)'
+ echo ' dtbs - Device-tree blobs for enabled boards'
+ echo ' dtbs_install - Install dtbs to $(INSTALL_DTBS_PATH)'
echo
endef
diff --git a/arch/loongarch/boot/dts/Makefile b/arch/loongarch/boot/dts/Makefile
index 5f1f55e911ad..1e24cdb5180a 100644
--- a/arch/loongarch/boot/dts/Makefile
+++ b/arch/loongarch/boot/dts/Makefile
@@ -1,4 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
-dtstree := $(srctree)/$(src)
-dtb-y := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts))
+obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_NAME))
diff --git a/arch/loongarch/kernel/setup.c b/arch/loongarch/kernel/setup.c
index 7783f0a3d742..e5008890beda 100644
--- a/arch/loongarch/kernel/setup.c
+++ b/arch/loongarch/kernel/setup.c
@@ -296,8 +296,13 @@ static void __init fdt_setup(void)
if (acpi_os_get_root_pointer())
return;
- /* Look for a device tree configuration table entry */
- fdt_pointer = efi_fdt_pointer();
+ /* We prefer to try to use built-in dtb, checking its legality first. */
+ if (!fdt_check_header(__dtb_start))
+ fdt_pointer = __dtb_start;
+ else
+ /* Fallback to efi dtb, when built-in dtb is not available. */
+ fdt_pointer = efi_fdt_pointer();
+
if (!fdt_pointer || fdt_check_header(fdt_pointer))
return;
--
2.39.3
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v2 4/7] LoongArch: dts: DeviceTree for Loongson-2K0500
2023-08-15 8:50 [PATCH v2 0/7] LoongArch: Add built-in dtb support Binbin Zhou
` (2 preceding siblings ...)
2023-08-15 8:50 ` [PATCH v2 3/7] LoongArch: Allow device trees to be built into the kernel Binbin Zhou
@ 2023-08-15 8:51 ` Binbin Zhou
2023-08-15 14:09 ` Conor Dooley
2023-08-15 14:48 ` Krzysztof Kozlowski
2023-08-15 8:51 ` [PATCH v2 5/7] LoongArch: dts: DeviceTree for Loongson-2K1000 Binbin Zhou
` (2 subsequent siblings)
6 siblings, 2 replies; 23+ messages in thread
From: Binbin Zhou @ 2023-08-15 8:51 UTC (permalink / raw)
To: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree
Cc: Huacai Chen, loongson-kernel, Xuerui Wang, loongarch, Jiaxun Yang,
Hongliang Wang, Binbin Zhou
Add DeviceTree file for Loongson-2K0500 processor, which integrates one
64-bit dual emission superscalar LA264 processor core.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
arch/loongarch/boot/dts/Makefile | 2 +
.../boot/dts/loongson-2k0500-ref.dts | 115 +++++++++
arch/loongarch/boot/dts/loongson-2k0500.dtsi | 244 ++++++++++++++++++
3 files changed, 361 insertions(+)
create mode 100644 arch/loongarch/boot/dts/loongson-2k0500-ref.dts
create mode 100644 arch/loongarch/boot/dts/loongson-2k0500.dtsi
diff --git a/arch/loongarch/boot/dts/Makefile b/arch/loongarch/boot/dts/Makefile
index 1e24cdb5180a..aa0b21d73d4e 100644
--- a/arch/loongarch/boot/dts/Makefile
+++ b/arch/loongarch/boot/dts/Makefile
@@ -1,3 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
+dtb-$(CONFIG_MACH_LOONGSON64) = loongson-2k0500-ref.dtb
+
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_NAME))
diff --git a/arch/loongarch/boot/dts/loongson-2k0500-ref.dts b/arch/loongarch/boot/dts/loongson-2k0500-ref.dts
new file mode 100644
index 000000000000..c89662e5a296
--- /dev/null
+++ b/arch/loongarch/boot/dts/loongson-2k0500-ref.dts
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Loongson Technology Corporation Limited
+ */
+
+/dts-v1/;
+
+#include "loongson-2k0500.dtsi"
+
+/ {
+ compatible = "loongson,ls2k0500-ref", "loongson,ls2k0500";
+ model = "Loongson-2K0500 Reference Board";
+
+ aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs = "earlycon";
+ };
+
+ cpu_clk: cpu-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <500000000>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "loongson,la264";
+ device_type = "cpu";
+ reg = <0x0>;
+ clocks = <&cpu_clk>;
+ };
+ };
+
+ memory@200000 {
+ device_type = "memory";
+ reg = <0x0 0x200000 0x0 0xee00000>, /* 238 MB at 2 MB */
+ <0x0 0x90000000 0x0 0x60000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x2000000>;
+ linux,cma-default;
+ };
+ };
+};
+
+&gmac0 {
+ status = "okay";
+
+ phy-mode = "rgmii";
+ bus_id = <0x0>;
+};
+
+&gmac1 {
+ status = "okay";
+
+ phy-mode = "rgmii";
+ bus_id = <0x1>;
+};
+
+&i2c0 {
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ eeprom@57{
+ compatible = "atmel,24c16";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&rtc0 {
+ status = "okay";
+};
diff --git a/arch/loongarch/boot/dts/loongson-2k0500.dtsi b/arch/loongarch/boot/dts/loongson-2k0500.dtsi
new file mode 100644
index 000000000000..e6f6476ab558
--- /dev/null
+++ b/arch/loongarch/boot/dts/loongson-2k0500.dtsi
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Loongson Technology Corporation Limited
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ref_100m: clock-ref-100m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "ref_100m";
+ };
+
+ cpuintc: interrupt-controller {
+ compatible = "loongson,cpu-interrupt-controller";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
+ bus@10000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>,
+ <0x0 0x2000000 0x0 0x2000000 0x0 0x2000000>,
+ <0x0 0x20000000 0x0 0x20000000 0x0 0x10000000>,
+ <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
+ <0xfe 0x0 0xfe 0x0 0x0 0x40000000>;
+
+ isa@16400000 {
+ compatible = "isa";
+ #size-cells = <1>;
+ #address-cells = <2>;
+ ranges = <1 0x0 0x0 0x16400000 0x4000>;
+ };
+
+ liointc0: interrupt-controller@1fe11400 {
+ compatible = "loongson,liointc-2.0";
+ reg = <0x0 0x1fe11400 0x0 0x40>,
+ <0x0 0x1fe11040 0x0 0x8>;
+ reg-names = "main", "isr0";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ interrupt-names = "int0";
+
+ loongson,parent_int_map = <0xffffffff>, /* int0 */
+ <0x00000000>, /* int1 */
+ <0x00000000>, /* int2 */
+ <0x00000000>; /* int3 */
+ };
+
+ liointc1: interrupt-controller@1fe11440 {
+ compatible = "loongson,liointc-2.0";
+ reg = <0x0 0x1fe11440 0x0 0x40>,
+ <0x0 0x1fe11048 0x0 0x8>;
+ reg-names = "main", "isr0";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <4>;
+ interrupt-names = "int2";
+
+ loongson,parent_int_map = <0x00000000>, /* int0 */
+ <0x00000000>, /* int1 */
+ <0xffffffff>, /* int2 */
+ <0x00000000>; /* int3 */
+ };
+
+ eiointc: interrupt-controller@1fe11600 {
+ compatible = "loongson,ls2k0500-eiointc";
+ reg = <0x0 0x1fe11600 0x0 0xea00>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <3>;
+ };
+
+ gmac0: ethernet@1f020000 {
+ compatible = "snps,dwmac-3.70a";
+ reg = <0x0 0x1f020000 0x0 0x10000>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ status = "disable";
+ };
+
+ gmac1: ethernet@1f030000 {
+ compatible = "snps,dwmac-3.70a";
+ reg = <0x0 0x1f030000 0x0 0x10000>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ status = "disable";
+ };
+
+ sata: sata@1f040000 {
+ compatible = "snps,spear-ahci";
+ reg = <0x0 0x1f040000 0x0 0x10000>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <75>;
+ status = "disable";
+ };
+
+ ehci0: usb@1f050000 {
+ compatible = "generic-ehci";
+ reg = <0x0 0x1f050000 0x0 0x8000>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <71>;
+ status = "disable";
+ };
+
+ ohci0: usb@1f058000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0x1f058000 0x0 0x8000>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <72>;
+ status = "disable";
+ };
+
+ clk: clock-controller@1fe10400 {
+ compatible = "loongson,ls2k-clk";
+ reg = <0x0 0x1fe10400 0x0 0x30>;
+ #clock-cells = <1>;
+ clocks = <&ref_100m>;
+ clock-names = "ref_100m";
+ status = "disabled";
+ };
+
+ uart0: serial@1ff40800 {
+ compatible = "ns16550a";
+ reg = <0x0 0x1ff40800 0x0 0x10>;
+ clock-frequency = <100000000>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <2>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ i2c0: i2c@1ff48000 {
+ compatible = "loongson,ls2k-i2c";
+ reg = <0x0 0x1ff48000 0x0 0x0800>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <14>;
+ status = "disabled";
+ };
+
+ i2c@1ff48800 {
+ compatible = "loongson,ls2k-i2c";
+ reg = <0x0 0x1ff48800 0x0 0x0800>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <15>;
+ status = "disabled";
+ };
+
+ i2c@1ff49000 {
+ compatible = "loongson,ls2k-i2c";
+ reg = <0x0 0x1ff49000 0x0 0x0800>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <16>;
+ status = "disabled";
+ };
+
+ i2c@1ff49800 {
+ compatible = "loongson,ls2k-i2c";
+ reg = <0x0 0x1ff49800 0x0 0x0800>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <17>;
+ status = "disabled";
+ };
+
+ i2c@1ff4a000 {
+ compatible = "loongson,ls2k-i2c";
+ reg = <0x0 0x1ff4a000 0x0 0x0800>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <18>;
+ status = "disabled";
+ };
+
+ i2c@1ff4a800 {
+ compatible = "loongson,ls2k-i2c";
+ reg = <0x0 0x1ff4a800 0x0 0x0800>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <19>;
+ status = "disabled";
+ };
+
+ rtc0: rtc@1ff6c100 {
+ compatible = "loongson,ls2k0500-rtc", "loongson,ls7a-rtc";
+ reg = <0x0 0x1ff6c100 0x0 0x100>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <35>;
+ status = "disabled";
+ };
+
+ pcie@1a000000 {
+ compatible = "loongson,ls2k-pci";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ reg = <0x0 0x1a000000 0x0 0x02000000>,
+ <0xfe 0x0 0x0 0x20000000>;
+
+ ranges = <0x2000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
+ <0x1000000 0x0 0x4000 0x0 0x16404000 0x0 0x4000>;
+
+ status = "disabled";
+
+ pcie@0,0 {
+ reg = <0x0000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupt-parent = <&eiointc>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &eiointc 81>;
+ ranges;
+ };
+
+ pcie@1,0 {
+ reg = <0x0800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupt-parent = <&eiointc>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &eiointc 82>;
+ ranges;
+ };
+ };
+ };
+};
--
2.39.3
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 4/7] LoongArch: dts: DeviceTree for Loongson-2K0500
2023-08-15 8:51 ` [PATCH v2 4/7] LoongArch: dts: DeviceTree for Loongson-2K0500 Binbin Zhou
@ 2023-08-15 14:09 ` Conor Dooley
2023-08-17 3:15 ` Binbin Zhou
2023-08-15 14:48 ` Krzysztof Kozlowski
1 sibling, 1 reply; 23+ messages in thread
From: Conor Dooley @ 2023-08-15 14:09 UTC (permalink / raw)
To: Binbin Zhou
Cc: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree, Huacai Chen, loongson-kernel,
Xuerui Wang, loongarch, Jiaxun Yang, Hongliang Wang
[-- Attachment #1: Type: text/plain, Size: 2423 bytes --]
On Tue, Aug 15, 2023 at 04:51:10PM +0800, Binbin Zhou wrote:
> Add DeviceTree file for Loongson-2K0500 processor, which integrates one
> 64-bit dual emission superscalar LA264 processor core.
>
> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> ---
> arch/loongarch/boot/dts/Makefile | 2 +
> .../boot/dts/loongson-2k0500-ref.dts | 115 +++++++++
> arch/loongarch/boot/dts/loongson-2k0500.dtsi | 244 ++++++++++++++++++
> 3 files changed, 361 insertions(+)
> create mode 100644 arch/loongarch/boot/dts/loongson-2k0500-ref.dts
> create mode 100644 arch/loongarch/boot/dts/loongson-2k0500.dtsi
>
> diff --git a/arch/loongarch/boot/dts/Makefile b/arch/loongarch/boot/dts/Makefile
> index 1e24cdb5180a..aa0b21d73d4e 100644
> --- a/arch/loongarch/boot/dts/Makefile
> +++ b/arch/loongarch/boot/dts/Makefile
> @@ -1,3 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0-only
>
> +dtb-$(CONFIG_MACH_LOONGSON64) = loongson-2k0500-ref.dtb
> +
> obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_NAME))
> diff --git a/arch/loongarch/boot/dts/loongson-2k0500-ref.dts b/arch/loongarch/boot/dts/loongson-2k0500-ref.dts
> new file mode 100644
> index 000000000000..c89662e5a296
> --- /dev/null
> +++ b/arch/loongarch/boot/dts/loongson-2k0500-ref.dts
> @@ -0,0 +1,115 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2023 Loongson Technology Corporation Limited
> + */
> +
> +/dts-v1/;
> +
> +#include "loongson-2k0500.dtsi"
> +
> +/ {
> + compatible = "loongson,ls2k0500-ref", "loongson,ls2k0500";
> + model = "Loongson-2K0500 Reference Board";
> +
> + aliases {
> + ethernet0 = &gmac0;
> + ethernet1 = &gmac1;
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + bootargs = "earlycon";
> + };
> +
> + cpu_clk: cpu-clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <500000000>;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + };
> + };
> +
> + cpu0: cpu@0 {
> + compatible = "loongson,la264";
> + device_type = "cpu";
> + reg = <0x0>;
> + clocks = <&cpu_clk>;
> + };
> + };
I've not read this whole patch, but from a glance - why is the cpu node
in the board file, not the soc one?
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^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v2 4/7] LoongArch: dts: DeviceTree for Loongson-2K0500
2023-08-15 14:09 ` Conor Dooley
@ 2023-08-17 3:15 ` Binbin Zhou
0 siblings, 0 replies; 23+ messages in thread
From: Binbin Zhou @ 2023-08-17 3:15 UTC (permalink / raw)
To: Conor Dooley
Cc: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree, Huacai Chen, loongson-kernel,
Xuerui Wang, loongarch, Jiaxun Yang, Hongliang Wang
Hi Conor:
Thanks for your reply.
On Tue, Aug 15, 2023 at 10:09 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Tue, Aug 15, 2023 at 04:51:10PM +0800, Binbin Zhou wrote:
> > Add DeviceTree file for Loongson-2K0500 processor, which integrates one
> > 64-bit dual emission superscalar LA264 processor core.
> >
> > Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> > ---
> > arch/loongarch/boot/dts/Makefile | 2 +
> > .../boot/dts/loongson-2k0500-ref.dts | 115 +++++++++
> > arch/loongarch/boot/dts/loongson-2k0500.dtsi | 244 ++++++++++++++++++
> > 3 files changed, 361 insertions(+)
> > create mode 100644 arch/loongarch/boot/dts/loongson-2k0500-ref.dts
> > create mode 100644 arch/loongarch/boot/dts/loongson-2k0500.dtsi
> >
> > diff --git a/arch/loongarch/boot/dts/Makefile b/arch/loongarch/boot/dts/Makefile
> > index 1e24cdb5180a..aa0b21d73d4e 100644
> > --- a/arch/loongarch/boot/dts/Makefile
> > +++ b/arch/loongarch/boot/dts/Makefile
> > @@ -1,3 +1,5 @@
> > # SPDX-License-Identifier: GPL-2.0-only
> >
> > +dtb-$(CONFIG_MACH_LOONGSON64) = loongson-2k0500-ref.dtb
> > +
> > obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_NAME))
> > diff --git a/arch/loongarch/boot/dts/loongson-2k0500-ref.dts b/arch/loongarch/boot/dts/loongson-2k0500-ref.dts
> > new file mode 100644
> > index 000000000000..c89662e5a296
> > --- /dev/null
> > +++ b/arch/loongarch/boot/dts/loongson-2k0500-ref.dts
> > @@ -0,0 +1,115 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2023 Loongson Technology Corporation Limited
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "loongson-2k0500.dtsi"
> > +
> > +/ {
> > + compatible = "loongson,ls2k0500-ref", "loongson,ls2k0500";
> > + model = "Loongson-2K0500 Reference Board";
> > +
> > + aliases {
> > + ethernet0 = &gmac0;
> > + ethernet1 = &gmac1;
> > + serial0 = &uart0;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0:115200n8";
> > + bootargs = "earlycon";
> > + };
> > +
> > + cpu_clk: cpu-clk {
> > + #clock-cells = <0>;
> > + compatible = "fixed-clock";
> > + clock-frequency = <500000000>;
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu-map {
> > + cluster0 {
> > + core0 {
> > + cpu = <&cpu0>;
> > + };
> > + };
> > + };
> > +
> > + cpu0: cpu@0 {
> > + compatible = "loongson,la264";
> > + device_type = "cpu";
> > + reg = <0x0>;
> > + clocks = <&cpu_clk>;
> > + };
> > + };
>
> I've not read this whole patch, but from a glance - why is the cpu node
> in the board file, not the soc one?
I'm very sorry, that was my mistake. cpu node should really be part of
soc, I'll put it in dtsi.
Thanks.
Binbin
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 4/7] LoongArch: dts: DeviceTree for Loongson-2K0500
2023-08-15 8:51 ` [PATCH v2 4/7] LoongArch: dts: DeviceTree for Loongson-2K0500 Binbin Zhou
2023-08-15 14:09 ` Conor Dooley
@ 2023-08-15 14:48 ` Krzysztof Kozlowski
2023-08-17 5:36 ` Binbin Zhou
1 sibling, 1 reply; 23+ messages in thread
From: Krzysztof Kozlowski @ 2023-08-15 14:48 UTC (permalink / raw)
To: Binbin Zhou, Binbin Zhou, Huacai Chen, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree
Cc: Huacai Chen, loongson-kernel, Xuerui Wang, loongarch, Jiaxun Yang,
Hongliang Wang
On 15/08/2023 10:51, Binbin Zhou wrote:
> Add DeviceTree file for Loongson-2K0500 processor, which integrates one
> 64-bit dual emission superscalar LA264 processor core.
>
> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> ---
> arch/loongarch/boot/dts/Makefile | 2 +
> .../boot/dts/loongson-2k0500-ref.dts | 115 +++++++++
> arch/loongarch/boot/dts/loongson-2k0500.dtsi | 244 ++++++++++++++++++
> 3 files changed, 361 insertions(+)
> create mode 100644 arch/loongarch/boot/dts/loongson-2k0500-ref.dts
> create mode 100644 arch/loongarch/boot/dts/loongson-2k0500.dtsi
>
> diff --git a/arch/loongarch/boot/dts/Makefile b/arch/loongarch/boot/dts/Makefile
> index 1e24cdb5180a..aa0b21d73d4e 100644
> --- a/arch/loongarch/boot/dts/Makefile
> +++ b/arch/loongarch/boot/dts/Makefile
> @@ -1,3 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0-only
>
> +dtb-$(CONFIG_MACH_LOONGSON64) = loongson-2k0500-ref.dtb
> +
> obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_NAME))
> diff --git a/arch/loongarch/boot/dts/loongson-2k0500-ref.dts b/arch/loongarch/boot/dts/loongson-2k0500-ref.dts
> new file mode 100644
> index 000000000000..c89662e5a296
> --- /dev/null
> +++ b/arch/loongarch/boot/dts/loongson-2k0500-ref.dts
> @@ -0,0 +1,115 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2023 Loongson Technology Corporation Limited
> + */
> +
> +/dts-v1/;
> +
> +#include "loongson-2k0500.dtsi"
> +
> +/ {
> + compatible = "loongson,ls2k0500-ref", "loongson,ls2k0500";
> + model = "Loongson-2K0500 Reference Board";
> +
> + aliases {
> + ethernet0 = &gmac0;
> + ethernet1 = &gmac1;
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + bootargs = "earlycon";
No earlycon in mainline. It's just development, not for products.
> + };
> +
> + cpu_clk: cpu-clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <500000000>;
Conor already commented on this...
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + };
> + };
> +
> + cpu0: cpu@0 {
> + compatible = "loongson,la264";
> + device_type = "cpu";
> + reg = <0x0>;
> + clocks = <&cpu_clk>;
> + };
> + };
> +
> + memory@200000 {
> + device_type = "memory";
> + reg = <0x0 0x200000 0x0 0xee00000>, /* 238 MB at 2 MB */
> + <0x0 0x90000000 0x0 0x60000000>;
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + linux,cma {
> + compatible = "shared-dma-pool";
> + reusable;
> + size = <0x0 0x2000000>;
> + linux,cma-default;
> + };
> + };
> +};
> +
> +&gmac0 {
> + status = "okay";
> +
> + phy-mode = "rgmii";
> + bus_id = <0x0>;
> +};
> +
> +&gmac1 {
> + status = "okay";
> +
> + phy-mode = "rgmii";
> + bus_id = <0x1>;
> +};
> +
> +&i2c0 {
> + status = "okay";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> + eeprom@57{
> + compatible = "atmel,24c16";
> + reg = <0x57>;
> + pagesize = <16>;
> + };
> +};
> +
> +&ehci0 {
> + status = "okay";
> +};
> +
> +&ohci0 {
> + status = "okay";
> +};
> +
> +&sata {
> + status = "okay";
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> +&rtc0 {
> + status = "okay";
> +};
> diff --git a/arch/loongarch/boot/dts/loongson-2k0500.dtsi b/arch/loongarch/boot/dts/loongson-2k0500.dtsi
> new file mode 100644
> index 000000000000..e6f6476ab558
> --- /dev/null
> +++ b/arch/loongarch/boot/dts/loongson-2k0500.dtsi
> @@ -0,0 +1,244 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2023 Loongson Technology Corporation Limited
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + ref_100m: clock-ref-100m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + clock-output-names = "ref_100m";
> + };
> +
> + cpuintc: interrupt-controller {
> + compatible = "loongson,cpu-interrupt-controller";
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + };
> +
> + bus@10000000 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>,
> + <0x0 0x2000000 0x0 0x2000000 0x0 0x2000000>,
> + <0x0 0x20000000 0x0 0x20000000 0x0 0x10000000>,
> + <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
> + <0xfe 0x0 0xfe 0x0 0x0 0x40000000>;
> +
> + isa@16400000 {
> + compatible = "isa";
> + #size-cells = <1>;
> + #address-cells = <2>;
> + ranges = <1 0x0 0x0 0x16400000 0x4000>;
> + };
> +
> + liointc0: interrupt-controller@1fe11400 {
> + compatible = "loongson,liointc-2.0";
> + reg = <0x0 0x1fe11400 0x0 0x40>,
> + <0x0 0x1fe11040 0x0 0x8>;
> + reg-names = "main", "isr0";
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&cpuintc>;
> + interrupts = <2>;
> + interrupt-names = "int0";
> +
> + loongson,parent_int_map = <0xffffffff>, /* int0 */
> + <0x00000000>, /* int1 */
> + <0x00000000>, /* int2 */
> + <0x00000000>; /* int3 */
> + };
> +
> + liointc1: interrupt-controller@1fe11440 {
> + compatible = "loongson,liointc-2.0";
> + reg = <0x0 0x1fe11440 0x0 0x40>,
> + <0x0 0x1fe11048 0x0 0x8>;
> + reg-names = "main", "isr0";
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&cpuintc>;
> + interrupts = <4>;
> + interrupt-names = "int2";
> +
> + loongson,parent_int_map = <0x00000000>, /* int0 */
> + <0x00000000>, /* int1 */
> + <0xffffffff>, /* int2 */
> + <0x00000000>; /* int3 */
> + };
> +
> + eiointc: interrupt-controller@1fe11600 {
> + compatible = "loongson,ls2k0500-eiointc";
> + reg = <0x0 0x1fe11600 0x0 0xea00>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + interrupt-parent = <&cpuintc>;
> + interrupts = <3>;
> + };
> +
> + gmac0: ethernet@1f020000 {
> + compatible = "snps,dwmac-3.70a";
> + reg = <0x0 0x1f020000 0x0 0x10000>;
> + interrupt-parent = <&liointc0>;
> + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq";
> + status = "disable";
That's not a valid status. Run some basic checks on your DTS before
submitting it (dtbs_check W=1)
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v2 4/7] LoongArch: dts: DeviceTree for Loongson-2K0500
2023-08-15 14:48 ` Krzysztof Kozlowski
@ 2023-08-17 5:36 ` Binbin Zhou
0 siblings, 0 replies; 23+ messages in thread
From: Binbin Zhou @ 2023-08-17 5:36 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree, Huacai Chen, loongson-kernel,
Xuerui Wang, loongarch, Jiaxun Yang, Hongliang Wang
Hi Krzysztof:
Thanks for your reply.
On Tue, Aug 15, 2023 at 10:48 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 15/08/2023 10:51, Binbin Zhou wrote:
> > Add DeviceTree file for Loongson-2K0500 processor, which integrates one
> > 64-bit dual emission superscalar LA264 processor core.
> >
> > Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> > ---
> > arch/loongarch/boot/dts/Makefile | 2 +
> > .../boot/dts/loongson-2k0500-ref.dts | 115 +++++++++
> > arch/loongarch/boot/dts/loongson-2k0500.dtsi | 244 ++++++++++++++++++
> > 3 files changed, 361 insertions(+)
> > create mode 100644 arch/loongarch/boot/dts/loongson-2k0500-ref.dts
> > create mode 100644 arch/loongarch/boot/dts/loongson-2k0500.dtsi
> >
> > diff --git a/arch/loongarch/boot/dts/Makefile b/arch/loongarch/boot/dts/Makefile
> > index 1e24cdb5180a..aa0b21d73d4e 100644
> > --- a/arch/loongarch/boot/dts/Makefile
> > +++ b/arch/loongarch/boot/dts/Makefile
> > @@ -1,3 +1,5 @@
> > # SPDX-License-Identifier: GPL-2.0-only
> >
> > +dtb-$(CONFIG_MACH_LOONGSON64) = loongson-2k0500-ref.dtb
> > +
> > obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_NAME))
> > diff --git a/arch/loongarch/boot/dts/loongson-2k0500-ref.dts b/arch/loongarch/boot/dts/loongson-2k0500-ref.dts
> > new file mode 100644
> > index 000000000000..c89662e5a296
> > --- /dev/null
> > +++ b/arch/loongarch/boot/dts/loongson-2k0500-ref.dts
> > @@ -0,0 +1,115 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2023 Loongson Technology Corporation Limited
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "loongson-2k0500.dtsi"
> > +
> > +/ {
> > + compatible = "loongson,ls2k0500-ref", "loongson,ls2k0500";
> > + model = "Loongson-2K0500 Reference Board";
> > +
> > + aliases {
> > + ethernet0 = &gmac0;
> > + ethernet1 = &gmac1;
> > + serial0 = &uart0;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0:115200n8";
> > + bootargs = "earlycon";
>
> No earlycon in mainline. It's just development, not for products.
I got it, I'll recheck the other dts and delete them.
>
> > + };
> > +
> > + cpu_clk: cpu-clk {
> > + #clock-cells = <0>;
> > + compatible = "fixed-clock";
> > + clock-frequency = <500000000>;
>
> Conor already commented on this...
>
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu-map {
> > + cluster0 {
> > + core0 {
> > + cpu = <&cpu0>;
> > + };
> > + };
> > + };
> > +
> > + cpu0: cpu@0 {
> > + compatible = "loongson,la264";
> > + device_type = "cpu";
> > + reg = <0x0>;
> > + clocks = <&cpu_clk>;
> > + };
> > + };
> > +
> > + memory@200000 {
> > + device_type = "memory";
> > + reg = <0x0 0x200000 0x0 0xee00000>, /* 238 MB at 2 MB */
> > + <0x0 0x90000000 0x0 0x60000000>;
> > + };
> > +
> > + reserved-memory {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + linux,cma {
> > + compatible = "shared-dma-pool";
> > + reusable;
> > + size = <0x0 0x2000000>;
> > + linux,cma-default;
> > + };
> > + };
> > +};
> > +
> > +&gmac0 {
> > + status = "okay";
> > +
> > + phy-mode = "rgmii";
> > + bus_id = <0x0>;
> > +};
> > +
> > +&gmac1 {
> > + status = "okay";
> > +
> > + phy-mode = "rgmii";
> > + bus_id = <0x1>;
> > +};
> > +
> > +&i2c0 {
> > + status = "okay";
> > +
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + eeprom@57{
> > + compatible = "atmel,24c16";
> > + reg = <0x57>;
> > + pagesize = <16>;
> > + };
> > +};
> > +
> > +&ehci0 {
> > + status = "okay";
> > +};
> > +
> > +&ohci0 {
> > + status = "okay";
> > +};
> > +
> > +&sata {
> > + status = "okay";
> > +};
> > +
> > +&uart0 {
> > + status = "okay";
> > +};
> > +
> > +&rtc0 {
> > + status = "okay";
> > +};
> > diff --git a/arch/loongarch/boot/dts/loongson-2k0500.dtsi b/arch/loongarch/boot/dts/loongson-2k0500.dtsi
> > new file mode 100644
> > index 000000000000..e6f6476ab558
> > --- /dev/null
> > +++ b/arch/loongarch/boot/dts/loongson-2k0500.dtsi
> > @@ -0,0 +1,244 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2023 Loongson Technology Corporation Limited
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +/ {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + ref_100m: clock-ref-100m {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + clock-output-names = "ref_100m";
> > + };
> > +
> > + cpuintc: interrupt-controller {
> > + compatible = "loongson,cpu-interrupt-controller";
> > + #interrupt-cells = <1>;
> > + interrupt-controller;
> > + };
> > +
> > + bus@10000000 {
> > + compatible = "simple-bus";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>,
> > + <0x0 0x2000000 0x0 0x2000000 0x0 0x2000000>,
> > + <0x0 0x20000000 0x0 0x20000000 0x0 0x10000000>,
> > + <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
> > + <0xfe 0x0 0xfe 0x0 0x0 0x40000000>;
> > +
> > + isa@16400000 {
> > + compatible = "isa";
> > + #size-cells = <1>;
> > + #address-cells = <2>;
> > + ranges = <1 0x0 0x0 0x16400000 0x4000>;
> > + };
> > +
> > + liointc0: interrupt-controller@1fe11400 {
> > + compatible = "loongson,liointc-2.0";
> > + reg = <0x0 0x1fe11400 0x0 0x40>,
> > + <0x0 0x1fe11040 0x0 0x8>;
> > + reg-names = "main", "isr0";
> > +
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + interrupt-parent = <&cpuintc>;
> > + interrupts = <2>;
> > + interrupt-names = "int0";
> > +
> > + loongson,parent_int_map = <0xffffffff>, /* int0 */
> > + <0x00000000>, /* int1 */
> > + <0x00000000>, /* int2 */
> > + <0x00000000>; /* int3 */
> > + };
> > +
> > + liointc1: interrupt-controller@1fe11440 {
> > + compatible = "loongson,liointc-2.0";
> > + reg = <0x0 0x1fe11440 0x0 0x40>,
> > + <0x0 0x1fe11048 0x0 0x8>;
> > + reg-names = "main", "isr0";
> > +
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + interrupt-parent = <&cpuintc>;
> > + interrupts = <4>;
> > + interrupt-names = "int2";
> > +
> > + loongson,parent_int_map = <0x00000000>, /* int0 */
> > + <0x00000000>, /* int1 */
> > + <0xffffffff>, /* int2 */
> > + <0x00000000>; /* int3 */
> > + };
> > +
> > + eiointc: interrupt-controller@1fe11600 {
> > + compatible = "loongson,ls2k0500-eiointc";
> > + reg = <0x0 0x1fe11600 0x0 0xea00>;
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + interrupt-parent = <&cpuintc>;
> > + interrupts = <3>;
> > + };
> > +
> > + gmac0: ethernet@1f020000 {
> > + compatible = "snps,dwmac-3.70a";
> > + reg = <0x0 0x1f020000 0x0 0x10000>;
> > + interrupt-parent = <&liointc0>;
> > + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "macirq";
> > + status = "disable";
>
> That's not a valid status. Run some basic checks on your DTS before
> submitting it (dtbs_check W=1)
I actually checked them before committing (dtbs_check W=1), except for
the warning about liointc, this needs another patch to fix:
https://lore.kernel.org/all/20230815084713.1627520-1-zhoubinbin@loongson.cn/
Since mips Loongson-2k1000 is also needed for it, I'm submitting it separately.
Thanks.
Binbin
>
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 5/7] LoongArch: dts: DeviceTree for Loongson-2K1000
2023-08-15 8:50 [PATCH v2 0/7] LoongArch: Add built-in dtb support Binbin Zhou
` (3 preceding siblings ...)
2023-08-15 8:51 ` [PATCH v2 4/7] LoongArch: dts: DeviceTree for Loongson-2K0500 Binbin Zhou
@ 2023-08-15 8:51 ` Binbin Zhou
2023-08-15 14:56 ` Krzysztof Kozlowski
2023-08-15 8:51 ` [PATCH v2 6/7] LoongArch: dts: DeviceTree for Loongson-2K2000 Binbin Zhou
2023-08-15 8:51 ` [PATCH v2 7/7] LoongArch: Parsing CPU-related information from DTS Binbin Zhou
6 siblings, 1 reply; 23+ messages in thread
From: Binbin Zhou @ 2023-08-15 8:51 UTC (permalink / raw)
To: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree
Cc: Huacai Chen, loongson-kernel, Xuerui Wang, loongarch, Jiaxun Yang,
Hongliang Wang, Binbin Zhou
Add DeviceTree file for Loongson-2K1000 processor, which integrates two
64-bit dual emission superscalar LA264 processor cores.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
arch/loongarch/boot/dts/Makefile | 3 +-
.../boot/dts/loongson-2k1000-ref.dts | 217 +++++++++++
arch/loongarch/boot/dts/loongson-2k1000.dtsi | 345 ++++++++++++++++++
3 files changed, 564 insertions(+), 1 deletion(-)
create mode 100644 arch/loongarch/boot/dts/loongson-2k1000-ref.dts
create mode 100644 arch/loongarch/boot/dts/loongson-2k1000.dtsi
diff --git a/arch/loongarch/boot/dts/Makefile b/arch/loongarch/boot/dts/Makefile
index aa0b21d73d4e..dc0782315bed 100644
--- a/arch/loongarch/boot/dts/Makefile
+++ b/arch/loongarch/boot/dts/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
-dtb-$(CONFIG_MACH_LOONGSON64) = loongson-2k0500-ref.dtb
+dtb-$(CONFIG_MACH_LOONGSON64) = loongson-2k0500-ref.dtb \
+ loongson-2k1000-ref.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_NAME))
diff --git a/arch/loongarch/boot/dts/loongson-2k1000-ref.dts b/arch/loongarch/boot/dts/loongson-2k1000-ref.dts
new file mode 100644
index 000000000000..950a2df4e33f
--- /dev/null
+++ b/arch/loongarch/boot/dts/loongson-2k1000-ref.dts
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Loongson Technology Corporation Limited
+ */
+
+/dts-v1/;
+
+#include "loongson-2k1000.dtsi"
+
+/ {
+ compatible = "loongson,ls2k1000-ref", "loongson,ls2k1000";
+ model = "Loongson-2K1000 Reference Board";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs = "earlycon";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "loongson,la264";
+ device_type = "cpu";
+ reg= <0x0>;
+ clocks = <&clk LOONGSON2_NODE_CLK>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "loongson,la264";
+ device_type = "cpu";
+ reg = <0x1>;
+ clocks = <&clk LOONGSON2_NODE_CLK>;
+ };
+ };
+
+ memory@200000 {
+ device_type = "memory";
+ reg = <0x0 0x200000 0x0 0x6e00000>,
+ <0x0 0x08000000 0x0 0x7000000>,
+ <0x0 0x90000000 0x1 0xe0000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x2000000>;
+ linux,cma-default;
+ };
+ };
+
+ i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <5>; /* ~100 kHz */
+ status = "disabled";
+ };
+
+ i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ scl-gpios = <&gpio0 33 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 32 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <5>; /* ~100 kHz */
+ status = "disabled";
+ };
+};
+
+&gmac0 {
+ status = "okay";
+
+ phy-mode = "rgmii";
+ phy-handle = <&phy0>;
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&gmac1 {
+ status = "okay";
+
+ phy-mode = "rgmii";
+ phy-handle = <&phy1>;
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy1: ethernet-phy@1 {
+ reg = <16>;
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ pinctrl-0 = <&i2c0_pins_default>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ eeprom@57{
+ compatible = "atmel,24c16";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&clk {
+ status = "okay";
+};
+
+&rtc0 {
+ status = "okay";
+};
+
+&pctrl {
+ status = "okay";
+ sdio_pins_default: sdio-pins {
+ sdio-pinmux {
+ groups = "sdio";
+ function = "sdio";
+ };
+ sdio-det-pinmux {
+ groups = "pwm2";
+ function = "gpio";
+ };
+ };
+
+ pwm1_pins_default: pwm1-pins {
+ pinmux {
+ groups = "pwm1";
+ function = "pwm1";
+ };
+ };
+
+ pwm0_pins_default: pwm0-pins {
+ pinmux {
+ groups = "pwm0";
+ function = "pwm0";
+ };
+ };
+
+ i2c1_pins_default: i2c1-pins {
+ pinmux {
+ groups = "i2c1";
+ function = "i2c1";
+ };
+ };
+
+ i2c0_pins_default: i2c0-pins {
+ pinmux {
+ groups = "i2c0";
+ function = "i2c0";
+ };
+ };
+
+ nand_pins_default: nand-pins {
+ pinmux {
+ groups = "nand";
+ function = "nand";
+ };
+ };
+
+ hda_pins_default: hda-pins {
+ grp0-pinmux {
+ groups = "hda";
+ function = "hda";
+ };
+ grp1-pinmux {
+ groups = "i2s";
+ function = "gpio";
+ };
+ };
+};
diff --git a/arch/loongarch/boot/dts/loongson-2k1000.dtsi b/arch/loongarch/boot/dts/loongson-2k1000.dtsi
new file mode 100644
index 000000000000..fc3bb6368a5e
--- /dev/null
+++ b/arch/loongarch/boot/dts/loongson-2k1000.dtsi
@@ -0,0 +1,345 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Loongson Technology Corporation Limited
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/loongson,ls2k-clk.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ref_100m: clock-ref-100m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "ref_100m";
+ };
+
+ cpuintc: interrupt-controller {
+ compatible = "loongson,cpu-interrupt-controller";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
+ bus@10000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>,
+ <0x0 0x2000000 0x0 0x2000000 0x0 0x2000000>,
+ <0x0 0x20000000 0x0 0x20000000 0x0 0x10000000>,
+ <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
+ <0xfe 0x0 0xfe 0x0 0x0 0x40000000>;
+
+ dma-coherent;
+
+ liointc0: interrupt-controller@1fe01400 {
+ compatible = "loongson,liointc-2.0";
+ reg = <0x0 0x1fe01400 0x0 0x40>,
+ <0x0 0x1fe01040 0x0 0x8>,
+ <0x0 0x1fe01140 0x0 0x8>;
+ reg-names = "main", "isr0", "isr1";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ interrupt-names = "int0";
+ loongson,parent_int_map = <0xffffffff>, /* int0 */
+ <0x00000000>, /* int1 */
+ <0x00000000>, /* int2 */
+ <0x00000000>; /* int3 */
+ };
+
+ liointc1: interrupt-controller@1fe01440 {
+ compatible = "loongson,liointc-2.0";
+ reg = <0x0 0x1fe01440 0x0 0x40>,
+ <0x0 0x1fe01048 0x0 0x8>,
+ <0x0 0x1fe01148 0x0 0x8>;
+ reg-names = "main", "isr0", "isr1";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <3>;
+ interrupt-names = "int1";
+ loongson,parent_int_map = <0x00000000>, /* int0 */
+ <0xffffffff>, /* int1 */
+ <0x00000000>, /* int2 */
+ <0x00000000>; /* int3 */
+ };
+
+ global-utilities@1fe00000 {
+ compatible = "loongson,ls2k-chipid";
+ reg = <0x0 0x1fe00000 0x0 0x3ffc>;
+ little-endian;
+ };
+
+ pctrl: pinctrl@1fe00420 {
+ compatible = "loongson,ls2k-pinctrl";
+ reg = <0x0 0x1fe00420 0x0 0x18>;
+ status = "disabled";
+ };
+
+ clk: clock-controller@1fe00480 {
+ compatible = "loongson,ls2k-clk";
+ reg = <0x0 0x1fe00480 0x0 0x58>;
+ #clock-cells = <1>;
+ clocks = <&ref_100m>;
+ clock-names = "ref_100m";
+ status = "disabled";
+ };
+
+ gpio0: gpio@1fe00500 {
+ compatible = "loongson,ls2k-gpio";
+ reg = <0x0 0x1fe00500 0x0 0x38>;
+ ngpios = <64>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pctrl 0x0 0x0 15>,
+ <&pctrl 16 16 15>,
+ <&pctrl 32 32 10>,
+ <&pctrl 44 44 20>;
+ interrupt-parent = <&liointc1>;
+ interrupts = <28 IRQ_TYPE_LEVEL_HIGH>,
+ <29 IRQ_TYPE_LEVEL_HIGH>,
+ <30 IRQ_TYPE_LEVEL_HIGH>,
+ <30 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <>,
+ <>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ uart0: serial@1fe20000 {
+ compatible = "ns16550a";
+ reg = <0x0 0x1fe20000 0x0 0x10>;
+ clock-frequency = <125000000>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <0x0 IRQ_TYPE_LEVEL_HIGH>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ i2c2: i2c@1fe21000 {
+ compatible = "loongson,ls2k-i2c";
+ reg = <0x0 0x1fe21000 0x0 0x8>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@1fe21800 {
+ compatible = "loongson,ls2k-i2c";
+ reg = <0x0 0x1fe21800 0x0 0x8>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ rtc0: rtc@1fe27800 {
+ compatible = "loongson,ls2k1000-rtc";
+ reg = <0x0 0x1fe27800 0x0 0x100>;
+ interrupt-parent = <&liointc1>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ pcie@1a000000 {
+ compatible = "loongson,ls2k-pci";
+ device_type = "pci";
+ #size-cells = <2>;
+ #address-cells = <3>;
+
+ reg = <0x0 0x1a000000 0x0 0x02000000>,
+ <0xfe 0x0 0x0 0x20000000>;
+
+ ranges = <0x1000000 0x0 0x8000 0x0 0x18008000 0x0 0x8000>,
+ <0x2000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>; /* mem */
+
+ gmac0: ethernet@3,0 {
+ reg = <0x1800 0x0 0x0 0x0 0x0>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
+ <13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_lpi";
+ status = "disabled";
+ };
+
+ gmac1: ethernet@3,1 {
+ reg = <0x1900 0x0 0x0 0x0 0x0>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
+ <15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_lpi";
+ status = "disabled";
+ };
+
+ ehci0: usb@4,1 {
+ reg = <0x2100 0x0 0x0 0x0 0x0>;
+ interrupt-parent = <&liointc1>;
+ interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ ohci0: usb@4,2 {
+ reg = <0x2200 0x0 0x0 0x0 0x0>;
+ interrupt-parent = <&liointc1>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ display@6,0 {
+ reg = <0x3000 0x0 0x0 0x0 0x0>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ hda@7,0 {
+ reg = <0x3800 0x0 0x0 0x0 0x0>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ sata: sata@8,0 {
+ reg = <0x4000 0x0 0x0 0x0 0x0>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ pcie@9,0 {
+ reg = <0x4800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 0x0 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@a,0 {
+ reg = <0x5000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&liointc1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 1 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@b,0 {
+ reg = <0x5800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&liointc1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 2 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@c,0 {
+ reg = <0x6000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&liointc1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 3 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@d,0 {
+ reg = <0x6800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&liointc1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 4 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@e,0 {
+ reg = <0x7000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&liointc1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 5 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+ };
+ };
+};
--
2.39.3
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 5/7] LoongArch: dts: DeviceTree for Loongson-2K1000
2023-08-15 8:51 ` [PATCH v2 5/7] LoongArch: dts: DeviceTree for Loongson-2K1000 Binbin Zhou
@ 2023-08-15 14:56 ` Krzysztof Kozlowski
2023-08-17 6:41 ` Binbin Zhou
0 siblings, 1 reply; 23+ messages in thread
From: Krzysztof Kozlowski @ 2023-08-15 14:56 UTC (permalink / raw)
To: Binbin Zhou, Binbin Zhou, Huacai Chen, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree
Cc: Huacai Chen, loongson-kernel, Xuerui Wang, loongarch, Jiaxun Yang,
Hongliang Wang
On 15/08/2023 10:51, Binbin Zhou wrote:
> Add DeviceTree file for Loongson-2K1000 processor, which integrates two
> 64-bit dual emission superscalar LA264 processor cores.
>
> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> ---
> arch/loongarch/boot/dts/Makefile | 3 +-
> .../boot/dts/loongson-2k1000-ref.dts | 217 +++++++++++
> arch/loongarch/boot/dts/loongson-2k1000.dtsi | 345 ++++++++++++++++++
> 3 files changed, 564 insertions(+), 1 deletion(-)
> create mode 100644 arch/loongarch/boot/dts/loongson-2k1000-ref.dts
> create mode 100644 arch/loongarch/boot/dts/loongson-2k1000.dtsi
>
> diff --git a/arch/loongarch/boot/dts/Makefile b/arch/loongarch/boot/dts/Makefile
> index aa0b21d73d4e..dc0782315bed 100644
> --- a/arch/loongarch/boot/dts/Makefile
> +++ b/arch/loongarch/boot/dts/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0-only
>
> -dtb-$(CONFIG_MACH_LOONGSON64) = loongson-2k0500-ref.dtb
> +dtb-$(CONFIG_MACH_LOONGSON64) = loongson-2k0500-ref.dtb \
> + loongson-2k1000-ref.dtb
>
> obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_NAME))
> diff --git a/arch/loongarch/boot/dts/loongson-2k1000-ref.dts b/arch/loongarch/boot/dts/loongson-2k1000-ref.dts
> new file mode 100644
> index 000000000000..950a2df4e33f
> --- /dev/null
> +++ b/arch/loongarch/boot/dts/loongson-2k1000-ref.dts
> @@ -0,0 +1,217 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2023 Loongson Technology Corporation Limited
> + */
> +
> +/dts-v1/;
> +
> +#include "loongson-2k1000.dtsi"
> +
> +/ {
> + compatible = "loongson,ls2k1000-ref", "loongson,ls2k1000";
> + model = "Loongson-2K1000 Reference Board";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + bootargs = "earlycon";
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
> + cpu = <&cpu1>;
> + };
> + };
> + };
> +
> + cpu0: cpu@0 {
> + compatible = "loongson,la264";
> + device_type = "cpu";
> + reg= <0x0>;
> + clocks = <&clk LOONGSON2_NODE_CLK>;
> + };
> +
> + cpu1: cpu@1 {
> + compatible = "loongson,la264";
> + device_type = "cpu";
> + reg = <0x1>;
> + clocks = <&clk LOONGSON2_NODE_CLK>;
> + };
> + };
> +
> + memory@200000 {
> + device_type = "memory";
> + reg = <0x0 0x200000 0x0 0x6e00000>,
> + <0x0 0x08000000 0x0 0x7000000>,
> + <0x0 0x90000000 0x1 0xe0000000>;
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + linux,cma {
> + compatible = "shared-dma-pool";
> + reusable;
> + size = <0x0 0x2000000>;
> + linux,cma-default;
> + };
> + };
> +
> + i2c-gpio-0 {
> + compatible = "i2c-gpio";
> + scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + i2c-gpio,delay-us = <5>; /* ~100 kHz */
> + status = "disabled";
Disabled node in board, without comment providing a reason, is useless.
Drop the node or fix the status.
> + };
> +
> + i2c-gpio-1 {
> + compatible = "i2c-gpio";
> + scl-gpios = <&gpio0 33 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio0 32 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + i2c-gpio,delay-us = <5>; /* ~100 kHz */
> + status = "disabled";
Ditto
> + };
> +};
> +
> +&gmac0 {
> + status = "okay";
> +
> + phy-mode = "rgmii";
> + phy-handle = <&phy0>;
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "snps,dwmac-mdio";
compatible is always the first property.
> + phy0: ethernet-phy@0 {
> + reg = <0>;
> + };
> + };
> +};
> +
> +&gmac1 {
> + status = "okay";
> +
> + phy-mode = "rgmii";
> + phy-handle = <&phy1>;
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "snps,dwmac-mdio";
compatible is always the first property.
> + phy1: ethernet-phy@1 {
> + reg = <16>;
> + };
> + };
> +};
...
> +};
> diff --git a/arch/loongarch/boot/dts/loongson-2k1000.dtsi b/arch/loongarch/boot/dts/loongson-2k1000.dtsi
> new file mode 100644
> index 000000000000..fc3bb6368a5e
> --- /dev/null
> +++ b/arch/loongarch/boot/dts/loongson-2k1000.dtsi
> @@ -0,0 +1,345 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2023 Loongson Technology Corporation Limited
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/clock/loongson,ls2k-clk.h>
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + ref_100m: clock-ref-100m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + clock-output-names = "ref_100m";
> + };
> +
> + cpuintc: interrupt-controller {
> + compatible = "loongson,cpu-interrupt-controller";
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + };
> +
> + bus@10000000 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>,
> + <0x0 0x2000000 0x0 0x2000000 0x0 0x2000000>,
> + <0x0 0x20000000 0x0 0x20000000 0x0 0x10000000>,
> + <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
> + <0xfe 0x0 0xfe 0x0 0x0 0x40000000>;
> +
> + dma-coherent;
> +
> + liointc0: interrupt-controller@1fe01400 {
> + compatible = "loongson,liointc-2.0";
> + reg = <0x0 0x1fe01400 0x0 0x40>,
> + <0x0 0x1fe01040 0x0 0x8>,
> + <0x0 0x1fe01140 0x0 0x8>;
> + reg-names = "main", "isr0", "isr1";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&cpuintc>;
> + interrupts = <2>;
> + interrupt-names = "int0";
> + loongson,parent_int_map = <0xffffffff>, /* int0 */
> + <0x00000000>, /* int1 */
> + <0x00000000>, /* int2 */
> + <0x00000000>; /* int3 */
> + };
> +
> + liointc1: interrupt-controller@1fe01440 {
> + compatible = "loongson,liointc-2.0";
> + reg = <0x0 0x1fe01440 0x0 0x40>,
> + <0x0 0x1fe01048 0x0 0x8>,
> + <0x0 0x1fe01148 0x0 0x8>;
> + reg-names = "main", "isr0", "isr1";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&cpuintc>;
> + interrupts = <3>;
> + interrupt-names = "int1";
> + loongson,parent_int_map = <0x00000000>, /* int0 */
> + <0xffffffff>, /* int1 */
> + <0x00000000>, /* int2 */
> + <0x00000000>; /* int3 */
> + };
> +
> + global-utilities@1fe00000 {
> + compatible = "loongson,ls2k-chipid";
> + reg = <0x0 0x1fe00000 0x0 0x3ffc>;
> + little-endian;
> + };
> +
> + pctrl: pinctrl@1fe00420 {
> + compatible = "loongson,ls2k-pinctrl";
> + reg = <0x0 0x1fe00420 0x0 0x18>;
> + status = "disabled";
> + };
> +
> + clk: clock-controller@1fe00480 {
> + compatible = "loongson,ls2k-clk";
> + reg = <0x0 0x1fe00480 0x0 0x58>;
> + #clock-cells = <1>;
> + clocks = <&ref_100m>;
> + clock-names = "ref_100m";
> + status = "disabled";
> + };
> +
> + gpio0: gpio@1fe00500 {
> + compatible = "loongson,ls2k-gpio";
> + reg = <0x0 0x1fe00500 0x0 0x38>;
> + ngpios = <64>;
> + #gpio-cells = <2>;
> + gpio-controller;
> + gpio-ranges = <&pctrl 0x0 0x0 15>,
> + <&pctrl 16 16 15>,
> + <&pctrl 32 32 10>,
> + <&pctrl 44 44 20>;
> + interrupt-parent = <&liointc1>;
> + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>,
> + <29 IRQ_TYPE_LEVEL_HIGH>,
> + <30 IRQ_TYPE_LEVEL_HIGH>,
> + <30 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <>,
> + <>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + uart0: serial@1fe20000 {
> + compatible = "ns16550a";
> + reg = <0x0 0x1fe20000 0x0 0x10>;
> + clock-frequency = <125000000>;
> + interrupt-parent = <&liointc0>;
> + interrupts = <0x0 IRQ_TYPE_LEVEL_HIGH>;
> + no-loopback-test;
> + status = "disabled";
> + };
> +
> + i2c2: i2c@1fe21000 {
> + compatible = "loongson,ls2k-i2c";
> + reg = <0x0 0x1fe21000 0x0 0x8>;
> + interrupt-parent = <&liointc0>;
> + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + i2c3: i2c@1fe21800 {
> + compatible = "loongson,ls2k-i2c";
> + reg = <0x0 0x1fe21800 0x0 0x8>;
> + interrupt-parent = <&liointc0>;
> + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + rtc0: rtc@1fe27800 {
> + compatible = "loongson,ls2k1000-rtc";
> + reg = <0x0 0x1fe27800 0x0 0x100>;
> + interrupt-parent = <&liointc1>;
> + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + pcie@1a000000 {
> + compatible = "loongson,ls2k-pci";
> + device_type = "pci";
> + #size-cells = <2>;
> + #address-cells = <3>;
> +
> + reg = <0x0 0x1a000000 0x0 0x02000000>,
> + <0xfe 0x0 0x0 0x20000000>;
> +
> + ranges = <0x1000000 0x0 0x8000 0x0 0x18008000 0x0 0x8000>,
> + <0x2000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>; /* mem */
> +
> + gmac0: ethernet@3,0 {
> + reg = <0x1800 0x0 0x0 0x0 0x0>;
> + interrupt-parent = <&liointc0>;
> + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
> + <13 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq", "eth_lpi";
> + status = "disabled";
> + };
> +
> + gmac1: ethernet@3,1 {
> + reg = <0x1900 0x0 0x0 0x0 0x0>;
> + interrupt-parent = <&liointc0>;
> + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
> + <15 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq", "eth_lpi";
> + status = "disabled";
> + };
> +
> + ehci0: usb@4,1 {
> + reg = <0x2100 0x0 0x0 0x0 0x0>;
> + interrupt-parent = <&liointc1>;
> + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
All these PCI devices are part of SoC? The SoC?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v2 5/7] LoongArch: dts: DeviceTree for Loongson-2K1000
2023-08-15 14:56 ` Krzysztof Kozlowski
@ 2023-08-17 6:41 ` Binbin Zhou
0 siblings, 0 replies; 23+ messages in thread
From: Binbin Zhou @ 2023-08-17 6:41 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree, Huacai Chen, loongson-kernel,
Xuerui Wang, loongarch, Jiaxun Yang, Hongliang Wang
Hi Krzysztof:
Thanks for your reply.
On Tue, Aug 15, 2023 at 10:56 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 15/08/2023 10:51, Binbin Zhou wrote:
> > Add DeviceTree file for Loongson-2K1000 processor, which integrates two
> > 64-bit dual emission superscalar LA264 processor cores.
> >
> > Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> > ---
> > arch/loongarch/boot/dts/Makefile | 3 +-
> > .../boot/dts/loongson-2k1000-ref.dts | 217 +++++++++++
> > arch/loongarch/boot/dts/loongson-2k1000.dtsi | 345 ++++++++++++++++++
> > 3 files changed, 564 insertions(+), 1 deletion(-)
> > create mode 100644 arch/loongarch/boot/dts/loongson-2k1000-ref.dts
> > create mode 100644 arch/loongarch/boot/dts/loongson-2k1000.dtsi
> >
> > diff --git a/arch/loongarch/boot/dts/Makefile b/arch/loongarch/boot/dts/Makefile
> > index aa0b21d73d4e..dc0782315bed 100644
> > --- a/arch/loongarch/boot/dts/Makefile
> > +++ b/arch/loongarch/boot/dts/Makefile
> > @@ -1,5 +1,6 @@
> > # SPDX-License-Identifier: GPL-2.0-only
> >
> > -dtb-$(CONFIG_MACH_LOONGSON64) = loongson-2k0500-ref.dtb
> > +dtb-$(CONFIG_MACH_LOONGSON64) = loongson-2k0500-ref.dtb \
> > + loongson-2k1000-ref.dtb
> >
> > obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_NAME))
> > diff --git a/arch/loongarch/boot/dts/loongson-2k1000-ref.dts b/arch/loongarch/boot/dts/loongson-2k1000-ref.dts
> > new file mode 100644
> > index 000000000000..950a2df4e33f
> > --- /dev/null
> > +++ b/arch/loongarch/boot/dts/loongson-2k1000-ref.dts
> > @@ -0,0 +1,217 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2023 Loongson Technology Corporation Limited
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "loongson-2k1000.dtsi"
> > +
> > +/ {
> > + compatible = "loongson,ls2k1000-ref", "loongson,ls2k1000";
> > + model = "Loongson-2K1000 Reference Board";
> > +
> > + aliases {
> > + serial0 = &uart0;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0:115200n8";
> > + bootargs = "earlycon";
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu-map {
> > + cluster0 {
> > + core0 {
> > + cpu = <&cpu0>;
> > + };
> > + core1 {
> > + cpu = <&cpu1>;
> > + };
> > + };
> > + };
> > +
> > + cpu0: cpu@0 {
> > + compatible = "loongson,la264";
> > + device_type = "cpu";
> > + reg= <0x0>;
> > + clocks = <&clk LOONGSON2_NODE_CLK>;
> > + };
> > +
> > + cpu1: cpu@1 {
> > + compatible = "loongson,la264";
> > + device_type = "cpu";
> > + reg = <0x1>;
> > + clocks = <&clk LOONGSON2_NODE_CLK>;
> > + };
> > + };
> > +
> > + memory@200000 {
> > + device_type = "memory";
> > + reg = <0x0 0x200000 0x0 0x6e00000>,
> > + <0x0 0x08000000 0x0 0x7000000>,
> > + <0x0 0x90000000 0x1 0xe0000000>;
> > + };
> > +
> > + reserved-memory {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + linux,cma {
> > + compatible = "shared-dma-pool";
> > + reusable;
> > + size = <0x0 0x2000000>;
> > + linux,cma-default;
> > + };
> > + };
> > +
> > + i2c-gpio-0 {
> > + compatible = "i2c-gpio";
> > + scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> > + sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> > + i2c-gpio,delay-us = <5>; /* ~100 kHz */
> > + status = "disabled";
>
> Disabled node in board, without comment providing a reason, is useless.
> Drop the node or fix the status.
I got it, I will check it again.
>
> > + };
> > +
> > + i2c-gpio-1 {
> > + compatible = "i2c-gpio";
> > + scl-gpios = <&gpio0 33 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> > + sda-gpios = <&gpio0 32 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> > + i2c-gpio,delay-us = <5>; /* ~100 kHz */
> > + status = "disabled";
>
> Ditto
>
> > + };
> > +};
> > +
> > +&gmac0 {
> > + status = "okay";
> > +
> > + phy-mode = "rgmii";
> > + phy-handle = <&phy0>;
> > + mdio {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "snps,dwmac-mdio";
>
> compatible is always the first property.
OK...
>
> > + phy0: ethernet-phy@0 {
> > + reg = <0>;
> > + };
> > + };
> > +};
> > +
> > +&gmac1 {
> > + status = "okay";
> > +
> > + phy-mode = "rgmii";
> > + phy-handle = <&phy1>;
> > + mdio {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "snps,dwmac-mdio";
>
> compatible is always the first property.
>
> > + phy1: ethernet-phy@1 {
> > + reg = <16>;
> > + };
> > + };
> > +};
>
> ...
>
> > +};
> > diff --git a/arch/loongarch/boot/dts/loongson-2k1000.dtsi b/arch/loongarch/boot/dts/loongson-2k1000.dtsi
> > new file mode 100644
> > index 000000000000..fc3bb6368a5e
> > --- /dev/null
> > +++ b/arch/loongarch/boot/dts/loongson-2k1000.dtsi
> > @@ -0,0 +1,345 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2023 Loongson Technology Corporation Limited
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/clock/loongson,ls2k-clk.h>
> > +#include <dt-bindings/gpio/gpio.h>
> > +
> > +/ {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + ref_100m: clock-ref-100m {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + clock-output-names = "ref_100m";
> > + };
> > +
> > + cpuintc: interrupt-controller {
> > + compatible = "loongson,cpu-interrupt-controller";
> > + #interrupt-cells = <1>;
> > + interrupt-controller;
> > + };
> > +
> > + bus@10000000 {
> > + compatible = "simple-bus";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>,
> > + <0x0 0x2000000 0x0 0x2000000 0x0 0x2000000>,
> > + <0x0 0x20000000 0x0 0x20000000 0x0 0x10000000>,
> > + <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
> > + <0xfe 0x0 0xfe 0x0 0x0 0x40000000>;
> > +
> > + dma-coherent;
> > +
> > + liointc0: interrupt-controller@1fe01400 {
> > + compatible = "loongson,liointc-2.0";
> > + reg = <0x0 0x1fe01400 0x0 0x40>,
> > + <0x0 0x1fe01040 0x0 0x8>,
> > + <0x0 0x1fe01140 0x0 0x8>;
> > + reg-names = "main", "isr0", "isr1";
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + interrupt-parent = <&cpuintc>;
> > + interrupts = <2>;
> > + interrupt-names = "int0";
> > + loongson,parent_int_map = <0xffffffff>, /* int0 */
> > + <0x00000000>, /* int1 */
> > + <0x00000000>, /* int2 */
> > + <0x00000000>; /* int3 */
> > + };
> > +
> > + liointc1: interrupt-controller@1fe01440 {
> > + compatible = "loongson,liointc-2.0";
> > + reg = <0x0 0x1fe01440 0x0 0x40>,
> > + <0x0 0x1fe01048 0x0 0x8>,
> > + <0x0 0x1fe01148 0x0 0x8>;
> > + reg-names = "main", "isr0", "isr1";
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + interrupt-parent = <&cpuintc>;
> > + interrupts = <3>;
> > + interrupt-names = "int1";
> > + loongson,parent_int_map = <0x00000000>, /* int0 */
> > + <0xffffffff>, /* int1 */
> > + <0x00000000>, /* int2 */
> > + <0x00000000>; /* int3 */
> > + };
> > +
> > + global-utilities@1fe00000 {
> > + compatible = "loongson,ls2k-chipid";
> > + reg = <0x0 0x1fe00000 0x0 0x3ffc>;
> > + little-endian;
> > + };
> > +
> > + pctrl: pinctrl@1fe00420 {
> > + compatible = "loongson,ls2k-pinctrl";
> > + reg = <0x0 0x1fe00420 0x0 0x18>;
> > + status = "disabled";
> > + };
> > +
> > + clk: clock-controller@1fe00480 {
> > + compatible = "loongson,ls2k-clk";
> > + reg = <0x0 0x1fe00480 0x0 0x58>;
> > + #clock-cells = <1>;
> > + clocks = <&ref_100m>;
> > + clock-names = "ref_100m";
> > + status = "disabled";
> > + };
> > +
> > + gpio0: gpio@1fe00500 {
> > + compatible = "loongson,ls2k-gpio";
> > + reg = <0x0 0x1fe00500 0x0 0x38>;
> > + ngpios = <64>;
> > + #gpio-cells = <2>;
> > + gpio-controller;
> > + gpio-ranges = <&pctrl 0x0 0x0 15>,
> > + <&pctrl 16 16 15>,
> > + <&pctrl 32 32 10>,
> > + <&pctrl 44 44 20>;
> > + interrupt-parent = <&liointc1>;
> > + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>,
> > + <29 IRQ_TYPE_LEVEL_HIGH>,
> > + <30 IRQ_TYPE_LEVEL_HIGH>,
> > + <30 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <26 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <>,
> > + <>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>,
> > + <27 IRQ_TYPE_LEVEL_HIGH>;
> > + };
> > +
> > + uart0: serial@1fe20000 {
> > + compatible = "ns16550a";
> > + reg = <0x0 0x1fe20000 0x0 0x10>;
> > + clock-frequency = <125000000>;
> > + interrupt-parent = <&liointc0>;
> > + interrupts = <0x0 IRQ_TYPE_LEVEL_HIGH>;
> > + no-loopback-test;
> > + status = "disabled";
> > + };
> > +
> > + i2c2: i2c@1fe21000 {
> > + compatible = "loongson,ls2k-i2c";
> > + reg = <0x0 0x1fe21000 0x0 0x8>;
> > + interrupt-parent = <&liointc0>;
> > + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + };
> > +
> > + i2c3: i2c@1fe21800 {
> > + compatible = "loongson,ls2k-i2c";
> > + reg = <0x0 0x1fe21800 0x0 0x8>;
> > + interrupt-parent = <&liointc0>;
> > + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + };
> > +
> > + rtc0: rtc@1fe27800 {
> > + compatible = "loongson,ls2k1000-rtc";
> > + reg = <0x0 0x1fe27800 0x0 0x100>;
> > + interrupt-parent = <&liointc1>;
> > + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + };
> > +
> > + pcie@1a000000 {
> > + compatible = "loongson,ls2k-pci";
> > + device_type = "pci";
> > + #size-cells = <2>;
> > + #address-cells = <3>;
> > +
> > + reg = <0x0 0x1a000000 0x0 0x02000000>,
> > + <0xfe 0x0 0x0 0x20000000>;
> > +
> > + ranges = <0x1000000 0x0 0x8000 0x0 0x18008000 0x0 0x8000>,
> > + <0x2000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>; /* mem */
> > +
> > + gmac0: ethernet@3,0 {
> > + reg = <0x1800 0x0 0x0 0x0 0x0>;
> > + interrupt-parent = <&liointc0>;
> > + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
> > + <13 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "macirq", "eth_lpi";
> > + status = "disabled";
> > + };
> > +
> > + gmac1: ethernet@3,1 {
> > + reg = <0x1900 0x0 0x0 0x0 0x0>;
> > + interrupt-parent = <&liointc0>;
> > + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
> > + <15 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "macirq", "eth_lpi";
> > + status = "disabled";
> > + };
> > +
> > + ehci0: usb@4,1 {
> > + reg = <0x2100 0x0 0x0 0x0 0x0>;
> > + interrupt-parent = <&liointc1>;
> > + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
>
>
> All these PCI devices are part of SoC? The SoC?
Yes, these PCI devices are SoC on-chip integrated.
They are connected to the IO interconnect module via a multi-stage
interconnect bus.
Thanks.
Binbin
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 6/7] LoongArch: dts: DeviceTree for Loongson-2K2000
2023-08-15 8:50 [PATCH v2 0/7] LoongArch: Add built-in dtb support Binbin Zhou
` (4 preceding siblings ...)
2023-08-15 8:51 ` [PATCH v2 5/7] LoongArch: dts: DeviceTree for Loongson-2K1000 Binbin Zhou
@ 2023-08-15 8:51 ` Binbin Zhou
2023-08-15 8:51 ` [PATCH v2 7/7] LoongArch: Parsing CPU-related information from DTS Binbin Zhou
6 siblings, 0 replies; 23+ messages in thread
From: Binbin Zhou @ 2023-08-15 8:51 UTC (permalink / raw)
To: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree
Cc: Huacai Chen, loongson-kernel, Xuerui Wang, loongarch, Jiaxun Yang,
Hongliang Wang, Binbin Zhou
Add DeviceTree file for Loongson-2K2000 processor, which integrates two
64-bit triple emission superscalar LA364 processor cores.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
arch/loongarch/boot/dts/Makefile | 3 +-
.../boot/dts/loongson-2k2000-ref.dts | 89 ++++++
arch/loongarch/boot/dts/loongson-2k2000.dtsi | 257 ++++++++++++++++++
3 files changed, 348 insertions(+), 1 deletion(-)
create mode 100644 arch/loongarch/boot/dts/loongson-2k2000-ref.dts
create mode 100644 arch/loongarch/boot/dts/loongson-2k2000.dtsi
diff --git a/arch/loongarch/boot/dts/Makefile b/arch/loongarch/boot/dts/Makefile
index dc0782315bed..c019d6676f7e 100644
--- a/arch/loongarch/boot/dts/Makefile
+++ b/arch/loongarch/boot/dts/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
dtb-$(CONFIG_MACH_LOONGSON64) = loongson-2k0500-ref.dtb \
- loongson-2k1000-ref.dtb
+ loongson-2k1000-ref.dtb \
+ loongson-2k2000-ref.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_NAME))
diff --git a/arch/loongarch/boot/dts/loongson-2k2000-ref.dts b/arch/loongarch/boot/dts/loongson-2k2000-ref.dts
new file mode 100644
index 000000000000..7543e3664ac8
--- /dev/null
+++ b/arch/loongarch/boot/dts/loongson-2k2000-ref.dts
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Loongson Technology Corporation Limited
+ */
+
+/dts-v1/;
+
+#include "loongson-2k2000.dtsi"
+
+/ {
+ compatible = "loongson,ls2k2000-ref", "loongson,ls2k2000";
+ model = "Loongson-2K2000 Reference Board";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs = "earlycon";
+ };
+
+ cpu_clk: cpu-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1200000000>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@1 {
+ compatible = "loongson,la364";
+ device_type = "cpu";
+ reg = <0x0>;
+ clocks = <&cpu_clk>;
+ };
+
+ cpu1: cpu@2 {
+ compatible = "loongson,la364";
+ device_type = "cpu";
+ reg = <0x1>;
+ clocks = <&cpu_clk>;
+ };
+ };
+
+ memory@200000 {
+ device_type = "memory";
+ reg = <0x0 0x200000 0x0 0xee00000>, /* 238 MB at 2 MB */
+ <0x0 0x90000000 0x0 0x70000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x2000000>;
+ linux,cma-default;
+ };
+ };
+};
+
+&sata {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&rtc0 {
+ status = "okay";
+};
diff --git a/arch/loongarch/boot/dts/loongson-2k2000.dtsi b/arch/loongarch/boot/dts/loongson-2k2000.dtsi
new file mode 100644
index 000000000000..f0959163f677
--- /dev/null
+++ b/arch/loongarch/boot/dts/loongson-2k2000.dtsi
@@ -0,0 +1,257 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Loongson Technology Corporation Limited
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpuintc: interrupt-controller {
+ compatible = "loongson,cpu-interrupt-controller";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
+ bus@10000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>,
+ <0x0 0x2000000 0x0 0x2000000 0x0 0x2000000>,
+ <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
+ <0xfe 0x0 0xfe 0x0 0x0 0x40000000>;
+
+ liointc: interrupt-controller@1fe01400 {
+ compatible = "loongson,liointc-2.0";
+ reg = <0x0 0x1fe01400 0x0 0x40>,
+ <0x0 0x1fe01440 0x0 0x8>,
+ <0x0 0x1fe01448 0x0 0x8>;
+ reg-names = "main", "isr0", "isr1";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ interrupt-names = "int0";
+ loongson,parent_int_map = <0xffffffff>, /* int0 */
+ <0x00000000>, /* int1 */
+ <0x00000000>, /* int2 */
+ <0x00000000>; /* int3 */
+ };
+
+ eiointc: interrupt-controller@1fe01600 {
+ compatible = "loongson,ls2k2000-eiointc";
+ reg = <0x0 0x1fe01600 0x0 0xea00>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <3>;
+ };
+
+ pic: interrupt-controller@10000000 {
+ compatible = "loongson,pch-pic-1.0";
+ reg = <0x0 0x10000000 0x0 0x400>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ loongson,pic-base-vec = <0>;
+ interrupt-parent = <&eiointc>;
+ };
+
+ msi: msi-controller@1fe01140 {
+ compatible = "loongson,pch-msi-1.0";
+ reg = <0x0 0x1fe01140 0x0 0x8>;
+ msi-controller;
+ loongson,msi-base-vec = <64>;
+ loongson,msi-num-vecs = <192>;
+ interrupt-parent = <&eiointc>;
+ };
+
+ rtc0: rtc@100d0100 {
+ compatible = "loongson,ls2k2000-rtc", "loongson,ls7a-rtc";
+ reg = <0x0 0x100d0100 0x0 0x100>;
+ interrupt-parent = <&pic>;
+ interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart0: serial@1fe001e0 {
+ compatible = "ns16550a";
+ reg = <0x0 0x1fe001e0 0x0 0x10>;
+ clock-frequency = <100000000>;
+ interrupt-parent = <&liointc>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ pcie@1a000000 {
+ compatible = "loongson,ls2k-pci";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ reg = <0x0 0x1a000000 0x0 0x02000000>,
+ <0xfe 0x0 0x0 0x20000000>;
+
+ ranges = <0x2000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>,
+ <0x1000000 0x0 0x8000 0x0 0x18400000 0x0 0x8000>;
+
+ ethernet@3,0 {
+ reg = <0x1800 0x0 0x0 0x0 0x0>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ status = "disabled";
+ };
+
+ ethernet@3,1 {
+ reg = <0x1900 0x0 0x0 0x0 0x0>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ status = "disabled";
+ };
+
+ ethernet@3,2 {
+ reg = <0x1a00 0x0 0x0 0x0 0x0>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ status = "disabled";
+ };
+
+ usb@4,0 {
+ reg = <0x2000 0x0 0x0 0x0 0x0>;
+ interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ status = "disabled";
+ };
+
+ usb@19,0 {
+ reg = <0xc800 0x0 0x0 0x0 0x0>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ status = "disabled";
+ };
+
+ display@6,1 {
+ reg = <0x3100 0x0 0x0 0x0 0x0>;
+ interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ status = "disabled";
+ };
+
+ hda@7,0 {
+ reg = <0x3800 0x0 0x0 0x0 0x0>;
+ interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ status = "disabled";
+ };
+
+ sata: sata@8,0 {
+ reg = <0x4000 0x0 0x0 0x0 0x0>;
+ interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ status = "disabled";
+ };
+
+ pcie@9,0 {
+ reg = <0x4800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&pic>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &pic 32 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@a,0 {
+ reg = <0x5000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&pic>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &pic 33 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@b,0 {
+ reg = <0x5800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&pic>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &pic 34 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@c,0 {
+ reg = <0x6000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&pic>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &pic 35 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@d,0 {
+ reg = <0x6800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&pic>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &pic 36 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@e,0 {
+ reg = <0x7000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&pic>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &pic 37 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@f,0 {
+ reg = <0x7800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&pic>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &pic 40 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@10,0 {
+ reg = <0x8000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&pic>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &pic 30 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+ };
+ };
+};
--
2.39.3
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v2 7/7] LoongArch: Parsing CPU-related information from DTS
2023-08-15 8:50 [PATCH v2 0/7] LoongArch: Add built-in dtb support Binbin Zhou
` (5 preceding siblings ...)
2023-08-15 8:51 ` [PATCH v2 6/7] LoongArch: dts: DeviceTree for Loongson-2K2000 Binbin Zhou
@ 2023-08-15 8:51 ` Binbin Zhou
6 siblings, 0 replies; 23+ messages in thread
From: Binbin Zhou @ 2023-08-15 8:51 UTC (permalink / raw)
To: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree
Cc: Huacai Chen, loongson-kernel, Xuerui Wang, loongarch, Jiaxun Yang,
Hongliang Wang, Binbin Zhou
Generally, we can get cpu-related information, such as model name, from
/proc/cpuinfo. for DT-based systems, we need to parse the relevant
information from DTS.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Signed-off-by: Hongliang Wang <wanghongliang@loongson.cn>
---
arch/loongarch/kernel/env.c | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/loongarch/kernel/env.c b/arch/loongarch/kernel/env.c
index 6b3bfb0092e6..0191fe20b535 100644
--- a/arch/loongarch/kernel/env.c
+++ b/arch/loongarch/kernel/env.c
@@ -5,13 +5,16 @@
* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
*/
#include <linux/acpi.h>
+#include <linux/clk.h>
#include <linux/efi.h>
#include <linux/export.h>
#include <linux/memblock.h>
+#include <linux/of_clk.h>
#include <asm/early_ioremap.h>
#include <asm/bootinfo.h>
#include <asm/loongson.h>
#include <asm/setup.h>
+#include <asm/time.h>
u64 efi_system_table;
struct loongson_system_configuration loongson_sysconf;
@@ -34,9 +37,39 @@ void __init init_environ(void)
efi_system_table = fw_arg2;
}
+static int __init fdt_cpu_clk_init(void)
+{
+ struct clk *clk;
+ struct device_node *np;
+
+ np = of_get_cpu_node(0, NULL);
+ if (!np)
+ return -ENODEV;
+
+ clk = of_clk_get(np, 0);
+ if (IS_ERR(clk))
+ return -ENODEV;
+
+ cpu_clock_freq = clk_get_rate(clk);
+ clk_put(clk);
+
+ return 0;
+}
+late_initcall(fdt_cpu_clk_init);
+
static int __init init_cpu_fullname(void)
{
int cpu;
+ char *prop;
+ struct device_node *root;
+
+ /* Parsing cpuname from DTS model property */
+ root = of_find_node_by_path("/");
+ if (root) {
+ of_property_read_string(root, "model", (const char **)&prop);
+ if (prop)
+ loongson_sysconf.cpuname = strsep(&prop, " ");
+ }
if (loongson_sysconf.cpuname && !strncmp(loongson_sysconf.cpuname, "Loongson", 8)) {
for (cpu = 0; cpu < NR_CPUS; cpu++)
--
2.39.3
^ permalink raw reply related [flat|nested] 23+ messages in thread