From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67E7E1607AC; Wed, 28 Aug 2024 09:11:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724836305; cv=none; b=KyOlZWU46rOz0YbZyowvFfHdFgzSwdlJRBOO1xfZNRqflw9KTx8IPjW947zlC1yEa24WE78lMx531wZGGsgv1kcG1GjfcRBdHS16nq9LgKhER+MDxavZpNaCgPzdH0HBH2wnD/LTYXtb62QNjYqyqh5apYdEW5/9z0zEF3O5gns= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724836305; c=relaxed/simple; bh=0h8O7FJ3DgvgGR17BcBk6wfFWrda7TDSqBbyr2M0Ubw=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=iNLzQ7cpOwZ7shGsSiMJM/4h2Jwgm/GZScaQmiIepJ74lP0m9gT0zWa7HwayJDZ6pfG8PiWcC1uGQU3ABhggZ0PiDDjCTDdyvjOuRQBmZw+Iq6o3HcUCowac5L6qZ2lHL29dqyJHyCigSHV7v1b4KWQbCexGeT722Q5eQ3JXifs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=I+fspJpN; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="I+fspJpN" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A85C5C51EE7; Wed, 28 Aug 2024 09:11:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724836304; bh=0h8O7FJ3DgvgGR17BcBk6wfFWrda7TDSqBbyr2M0Ubw=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=I+fspJpN+ifmm1D7U6v+HSzkaGPjPPilt3HUwEAU722sfeMSp67NFdNXcJ328RMu0 Gnmn14XMc1kBl4uBDrp7yr2Sxo0NUyjeulXLgYK+yWRWwC3+OobBRqULU+kJo19fCR sKlmwH6S2niy9eB4qjMHhtszgWjkrir2/a5UKpnie9YHAhXs6v9RSZKvwr0iZcJrcs uyycCazxcv9GMBurmktEhyW98mbA7XBNn/dlbyUOfNqU9g/d8Z5V/wOkBTyLqfAStG pmWuY/tGOc0UavfTJVDbZjfUlhI7mbQSm95663RfHUt8ssz8hEnR5tN6gL4AdxV8Q1 O5+GzqFq1AvxQ== Message-ID: <0ec92d59-0648-40ed-a522-307152b5c37d@kernel.org> Date: Wed, 28 Aug 2024 11:11:38 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 6/6] arm64: dts: qcom: add base QCS615 RIDE dts To: Lijuan Gao Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , kernel@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20240828-add_initial_support_for_qcs615-v1-0-5599869ea10f@quicinc.com> <20240828-add_initial_support_for_qcs615-v1-6-5599869ea10f@quicinc.com> <22qkvfravm6sxiq3xfavahg2u6b2pwlyzqbqvd55zym5zef3gi@m4bsqkdvggty> <17d0017e-b55d-4b32-9fd3-1a1a84e5ebf9@quicinc.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 28/08/2024 09:54, Lijuan Gao wrote: > > > 在 8/28/2024 2:25 PM, Krzysztof Kozlowski 写道: >> On Wed, Aug 28, 2024 at 10:02:16AM +0800, Lijuan Gao wrote: >>> Add initial support for Qualcomm QCS615 RIDE board and enable >>> the QCS615 RIDE board to shell with dcc console. >>> >>> Signed-off-by: Lijuan Gao >>> --- >>> arch/arm64/boot/dts/qcom/Makefile | 1 + >>> arch/arm64/boot/dts/qcom/qcs615-ride.dts | 15 +++++++++++++++ >>> 2 files changed, 16 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile >>> index 197ab325c0b9..c5503f189847 100644 >>> --- a/arch/arm64/boot/dts/qcom/Makefile >>> +++ b/arch/arm64/boot/dts/qcom/Makefile >>> @@ -110,6 +110,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb >>> +dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb >>> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts >>> new file mode 100644 >>> index 000000000000..31d32ad951b5 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts >>> @@ -0,0 +1,15 @@ >>> +// SPDX-License-Identifier: BSD-3-Clause >>> +/* >>> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. >>> + */ >>> +/dts-v1/; >>> + >>> +#include "qcs615.dtsi" >>> +/ { >>> + model = "Qualcomm Technologies, Inc. QCS615 Ride"; >>> + compatible = "qcom,qcs615-ride", "qcom,qcs615"; >>> + >>> + chosen { >>> + bootargs = "console=hvc0"; >> >> Noooo, last time I agreed on this, you told me later it is different. >> > In the early stages, enabling HVC is to more easily verify clock and > PMIC related functions, as it’s difficult to debug without the console > log. After the clock and PMIC are ready, we will enable the UART console. Working serial is supposed to be part of the early submission. Best regards, Krzysztof