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Mon, 1 Jun 2026 04:27:26 -0500 Received: from [172.24.233.254] (santhoshkumark.dhcp.ti.com [172.24.233.254]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 6519RLwH716951; Mon, 1 Jun 2026 04:27:21 -0500 Message-ID: <0ee42621-f970-451c-82cd-9a1a63ce197e@ti.com> Date: Mon, 1 Jun 2026 14:57:20 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 09/13] spi: cadence-quadspi: reject 2-byte-address DDR ops on PHY-tunable hardware To: Miquel Raynal CC: , , , , , , , , , , , , , , , , References: <20260527175527.2247679-1-s-k6@ti.com> <20260527175527.2247679-10-s-k6@ti.com> <87y0h3gb6o.fsf@bootlin.com> Content-Language: en-US From: Santhosh Kumar K In-Reply-To: <87y0h3gb6o.fsf@bootlin.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000209:EE_|SA2PR10MB4570:EE_ X-MS-Office365-Filtering-Correlation-Id: 0145e690-5cf2-461f-e245-08debfbfff0a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|1800799024|36860700016|3023799007|6133799003|56012099006|4143699003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jpP4M49lk0aFQ9u6I3r+BGQi5vBiJDftD44eu2vTyVq2rnRlRrHL7rvGYkFElOOapUxdcoNBoVTwIZXCmkERsm3DeOVHD+dXijeEEpHkikbVlT1Dbl25qZyoNDMb4ehYo7RYyt7kOjR9yCFJ+ltLgBelMcoDSZfhAbQrTfQYlsLFcGhW/IHGx9z3HQmgV/6lnSJ6EocwHkO0MebKg5OmprvyJ505n7p0hIPNFJaRw432O/iu/VssW7EK84Sx1zyG5LMi8ycAxzyQ3wo1SzYzzfbUGqbPMdbJkChp7qYxchrGfjY9Jm4iI49pBNIfWASnU6jVP1nUlKDwPEM2KX5G77cWA2JERD9mXbPVnaBCT2eYWa8MxU8T4fVxTV47ia0tNM5n+4h2EhoEJw7oOo7SBnY+M68hC0/Fsm1drqFOGkkgy1fzN6vI3BSn7X3kaIow X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Jun 2026 09:27:27.0353 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0145e690-5cf2-461f-e245-08debfbfff0a X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000209.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA2PR10MB4570 Hello Miquel, On 28/05/26 14:31, Miquel Raynal wrote: > On 27/05/2026 at 23:25:23 +0530, Santhosh Kumar K wrote: > >> Erratum i2383 affects the AM654 OSPI controller: in PHY DDR mode, >> operations with a 2-byte address cause an internal state machine to >> mis-compare the transmitted address byte count against 1 instead of 2, >> locking up the address phase. [0] >> >> Add a CQSPI_NO_2BYTE_ADDR_PHY_DDR quirk flag and set it on the am654_ospi >> platform data. In cqspi_supports_mem_op(), when a controller carries this >> quirk and has PHY tuning support, reject DDR operations that use 2-byte >> addressing. >> >> [0] https://www.ti.com/lit/er/sprz544c/sprz544c.pdf >> >> Signed-off-by: Santhosh Kumar K >> --- >> drivers/spi/spi-cadence-quadspi.c | 15 ++++++++++++++- >> 1 file changed, 14 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c >> index 508bc5bc4ab5..72208d376305 100644 >> --- a/drivers/spi/spi-cadence-quadspi.c >> +++ b/drivers/spi/spi-cadence-quadspi.c >> @@ -49,6 +49,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <= SPI_DEVICE_CS_CNT_MAX); >> #define CQSPI_DISABLE_RUNTIME_PM BIT(10) >> #define CQSPI_NO_INDIRECT_MODE BIT(11) >> #define CQSPI_HAS_WR_PROTECT BIT(12) >> +#define CQSPI_NO_2BYTE_ADDR_PHY_DDR BIT(13) >> >> /* Capabilities */ >> #define CQSPI_SUPPORTS_OCTAL BIT(0) >> @@ -1627,6 +1628,18 @@ static bool cqspi_supports_mem_op(struct spi_mem *mem, >> if (op->data.nbytes && op->data.buswidth != 8) >> return false; >> >> + /* >> + * Erratum i2383: In PHY DDR mode, 2-byte addressing causes an >> + * internal state machine to mis-compare the transmitted >> + * address byte count against 1 instead of 2, locking up the >> + * address phase. Reject such ops on controllers that need it. >> + */ >> + if (cqspi->ddata && >> + (cqspi->ddata->quirks & CQSPI_NO_2BYTE_ADDR_PHY_DDR)) { >> + if (op->addr.nbytes == 2 && cqspi->ddata->execute_tuning) >> + return false; >> + } > > I don't think this is a valid approach. What we want is to prevent > tuning in octal DTR mode with 2 bytes addressing, instead of preventing > reads/writes in octal DTR modes after tuning. Have you tried on an AM62A LP > SK? I bet probe fails.. > > The quirk should be handled at the beginning of the tuning procedure, so > we skip tuning entirely in this case. I see your point. However, in my testing on AM62Ax LP SK, the controller and the flash probes and operates correctly in 8S PHY mode. The reason I handled this in supports_op() is that, for these devices, simply skipping tuning when a 2-byte DDR operation is selected may not lead to the best achievable operating point. The performance ordering I measured is: 8S non-PHY < 8D non-PHY < 8S PHY So falling back from 8D PHY to 8D non-PHY would leave performance on the table compared to selecting and tuning an 8S operation. That said, I agree that encoding this as an operation support restriction is probably not the right place to handle it. I'll rework the initialization flow so that operation selection can take PHY-achievable frequencies and controller-specific restrictions such as i2383 into account when choosing the final operations. Let me prototype this approach and will report back with the results. Thanks, Santhosh. > > Thanks, > Miquèl