From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5975347503; Wed, 29 Apr 2026 04:14:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777436066; cv=none; b=dYmZBz89O14nFkpCog+3Mx1tFUaIHhlq/Ge4CT/a0t9ynopalgUrR11TWiEE+1xMWSbhNVN9I69/7hJB6l6pfO0M6EsqcbK25j9cSnQZ/y4FNIC8bl83RnxaNCuVPKOdPPJR1OpoHog0PpJF1VCrtK6OBt3l9xXo44eltmkV10w= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777436066; c=relaxed/simple; bh=0ZwZkqVJrw29/5iaSkv2Pk4a6yjdFhnMUB9Mo7b0o7M=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=Ts/3nDMyr1p3Y+87Wn7Yogj5LiBQnsQweCPmUh+CT9xch9XRK6//TuyU8U/1ggTCMOs3NIHEovnkmeXCv86WAeMDHlZ7T2IVlQBXklbIiYLY7NN/WmAbF8fvLVM6EMeY5aJljNl9sTw+LKU+vHbIVroz68X9igfmZjDeKQk1pbk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LWn5dkda; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LWn5dkda" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 97C5EC19425; Wed, 29 Apr 2026 04:14:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777436066; bh=0ZwZkqVJrw29/5iaSkv2Pk4a6yjdFhnMUB9Mo7b0o7M=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=LWn5dkdaXbwjK8iHaKQk4PW31akmpHACgkfC63R42t66c0jpXYGNcvH3CDfsL69iD GOOfiH3DkKj5ZUwofhlRZtFdj3/aVKKPZ3IiKa6Lsh4tNgqsc7LumLnaUeu6+dE/w1 MV/fX9arnwACG2wGG2ADpVU8HDKdm31kt1RwF4BacZSBT4dnVpe0cVisYWCudVoo3R aPPsLEyyWPgn+Ludvr+nhmFznZgDNS4nFLkUxrjdDVPbzuY96tizEYkLpFtBGnQugr DkFmYYwkWEY5XS26JFMekg0y0kBXMxy7AHLh2UwTW5nBYcxcI26a7GD1azSpBj310D +MpYvn6mEx0uA== Message-ID: <0ee6bf23-17a3-4a7c-93d2-276e97cc3a14@kernel.org> Date: Wed, 29 Apr 2026 05:14:20 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC v3 07/11] clk: qcom: gcc-msm8939: mark Venus core GDSCs as hardware controlled To: Erikas Bitovtas , Vikash Garodia , Dikshita Agarwal , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?Q?Andr=C3=A9_Apitzsch?= , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org References: <20260427-msm8939-venus-rfc-v3-0-288195bb7917@gmail.com> <9kBbj8Jr-f6eqC6XfnJPf3gKQD-3WfzXgzl4KEVKhRZlW2_GftgFBsijqUgEvGcgmeFqPwtVquMmibHUMaR_sQ==@protonmail.internalid> <20260427-msm8939-venus-rfc-v3-7-288195bb7917@gmail.com> Content-Language: en-US From: Bryan O'Donoghue In-Reply-To: <20260427-msm8939-venus-rfc-v3-7-288195bb7917@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 27/04/2026 18:58, Erikas Bitovtas wrote: > Since in downstream kernel VENUS_CORE0_GDSC and VENUS_CORE1_GDSC have a > device tree property "qcom,supports-hw-trigger", add a HW_CTRL flag > to these GDSCs to indicate that they are hardware controlled. > > Venus core clock cannot be enabled if Venus core GDSCs are switched off. > But since they are hardware controlled, they can be switched off at > any moment. Vote for the Venus core clock to enable it later when GDSCs > get turned on. > > Signed-off-by: Erikas Bitovtas > --- > drivers/clk/qcom/gcc-msm8939.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c > index 45193b3d714b..420997b00ae0 100644 > --- a/drivers/clk/qcom/gcc-msm8939.c > +++ b/drivers/clk/qcom/gcc-msm8939.c > @@ -3664,6 +3664,7 @@ static struct clk_branch gcc_venus0_vcodec0_clk = { > > static struct clk_branch gcc_venus0_core0_vcodec0_clk = { > .halt_reg = 0x4c02c, > + .halt_check = BRANCH_HALT_SKIP, > .clkr = { > .enable_reg = 0x4c02c, > .enable_mask = BIT(0), > @@ -3681,6 +3682,7 @@ static struct clk_branch gcc_venus0_core0_vcodec0_clk = { > > static struct clk_branch gcc_venus0_core1_vcodec0_clk = { > .halt_reg = 0x4c034, > + .halt_check = BRANCH_HALT_SKIP, > .clkr = { > .enable_reg = 0x4c034, > .enable_mask = BIT(0), > @@ -3753,6 +3755,7 @@ static struct gdsc venus_core0_gdsc = { > .pd = { > .name = "venus_core0", > }, > + .flags = HW_CTRL, > .pwrsts = PWRSTS_OFF_ON, > }; > > @@ -3761,6 +3764,7 @@ static struct gdsc venus_core1_gdsc = { > .pd = { > .name = "venus_core1", > }, > + .flags = HW_CTRL, > .pwrsts = PWRSTS_OFF_ON, > }; > > > -- > 2.54.0 > The downstream opts to put the GDSC under hw control, which is not the same thing as it being under hw control, its up to you to put it under hw control. So you might want to be more conservative especially given you have a problem getting the encoder and decoder to run simultaneously - I might try parking this patch and then see what happens. --- bod