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[81.204.249.205]) by smtp.gmail.com with ESMTPSA id dk21-20020a0564021d9500b0041b501eab8csm2414432edb.57.2022.04.02.05.20.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 02 Apr 2022 05:20:03 -0700 (PDT) Message-ID: <0eed395b-ca02-2308-a5c6-7c4a72720175@gmail.com> Date: Sat, 2 Apr 2022 14:20:02 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Subject: Re: [PATCH v3 1/2] dt-bindings: clock: convert rockchip,rk3188-cru.txt to YAML Content-Language: en-US To: Krzysztof Kozlowski , =?UTF-8?Q?Heiko_St=c3=bcbner?= , zhangqing@rock-chips.com, Stephen Boyd Cc: robh+dt@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org References: <20220329111323.3569-1-jbx6244@gmail.com> <20220331225134.7A0A9C340ED@smtp.kernel.org> <3107512.vfdyTQepKt@diego> <7c786619-6fcf-21dd-8e5a-0ec67da2a63d@gmail.com> <5e1b6c09-0a8f-f1d9-728b-90ffbaedae83@linaro.org> From: Johan Jonker In-Reply-To: <5e1b6c09-0a8f-f1d9-728b-90ffbaedae83@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 4/2/22 14:16, Krzysztof Kozlowski wrote: > On 02/04/2022 13:45, Johan Jonker wrote: >> >> >> On 4/2/22 13:41, Krzysztof Kozlowski wrote: >>> On 01/04/2022 09:55, Heiko Stübner wrote: >>>> Hi Stephen, >>>> >>>> Am Freitag, 1. April 2022, 00:51:32 CEST schrieb Stephen Boyd: >>>>> Quoting Johan Jonker (2022-03-29 04:13:22) >>>>>> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.yaml >>>>>> new file mode 100644 >>>>>> index 000000000..ddd7e46af >>>>>> --- /dev/null >>>>>> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.yaml >>>>>> @@ -0,0 +1,78 @@ >>>>>> +# SPDX-License-Identifier: GPL-2.0 >>>>>> +%YAML 1.2 >>>>>> +--- >>>>>> +$id: http://devicetree.org/schemas/clock/rockchip,rk3188-cru.yaml# >>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>>>> + >>>>>> +title: Rockchip RK3188/RK3066 Clock and Reset Unit (CRU) >>>>>> + >>>>>> +maintainers: >>>>>> + - Elaine Zhang >>>>>> + - Heiko Stuebner >>>>>> + >>>>>> +description: | >>>>>> + The RK3188/RK3066 clock controller generates and supplies clocks to various >>>>>> + controllers within the SoC and also implements a reset controller for SoC >>>>>> + peripherals. >>>>>> + Each clock is assigned an identifier and client nodes can use this identifier >>>>>> + to specify the clock which they consume. All available clocks are defined as >>>>>> + preprocessor macros in the dt-bindings/clock/rk3188-cru.h and >>>>>> + dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources. >>>>>> + Similar macros exist for the reset sources in these files. >>>>>> + There are several clocks that are generated outside the SoC. It is expected >>>>>> + that they are defined using standard clock bindings with following >>>>>> + clock-output-names: >>>>>> + - "xin24m" - crystal input - required >>>>>> + - "xin32k" - RTC clock - optional >>>>>> + - "xin27m" - 27mhz crystal input on RK3066 - optional >>>>>> + - "ext_hsadc" - external HSADC clock - optional >>>>>> + - "ext_cif0" - external camera clock - optional >>>>>> + - "ext_rmii" - external RMII clock - optional >>>>>> + - "ext_jtag" - external JTAG clock - optional >>>>> >>>>> I'd expect all these clks here to be inputs to this node. >>>> >>>> The optional clocks are all part of a circular dependency. >>>> >>>> So for example xin32k normally is generated by the pmic and fed >>>> back into the system, so to get xin32k, we need the pmic to probe, >>>> which needs i2c, which in turn already needs the clock controller. >>> >>> Are you sure that xin32k (RTC) clock should be input to the clock >>> controller? I would expect it is the input to the SoC RTC block, so >>> there is no circular dependency. >> >> clk-rk3188.c: >> >> PNAME(mux_pll_p) = { "xin24m", "xin32k" }; > > Thanks, but that's not the answer whether it is an input to the clock > controller. It's the answer how the driver implements this. :) PX2 == rk3066 Rockchip PX2 TRM V1.0.pdf page 30 Chip Clock Architecture Diagram 1 > > Best regards, > Krzysztof